1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __LINUX_GPIO_DRIVER_H |
3 | #define __LINUX_GPIO_DRIVER_H |
4 | |
5 | #include <linux/bits.h> |
6 | #include <linux/cleanup.h> |
7 | #include <linux/err.h> |
8 | #include <linux/irqchip/chained_irq.h> |
9 | #include <linux/irqdomain.h> |
10 | #include <linux/irqhandler.h> |
11 | #include <linux/lockdep.h> |
12 | #include <linux/pinctrl/pinconf-generic.h> |
13 | #include <linux/pinctrl/pinctrl.h> |
14 | #include <linux/property.h> |
15 | #include <linux/spinlock_types.h> |
16 | #include <linux/types.h> |
17 | |
18 | #ifdef CONFIG_GENERIC_MSI_IRQ |
19 | #include <asm/msi.h> |
20 | #endif |
21 | |
22 | struct device; |
23 | struct irq_chip; |
24 | struct irq_data; |
25 | struct module; |
26 | struct of_phandle_args; |
27 | struct pinctrl_dev; |
28 | struct seq_file; |
29 | |
30 | struct gpio_chip; |
31 | struct gpio_desc; |
32 | struct gpio_device; |
33 | |
34 | enum gpio_lookup_flags; |
35 | enum gpiod_flags; |
36 | |
37 | union gpio_irq_fwspec { |
38 | struct irq_fwspec fwspec; |
39 | #ifdef CONFIG_GENERIC_MSI_IRQ |
40 | msi_alloc_info_t msiinfo; |
41 | #endif |
42 | }; |
43 | |
44 | #define GPIO_LINE_DIRECTION_IN 1 |
45 | #define GPIO_LINE_DIRECTION_OUT 0 |
46 | |
47 | /** |
48 | * struct gpio_irq_chip - GPIO interrupt controller |
49 | */ |
50 | struct gpio_irq_chip { |
51 | /** |
52 | * @chip: |
53 | * |
54 | * GPIO IRQ chip implementation, provided by GPIO driver. |
55 | */ |
56 | struct irq_chip *chip; |
57 | |
58 | /** |
59 | * @domain: |
60 | * |
61 | * Interrupt translation domain; responsible for mapping between GPIO |
62 | * hwirq number and Linux IRQ number. |
63 | */ |
64 | struct irq_domain *domain; |
65 | |
66 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
67 | /** |
68 | * @fwnode: |
69 | * |
70 | * Firmware node corresponding to this gpiochip/irqchip, necessary |
71 | * for hierarchical irqdomain support. |
72 | */ |
73 | struct fwnode_handle *fwnode; |
74 | |
75 | /** |
76 | * @parent_domain: |
77 | * |
78 | * If non-NULL, will be set as the parent of this GPIO interrupt |
79 | * controller's IRQ domain to establish a hierarchical interrupt |
80 | * domain. The presence of this will activate the hierarchical |
81 | * interrupt support. |
82 | */ |
83 | struct irq_domain *parent_domain; |
84 | |
85 | /** |
86 | * @child_to_parent_hwirq: |
87 | * |
88 | * This callback translates a child hardware IRQ offset to a parent |
89 | * hardware IRQ offset on a hierarchical interrupt chip. The child |
90 | * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the |
91 | * ngpio field of struct gpio_chip) and the corresponding parent |
92 | * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by |
93 | * the driver. The driver can calculate this from an offset or using |
94 | * a lookup table or whatever method is best for this chip. Return |
95 | * 0 on successful translation in the driver. |
96 | * |
97 | * If some ranges of hardware IRQs do not have a corresponding parent |
98 | * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and |
99 | * @need_valid_mask to make these GPIO lines unavailable for |
100 | * translation. |
101 | */ |
102 | int (*child_to_parent_hwirq)(struct gpio_chip *gc, |
103 | unsigned int child_hwirq, |
104 | unsigned int child_type, |
105 | unsigned int *parent_hwirq, |
106 | unsigned int *parent_type); |
107 | |
108 | /** |
109 | * @populate_parent_alloc_arg : |
110 | * |
111 | * This optional callback allocates and populates the specific struct |
112 | * for the parent's IRQ domain. If this is not specified, then |
113 | * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell |
114 | * variant named &gpiochip_populate_parent_fwspec_fourcell is also |
115 | * available. |
116 | */ |
117 | int (*populate_parent_alloc_arg)(struct gpio_chip *gc, |
118 | union gpio_irq_fwspec *fwspec, |
119 | unsigned int parent_hwirq, |
120 | unsigned int parent_type); |
121 | |
122 | /** |
123 | * @child_offset_to_irq: |
124 | * |
125 | * This optional callback is used to translate the child's GPIO line |
126 | * offset on the GPIO chip to an IRQ number for the GPIO to_irq() |
127 | * callback. If this is not specified, then a default callback will be |
128 | * provided that returns the line offset. |
129 | */ |
130 | unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, |
131 | unsigned int pin); |
132 | |
133 | /** |
134 | * @child_irq_domain_ops: |
135 | * |
136 | * The IRQ domain operations that will be used for this GPIO IRQ |
137 | * chip. If no operations are provided, then default callbacks will |
138 | * be populated to setup the IRQ hierarchy. Some drivers need to |
139 | * supply their own translate function. |
140 | */ |
141 | struct irq_domain_ops child_irq_domain_ops; |
142 | #endif |
143 | |
144 | /** |
145 | * @handler: |
146 | * |
147 | * The IRQ handler to use (often a predefined IRQ core function) for |
148 | * GPIO IRQs, provided by GPIO driver. |
149 | */ |
150 | irq_flow_handler_t handler; |
151 | |
152 | /** |
153 | * @default_type: |
154 | * |
155 | * Default IRQ triggering type applied during GPIO driver |
156 | * initialization, provided by GPIO driver. |
157 | */ |
158 | unsigned int default_type; |
159 | |
160 | /** |
161 | * @lock_key: |
162 | * |
163 | * Per GPIO IRQ chip lockdep class for IRQ lock. |
164 | */ |
165 | struct lock_class_key *lock_key; |
166 | |
167 | /** |
168 | * @request_key: |
169 | * |
170 | * Per GPIO IRQ chip lockdep class for IRQ request. |
171 | */ |
172 | struct lock_class_key *request_key; |
173 | |
174 | /** |
175 | * @parent_handler: |
176 | * |
177 | * The interrupt handler for the GPIO chip's parent interrupts, may be |
178 | * NULL if the parent interrupts are nested rather than cascaded. |
179 | */ |
180 | irq_flow_handler_t parent_handler; |
181 | |
182 | union { |
183 | /** |
184 | * @parent_handler_data: |
185 | * |
186 | * If @per_parent_data is false, @parent_handler_data is a |
187 | * single pointer used as the data associated with every |
188 | * parent interrupt. |
189 | */ |
190 | void *parent_handler_data; |
191 | |
192 | /** |
193 | * @parent_handler_data_array: |
194 | * |
195 | * If @per_parent_data is true, @parent_handler_data_array is |
196 | * an array of @num_parents pointers, and is used to associate |
197 | * different data for each parent. This cannot be NULL if |
198 | * @per_parent_data is true. |
199 | */ |
200 | void **parent_handler_data_array; |
201 | }; |
202 | |
203 | /** |
204 | * @num_parents: |
205 | * |
206 | * The number of interrupt parents of a GPIO chip. |
207 | */ |
208 | unsigned int num_parents; |
209 | |
210 | /** |
211 | * @parents: |
212 | * |
213 | * A list of interrupt parents of a GPIO chip. This is owned by the |
214 | * driver, so the core will only reference this list, not modify it. |
215 | */ |
216 | unsigned int *parents; |
217 | |
218 | /** |
219 | * @map: |
220 | * |
221 | * A list of interrupt parents for each line of a GPIO chip. |
222 | */ |
223 | unsigned int *map; |
224 | |
225 | /** |
226 | * @threaded: |
227 | * |
228 | * True if set the interrupt handling uses nested threads. |
229 | */ |
230 | bool threaded; |
231 | |
232 | /** |
233 | * @per_parent_data: |
234 | * |
235 | * True if parent_handler_data_array describes a @num_parents |
236 | * sized array to be used as parent data. |
237 | */ |
238 | bool per_parent_data; |
239 | |
240 | /** |
241 | * @initialized: |
242 | * |
243 | * Flag to track GPIO chip irq member's initialization. |
244 | * This flag will make sure GPIO chip irq members are not used |
245 | * before they are initialized. |
246 | */ |
247 | bool initialized; |
248 | |
249 | /** |
250 | * @domain_is_allocated_externally: |
251 | * |
252 | * True it the irq_domain was allocated outside of gpiolib, in which |
253 | * case gpiolib won't free the irq_domain itself. |
254 | */ |
255 | bool domain_is_allocated_externally; |
256 | |
257 | /** |
258 | * @init_hw: optional routine to initialize hardware before |
259 | * an IRQ chip will be added. This is quite useful when |
260 | * a particular driver wants to clear IRQ related registers |
261 | * in order to avoid undesired events. |
262 | */ |
263 | int (*init_hw)(struct gpio_chip *gc); |
264 | |
265 | /** |
266 | * @init_valid_mask: optional routine to initialize @valid_mask, to be |
267 | * used if not all GPIO lines are valid interrupts. Sometimes some |
268 | * lines just cannot fire interrupts, and this routine, when defined, |
269 | * is passed a bitmap in "valid_mask" and it will have ngpios |
270 | * bits from 0..(ngpios-1) set to "1" as in valid. The callback can |
271 | * then directly set some bits to "0" if they cannot be used for |
272 | * interrupts. |
273 | */ |
274 | void (*init_valid_mask)(struct gpio_chip *gc, |
275 | unsigned long *valid_mask, |
276 | unsigned int ngpios); |
277 | |
278 | /** |
279 | * @valid_mask: |
280 | * |
281 | * If not %NULL, holds bitmask of GPIOs which are valid to be included |
282 | * in IRQ domain of the chip. |
283 | */ |
284 | unsigned long *valid_mask; |
285 | |
286 | /** |
287 | * @first: |
288 | * |
289 | * Required for static IRQ allocation. If set, irq_domain_add_simple() |
290 | * will allocate and map all IRQs during initialization. |
291 | */ |
292 | unsigned int first; |
293 | |
294 | /** |
295 | * @irq_enable: |
296 | * |
297 | * Store old irq_chip irq_enable callback |
298 | */ |
299 | void (*irq_enable)(struct irq_data *data); |
300 | |
301 | /** |
302 | * @irq_disable: |
303 | * |
304 | * Store old irq_chip irq_disable callback |
305 | */ |
306 | void (*irq_disable)(struct irq_data *data); |
307 | /** |
308 | * @irq_unmask: |
309 | * |
310 | * Store old irq_chip irq_unmask callback |
311 | */ |
312 | void (*irq_unmask)(struct irq_data *data); |
313 | |
314 | /** |
315 | * @irq_mask: |
316 | * |
317 | * Store old irq_chip irq_mask callback |
318 | */ |
319 | void (*irq_mask)(struct irq_data *data); |
320 | }; |
321 | |
322 | /** |
323 | * struct gpio_chip - abstract a GPIO controller |
324 | * @label: a functional name for the GPIO device, such as a part |
325 | * number or the name of the SoC IP-block implementing it. |
326 | * @gpiodev: the internal state holder, opaque struct |
327 | * @parent: optional parent device providing the GPIOs |
328 | * @fwnode: optional fwnode providing this controller's properties |
329 | * @owner: helps prevent removal of modules exporting active GPIOs |
330 | * @request: optional hook for chip-specific activation, such as |
331 | * enabling module power and clock; may sleep |
332 | * @free: optional hook for chip-specific deactivation, such as |
333 | * disabling module power and clock; may sleep |
334 | * @get_direction: returns direction for signal "offset", 0=out, 1=in, |
335 | * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), |
336 | * or negative error. It is recommended to always implement this |
337 | * function, even on input-only or output-only gpio chips. |
338 | * @direction_input: configures signal "offset" as input, or returns error |
339 | * This can be omitted on input-only or output-only gpio chips. |
340 | * @direction_output: configures signal "offset" as output, or returns error |
341 | * This can be omitted on input-only or output-only gpio chips. |
342 | * @get: returns value for signal "offset", 0=low, 1=high, or negative error |
343 | * @get_multiple: reads values for multiple signals defined by "mask" and |
344 | * stores them in "bits", returns 0 on success or negative error |
345 | * @set: assigns output value for signal "offset" |
346 | * @set_multiple: assigns output values for multiple signals defined by "mask" |
347 | * @set_config: optional hook for all kinds of settings. Uses the same |
348 | * packed config format as generic pinconf. |
349 | * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; |
350 | * implementation may not sleep |
351 | * @dbg_show: optional routine to show contents in debugfs; default code |
352 | * will be used when this is omitted, but custom code can show extra |
353 | * state (such as pullup/pulldown configuration). |
354 | * @init_valid_mask: optional routine to initialize @valid_mask, to be used if |
355 | * not all GPIOs are valid. |
356 | * @add_pin_ranges: optional routine to initialize pin ranges, to be used when |
357 | * requires special mapping of the pins that provides GPIO functionality. |
358 | * It is called after adding GPIO chip and before adding IRQ chip. |
359 | * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to |
360 | * enable hardware timestamp. |
361 | * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to |
362 | * disable hardware timestamp. |
363 | * @base: identifies the first GPIO number handled by this chip; |
364 | * or, if negative during registration, requests dynamic ID allocation. |
365 | * DEPRECATION: providing anything non-negative and nailing the base |
366 | * offset of GPIO chips is deprecated. Please pass -1 as base to |
367 | * let gpiolib select the chip base in all possible cases. We want to |
368 | * get rid of the static GPIO number space in the long run. |
369 | * @ngpio: the number of GPIOs handled by this controller; the last GPIO |
370 | * handled is (base + ngpio - 1). |
371 | * @offset: when multiple gpio chips belong to the same device this |
372 | * can be used as offset within the device so friendly names can |
373 | * be properly assigned. |
374 | * @names: if set, must be an array of strings to use as alternative |
375 | * names for the GPIOs in this chip. Any entry in the array |
376 | * may be NULL if there is no alias for the GPIO, however the |
377 | * array must be @ngpio entries long. A name can include a single printk |
378 | * format specifier for an unsigned int. It is substituted by the actual |
379 | * number of the gpio. |
380 | * @can_sleep: flag must be set iff get()/set() methods sleep, as they |
381 | * must while accessing GPIO expander chips over I2C or SPI. This |
382 | * implies that if the chip supports IRQs, these IRQs need to be threaded |
383 | * as the chip access may sleep when e.g. reading out the IRQ status |
384 | * registers. |
385 | * @read_reg: reader function for generic GPIO |
386 | * @write_reg: writer function for generic GPIO |
387 | * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing |
388 | * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the |
389 | * generic GPIO core. It is for internal housekeeping only. |
390 | * @reg_dat: data (in) register for generic GPIO |
391 | * @reg_set: output set register (out=high) for generic GPIO |
392 | * @reg_clr: output clear register (out=low) for generic GPIO |
393 | * @reg_dir_out: direction out setting register for generic GPIO |
394 | * @reg_dir_in: direction in setting register for generic GPIO |
395 | * @bgpio_dir_unreadable: indicates that the direction register(s) cannot |
396 | * be read and we need to rely on out internal state tracking. |
397 | * @bgpio_bits: number of register bits used for a generic GPIO i.e. |
398 | * <register width> * 8 |
399 | * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep |
400 | * shadowed and real data registers writes together. |
401 | * @bgpio_data: shadowed data register for generic GPIO to clear/set bits |
402 | * safely. |
403 | * @bgpio_dir: shadowed direction register for generic GPIO to clear/set |
404 | * direction safely. A "1" in this word means the line is set as |
405 | * output. |
406 | * |
407 | * A gpio_chip can help platforms abstract various sources of GPIOs so |
408 | * they can all be accessed through a common programming interface. |
409 | * Example sources would be SOC controllers, FPGAs, multifunction |
410 | * chips, dedicated GPIO expanders, and so on. |
411 | * |
412 | * Each chip controls a number of signals, identified in method calls |
413 | * by "offset" values in the range 0..(@ngpio - 1). When those signals |
414 | * are referenced through calls like gpio_get_value(gpio), the offset |
415 | * is calculated by subtracting @base from the gpio number. |
416 | */ |
417 | struct gpio_chip { |
418 | const char *label; |
419 | struct gpio_device *gpiodev; |
420 | struct device *parent; |
421 | struct fwnode_handle *fwnode; |
422 | struct module *owner; |
423 | |
424 | int (*request)(struct gpio_chip *gc, |
425 | unsigned int offset); |
426 | void (*free)(struct gpio_chip *gc, |
427 | unsigned int offset); |
428 | int (*get_direction)(struct gpio_chip *gc, |
429 | unsigned int offset); |
430 | int (*direction_input)(struct gpio_chip *gc, |
431 | unsigned int offset); |
432 | int (*direction_output)(struct gpio_chip *gc, |
433 | unsigned int offset, int value); |
434 | int (*get)(struct gpio_chip *gc, |
435 | unsigned int offset); |
436 | int (*get_multiple)(struct gpio_chip *gc, |
437 | unsigned long *mask, |
438 | unsigned long *bits); |
439 | void (*set)(struct gpio_chip *gc, |
440 | unsigned int offset, int value); |
441 | void (*set_multiple)(struct gpio_chip *gc, |
442 | unsigned long *mask, |
443 | unsigned long *bits); |
444 | int (*set_config)(struct gpio_chip *gc, |
445 | unsigned int offset, |
446 | unsigned long config); |
447 | int (*to_irq)(struct gpio_chip *gc, |
448 | unsigned int offset); |
449 | |
450 | void (*dbg_show)(struct seq_file *s, |
451 | struct gpio_chip *gc); |
452 | |
453 | int (*init_valid_mask)(struct gpio_chip *gc, |
454 | unsigned long *valid_mask, |
455 | unsigned int ngpios); |
456 | |
457 | int (*add_pin_ranges)(struct gpio_chip *gc); |
458 | |
459 | int (*en_hw_timestamp)(struct gpio_chip *gc, |
460 | u32 offset, |
461 | unsigned long flags); |
462 | int (*dis_hw_timestamp)(struct gpio_chip *gc, |
463 | u32 offset, |
464 | unsigned long flags); |
465 | int base; |
466 | u16 ngpio; |
467 | u16 offset; |
468 | const char *const *names; |
469 | bool can_sleep; |
470 | |
471 | #if IS_ENABLED(CONFIG_GPIO_GENERIC) |
472 | unsigned long (*read_reg)(void __iomem *reg); |
473 | void (*write_reg)(void __iomem *reg, unsigned long data); |
474 | bool be_bits; |
475 | void __iomem *reg_dat; |
476 | void __iomem *reg_set; |
477 | void __iomem *reg_clr; |
478 | void __iomem *reg_dir_out; |
479 | void __iomem *reg_dir_in; |
480 | bool bgpio_dir_unreadable; |
481 | int bgpio_bits; |
482 | raw_spinlock_t bgpio_lock; |
483 | unsigned long bgpio_data; |
484 | unsigned long bgpio_dir; |
485 | #endif /* CONFIG_GPIO_GENERIC */ |
486 | |
487 | #ifdef CONFIG_GPIOLIB_IRQCHIP |
488 | /* |
489 | * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib |
490 | * to handle IRQs for most practical cases. |
491 | */ |
492 | |
493 | /** |
494 | * @irq: |
495 | * |
496 | * Integrates interrupt chip functionality with the GPIO chip. Can be |
497 | * used to handle IRQs for most practical cases. |
498 | */ |
499 | struct gpio_irq_chip irq; |
500 | #endif /* CONFIG_GPIOLIB_IRQCHIP */ |
501 | |
502 | /** |
503 | * @valid_mask: |
504 | * |
505 | * If not %NULL, holds bitmask of GPIOs which are valid to be used |
506 | * from the chip. |
507 | */ |
508 | unsigned long *valid_mask; |
509 | |
510 | #if defined(CONFIG_OF_GPIO) |
511 | /* |
512 | * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in |
513 | * the device tree automatically may have an OF translation |
514 | */ |
515 | |
516 | /** |
517 | * @of_gpio_n_cells: |
518 | * |
519 | * Number of cells used to form the GPIO specifier. |
520 | */ |
521 | unsigned int of_gpio_n_cells; |
522 | |
523 | /** |
524 | * @of_xlate: |
525 | * |
526 | * Callback to translate a device tree GPIO specifier into a chip- |
527 | * relative GPIO number and flags. |
528 | */ |
529 | int (*of_xlate)(struct gpio_chip *gc, |
530 | const struct of_phandle_args *gpiospec, u32 *flags); |
531 | #endif /* CONFIG_OF_GPIO */ |
532 | }; |
533 | |
534 | const char *gpiochip_is_requested(struct gpio_chip *gc, unsigned int offset); |
535 | |
536 | /** |
537 | * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range |
538 | * @chip: the chip to query |
539 | * @i: loop variable |
540 | * @base: first GPIO in the range |
541 | * @size: amount of GPIOs to check starting from @base |
542 | * @label: label of current GPIO |
543 | */ |
544 | #define for_each_requested_gpio_in_range(chip, i, base, size, label) \ |
545 | for (i = 0; i < size; i++) \ |
546 | if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else |
547 | |
548 | /* Iterates over all requested GPIO of the given @chip */ |
549 | #define for_each_requested_gpio(chip, i, label) \ |
550 | for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) |
551 | |
552 | /* add/remove chips */ |
553 | int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, |
554 | struct lock_class_key *lock_key, |
555 | struct lock_class_key *request_key); |
556 | |
557 | /** |
558 | * gpiochip_add_data() - register a gpio_chip |
559 | * @gc: the chip to register, with gc->base initialized |
560 | * @data: driver-private data associated with this chip |
561 | * |
562 | * Context: potentially before irqs will work |
563 | * |
564 | * When gpiochip_add_data() is called very early during boot, so that GPIOs |
565 | * can be freely used, the gc->parent device must be registered before |
566 | * the gpio framework's arch_initcall(). Otherwise sysfs initialization |
567 | * for GPIOs will fail rudely. |
568 | * |
569 | * gpiochip_add_data() must only be called after gpiolib initialization, |
570 | * i.e. after core_initcall(). |
571 | * |
572 | * If gc->base is negative, this requests dynamic assignment of |
573 | * a range of valid GPIOs. |
574 | * |
575 | * Returns: |
576 | * A negative errno if the chip can't be registered, such as because the |
577 | * gc->base is invalid or already associated with a different chip. |
578 | * Otherwise it returns zero as a success code. |
579 | */ |
580 | #ifdef CONFIG_LOCKDEP |
581 | #define gpiochip_add_data(gc, data) ({ \ |
582 | static struct lock_class_key lock_key; \ |
583 | static struct lock_class_key request_key; \ |
584 | gpiochip_add_data_with_key(gc, data, &lock_key, \ |
585 | &request_key); \ |
586 | }) |
587 | #define devm_gpiochip_add_data(dev, gc, data) ({ \ |
588 | static struct lock_class_key lock_key; \ |
589 | static struct lock_class_key request_key; \ |
590 | devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ |
591 | &request_key); \ |
592 | }) |
593 | #else |
594 | #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) |
595 | #define devm_gpiochip_add_data(dev, gc, data) \ |
596 | devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) |
597 | #endif /* CONFIG_LOCKDEP */ |
598 | |
599 | static inline int gpiochip_add(struct gpio_chip *gc) |
600 | { |
601 | return gpiochip_add_data(gc, NULL); |
602 | } |
603 | void gpiochip_remove(struct gpio_chip *gc); |
604 | int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, |
605 | void *data, struct lock_class_key *lock_key, |
606 | struct lock_class_key *request_key); |
607 | |
608 | struct gpio_device *gpio_device_find(void *data, |
609 | int (*match)(struct gpio_chip *gc, void *data)); |
610 | struct gpio_device *gpio_device_find_by_label(const char *label); |
611 | struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode); |
612 | |
613 | struct gpio_device *gpio_device_get(struct gpio_device *gdev); |
614 | void gpio_device_put(struct gpio_device *gdev); |
615 | |
616 | DEFINE_FREE(gpio_device_put, struct gpio_device *, |
617 | if (IS_ERR_OR_NULL(_T)) gpio_device_put(_T)); |
618 | |
619 | struct device *gpio_device_to_device(struct gpio_device *gdev); |
620 | |
621 | bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); |
622 | int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); |
623 | void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); |
624 | void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); |
625 | void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); |
626 | |
627 | /* irq_data versions of the above */ |
628 | int gpiochip_irq_reqres(struct irq_data *data); |
629 | void gpiochip_irq_relres(struct irq_data *data); |
630 | |
631 | /* Paste this in your irq_chip structure */ |
632 | #define GPIOCHIP_IRQ_RESOURCE_HELPERS \ |
633 | .irq_request_resources = gpiochip_irq_reqres, \ |
634 | .irq_release_resources = gpiochip_irq_relres |
635 | |
636 | static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, |
637 | const struct irq_chip *chip) |
638 | { |
639 | /* Yes, dropping const is ugly, but it isn't like we have a choice */ |
640 | girq->chip = (struct irq_chip *)chip; |
641 | } |
642 | |
643 | /* Line status inquiry for drivers */ |
644 | bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); |
645 | bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); |
646 | |
647 | /* Sleep persistence inquiry for drivers */ |
648 | bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); |
649 | bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); |
650 | |
651 | /* get driver data */ |
652 | void *gpiochip_get_data(struct gpio_chip *gc); |
653 | |
654 | struct bgpio_pdata { |
655 | const char *label; |
656 | int base; |
657 | int ngpio; |
658 | }; |
659 | |
660 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
661 | |
662 | int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, |
663 | union gpio_irq_fwspec *gfwspec, |
664 | unsigned int parent_hwirq, |
665 | unsigned int parent_type); |
666 | int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, |
667 | union gpio_irq_fwspec *gfwspec, |
668 | unsigned int parent_hwirq, |
669 | unsigned int parent_type); |
670 | |
671 | #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
672 | |
673 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
674 | unsigned long sz, void __iomem *dat, void __iomem *set, |
675 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, |
676 | unsigned long flags); |
677 | |
678 | #define BGPIOF_BIG_ENDIAN BIT(0) |
679 | #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ |
680 | #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ |
681 | #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) |
682 | #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ |
683 | #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ |
684 | #define BGPIOF_NO_SET_ON_INPUT BIT(6) |
685 | |
686 | int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, |
687 | irq_hw_number_t hwirq); |
688 | void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); |
689 | |
690 | int gpiochip_irq_domain_activate(struct irq_domain *domain, |
691 | struct irq_data *data, bool reserve); |
692 | void gpiochip_irq_domain_deactivate(struct irq_domain *domain, |
693 | struct irq_data *data); |
694 | |
695 | bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc, |
696 | unsigned int offset); |
697 | |
698 | #ifdef CONFIG_GPIOLIB_IRQCHIP |
699 | int gpiochip_irqchip_add_domain(struct gpio_chip *gc, |
700 | struct irq_domain *domain); |
701 | #else |
702 | |
703 | #include <asm/bug.h> |
704 | #include <asm/errno.h> |
705 | |
706 | static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, |
707 | struct irq_domain *domain) |
708 | { |
709 | WARN_ON(1); |
710 | return -EINVAL; |
711 | } |
712 | #endif |
713 | |
714 | int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); |
715 | void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); |
716 | int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, |
717 | unsigned long config); |
718 | |
719 | /** |
720 | * struct gpio_pin_range - pin range controlled by a gpio chip |
721 | * @node: list for maintaining set of pin ranges, used internally |
722 | * @pctldev: pinctrl device which handles corresponding pins |
723 | * @range: actual range of pins controlled by a gpio controller |
724 | */ |
725 | struct gpio_pin_range { |
726 | struct list_head node; |
727 | struct pinctrl_dev *pctldev; |
728 | struct pinctrl_gpio_range range; |
729 | }; |
730 | |
731 | #ifdef CONFIG_PINCTRL |
732 | |
733 | int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, |
734 | unsigned int gpio_offset, unsigned int pin_offset, |
735 | unsigned int npins); |
736 | int gpiochip_add_pingroup_range(struct gpio_chip *gc, |
737 | struct pinctrl_dev *pctldev, |
738 | unsigned int gpio_offset, const char *pin_group); |
739 | void gpiochip_remove_pin_ranges(struct gpio_chip *gc); |
740 | |
741 | #else /* ! CONFIG_PINCTRL */ |
742 | |
743 | static inline int |
744 | gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, |
745 | unsigned int gpio_offset, unsigned int pin_offset, |
746 | unsigned int npins) |
747 | { |
748 | return 0; |
749 | } |
750 | static inline int |
751 | gpiochip_add_pingroup_range(struct gpio_chip *gc, |
752 | struct pinctrl_dev *pctldev, |
753 | unsigned int gpio_offset, const char *pin_group) |
754 | { |
755 | return 0; |
756 | } |
757 | |
758 | static inline void |
759 | gpiochip_remove_pin_ranges(struct gpio_chip *gc) |
760 | { |
761 | } |
762 | |
763 | #endif /* CONFIG_PINCTRL */ |
764 | |
765 | struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, |
766 | unsigned int hwnum, |
767 | const char *label, |
768 | enum gpio_lookup_flags lflags, |
769 | enum gpiod_flags dflags); |
770 | void gpiochip_free_own_desc(struct gpio_desc *desc); |
771 | |
772 | struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, unsigned int hwnum); |
773 | struct gpio_desc * |
774 | gpio_device_get_desc(struct gpio_device *gdev, unsigned int hwnum); |
775 | |
776 | struct gpio_chip *gpio_device_get_chip(struct gpio_device *gdev); |
777 | |
778 | #ifdef CONFIG_GPIOLIB |
779 | |
780 | /* lock/unlock as IRQ */ |
781 | int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); |
782 | void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); |
783 | |
784 | struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); |
785 | struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc); |
786 | |
787 | /* struct gpio_device getters */ |
788 | int gpio_device_get_base(struct gpio_device *gdev); |
789 | |
790 | #else /* CONFIG_GPIOLIB */ |
791 | |
792 | #include <linux/err.h> |
793 | |
794 | #include <asm/bug.h> |
795 | |
796 | static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) |
797 | { |
798 | /* GPIO can never have been requested */ |
799 | WARN_ON(1); |
800 | return ERR_PTR(-ENODEV); |
801 | } |
802 | |
803 | static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, |
804 | unsigned int offset) |
805 | { |
806 | WARN_ON(1); |
807 | return -EINVAL; |
808 | } |
809 | |
810 | static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, |
811 | unsigned int offset) |
812 | { |
813 | WARN_ON(1); |
814 | } |
815 | #endif /* CONFIG_GPIOLIB */ |
816 | |
817 | #define for_each_gpiochip_node(dev, child) \ |
818 | device_for_each_child_node(dev, child) \ |
819 | if (!fwnode_property_present(child, "gpio-controller")) {} else |
820 | |
821 | static inline unsigned int gpiochip_node_count(struct device *dev) |
822 | { |
823 | struct fwnode_handle *child; |
824 | unsigned int count = 0; |
825 | |
826 | for_each_gpiochip_node(dev, child) |
827 | count++; |
828 | |
829 | return count; |
830 | } |
831 | |
832 | static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev) |
833 | { |
834 | struct fwnode_handle *fwnode; |
835 | |
836 | for_each_gpiochip_node(dev, fwnode) |
837 | return fwnode; |
838 | |
839 | return NULL; |
840 | } |
841 | |
842 | #endif /* __LINUX_GPIO_DRIVER_H */ |
843 | |