1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * max77686-private.h - Voltage regulator driver for the Maxim 77686/802 |
4 | * |
5 | * Copyright (C) 2012 Samsung Electrnoics |
6 | * Chiwoong Byun <woong.byun@samsung.com> |
7 | */ |
8 | |
9 | #ifndef __LINUX_MFD_MAX77686_PRIV_H |
10 | #define __LINUX_MFD_MAX77686_PRIV_H |
11 | |
12 | #include <linux/i2c.h> |
13 | #include <linux/regmap.h> |
14 | #include <linux/module.h> |
15 | |
16 | #define MAX77686_REG_INVALID (0xff) |
17 | |
18 | /* MAX77686 PMIC registers */ |
19 | enum max77686_pmic_reg { |
20 | MAX77686_REG_DEVICE_ID = 0x00, |
21 | MAX77686_REG_INTSRC = 0x01, |
22 | MAX77686_REG_INT1 = 0x02, |
23 | MAX77686_REG_INT2 = 0x03, |
24 | |
25 | MAX77686_REG_INT1MSK = 0x04, |
26 | MAX77686_REG_INT2MSK = 0x05, |
27 | |
28 | MAX77686_REG_STATUS1 = 0x06, |
29 | MAX77686_REG_STATUS2 = 0x07, |
30 | |
31 | MAX77686_REG_PWRON = 0x08, |
32 | MAX77686_REG_ONOFF_DELAY = 0x09, |
33 | MAX77686_REG_MRSTB = 0x0A, |
34 | /* Reserved: 0x0B-0x0F */ |
35 | |
36 | MAX77686_REG_BUCK1CTRL = 0x10, |
37 | MAX77686_REG_BUCK1OUT = 0x11, |
38 | MAX77686_REG_BUCK2CTRL1 = 0x12, |
39 | MAX77686_REG_BUCK234FREQ = 0x13, |
40 | MAX77686_REG_BUCK2DVS1 = 0x14, |
41 | MAX77686_REG_BUCK2DVS2 = 0x15, |
42 | MAX77686_REG_BUCK2DVS3 = 0x16, |
43 | MAX77686_REG_BUCK2DVS4 = 0x17, |
44 | MAX77686_REG_BUCK2DVS5 = 0x18, |
45 | MAX77686_REG_BUCK2DVS6 = 0x19, |
46 | MAX77686_REG_BUCK2DVS7 = 0x1A, |
47 | MAX77686_REG_BUCK2DVS8 = 0x1B, |
48 | MAX77686_REG_BUCK3CTRL1 = 0x1C, |
49 | /* Reserved: 0x1D */ |
50 | MAX77686_REG_BUCK3DVS1 = 0x1E, |
51 | MAX77686_REG_BUCK3DVS2 = 0x1F, |
52 | MAX77686_REG_BUCK3DVS3 = 0x20, |
53 | MAX77686_REG_BUCK3DVS4 = 0x21, |
54 | MAX77686_REG_BUCK3DVS5 = 0x22, |
55 | MAX77686_REG_BUCK3DVS6 = 0x23, |
56 | MAX77686_REG_BUCK3DVS7 = 0x24, |
57 | MAX77686_REG_BUCK3DVS8 = 0x25, |
58 | MAX77686_REG_BUCK4CTRL1 = 0x26, |
59 | /* Reserved: 0x27 */ |
60 | MAX77686_REG_BUCK4DVS1 = 0x28, |
61 | MAX77686_REG_BUCK4DVS2 = 0x29, |
62 | MAX77686_REG_BUCK4DVS3 = 0x2A, |
63 | MAX77686_REG_BUCK4DVS4 = 0x2B, |
64 | MAX77686_REG_BUCK4DVS5 = 0x2C, |
65 | MAX77686_REG_BUCK4DVS6 = 0x2D, |
66 | MAX77686_REG_BUCK4DVS7 = 0x2E, |
67 | MAX77686_REG_BUCK4DVS8 = 0x2F, |
68 | MAX77686_REG_BUCK5CTRL = 0x30, |
69 | MAX77686_REG_BUCK5OUT = 0x31, |
70 | MAX77686_REG_BUCK6CTRL = 0x32, |
71 | MAX77686_REG_BUCK6OUT = 0x33, |
72 | MAX77686_REG_BUCK7CTRL = 0x34, |
73 | MAX77686_REG_BUCK7OUT = 0x35, |
74 | MAX77686_REG_BUCK8CTRL = 0x36, |
75 | MAX77686_REG_BUCK8OUT = 0x37, |
76 | MAX77686_REG_BUCK9CTRL = 0x38, |
77 | MAX77686_REG_BUCK9OUT = 0x39, |
78 | /* Reserved: 0x3A-0x3F */ |
79 | |
80 | MAX77686_REG_LDO1CTRL1 = 0x40, |
81 | MAX77686_REG_LDO2CTRL1 = 0x41, |
82 | MAX77686_REG_LDO3CTRL1 = 0x42, |
83 | MAX77686_REG_LDO4CTRL1 = 0x43, |
84 | MAX77686_REG_LDO5CTRL1 = 0x44, |
85 | MAX77686_REG_LDO6CTRL1 = 0x45, |
86 | MAX77686_REG_LDO7CTRL1 = 0x46, |
87 | MAX77686_REG_LDO8CTRL1 = 0x47, |
88 | MAX77686_REG_LDO9CTRL1 = 0x48, |
89 | MAX77686_REG_LDO10CTRL1 = 0x49, |
90 | MAX77686_REG_LDO11CTRL1 = 0x4A, |
91 | MAX77686_REG_LDO12CTRL1 = 0x4B, |
92 | MAX77686_REG_LDO13CTRL1 = 0x4C, |
93 | MAX77686_REG_LDO14CTRL1 = 0x4D, |
94 | MAX77686_REG_LDO15CTRL1 = 0x4E, |
95 | MAX77686_REG_LDO16CTRL1 = 0x4F, |
96 | MAX77686_REG_LDO17CTRL1 = 0x50, |
97 | MAX77686_REG_LDO18CTRL1 = 0x51, |
98 | MAX77686_REG_LDO19CTRL1 = 0x52, |
99 | MAX77686_REG_LDO20CTRL1 = 0x53, |
100 | MAX77686_REG_LDO21CTRL1 = 0x54, |
101 | MAX77686_REG_LDO22CTRL1 = 0x55, |
102 | MAX77686_REG_LDO23CTRL1 = 0x56, |
103 | MAX77686_REG_LDO24CTRL1 = 0x57, |
104 | MAX77686_REG_LDO25CTRL1 = 0x58, |
105 | MAX77686_REG_LDO26CTRL1 = 0x59, |
106 | /* Reserved: 0x5A-0x5F */ |
107 | MAX77686_REG_LDO1CTRL2 = 0x60, |
108 | MAX77686_REG_LDO2CTRL2 = 0x61, |
109 | MAX77686_REG_LDO3CTRL2 = 0x62, |
110 | MAX77686_REG_LDO4CTRL2 = 0x63, |
111 | MAX77686_REG_LDO5CTRL2 = 0x64, |
112 | MAX77686_REG_LDO6CTRL2 = 0x65, |
113 | MAX77686_REG_LDO7CTRL2 = 0x66, |
114 | MAX77686_REG_LDO8CTRL2 = 0x67, |
115 | MAX77686_REG_LDO9CTRL2 = 0x68, |
116 | MAX77686_REG_LDO10CTRL2 = 0x69, |
117 | MAX77686_REG_LDO11CTRL2 = 0x6A, |
118 | MAX77686_REG_LDO12CTRL2 = 0x6B, |
119 | MAX77686_REG_LDO13CTRL2 = 0x6C, |
120 | MAX77686_REG_LDO14CTRL2 = 0x6D, |
121 | MAX77686_REG_LDO15CTRL2 = 0x6E, |
122 | MAX77686_REG_LDO16CTRL2 = 0x6F, |
123 | MAX77686_REG_LDO17CTRL2 = 0x70, |
124 | MAX77686_REG_LDO18CTRL2 = 0x71, |
125 | MAX77686_REG_LDO19CTRL2 = 0x72, |
126 | MAX77686_REG_LDO20CTRL2 = 0x73, |
127 | MAX77686_REG_LDO21CTRL2 = 0x74, |
128 | MAX77686_REG_LDO22CTRL2 = 0x75, |
129 | MAX77686_REG_LDO23CTRL2 = 0x76, |
130 | MAX77686_REG_LDO24CTRL2 = 0x77, |
131 | MAX77686_REG_LDO25CTRL2 = 0x78, |
132 | MAX77686_REG_LDO26CTRL2 = 0x79, |
133 | /* Reserved: 0x7A-0x7D */ |
134 | |
135 | MAX77686_REG_BBAT_CHG = 0x7E, |
136 | MAX77686_REG_32KHZ = 0x7F, |
137 | |
138 | MAX77686_REG_PMIC_END = 0x80, |
139 | }; |
140 | |
141 | enum max77686_rtc_reg { |
142 | MAX77686_RTC_INT = 0x00, |
143 | MAX77686_RTC_INTM = 0x01, |
144 | MAX77686_RTC_CONTROLM = 0x02, |
145 | MAX77686_RTC_CONTROL = 0x03, |
146 | MAX77686_RTC_UPDATE0 = 0x04, |
147 | /* Reserved: 0x5 */ |
148 | MAX77686_WTSR_SMPL_CNTL = 0x06, |
149 | MAX77686_RTC_SEC = 0x07, |
150 | MAX77686_RTC_MIN = 0x08, |
151 | MAX77686_RTC_HOUR = 0x09, |
152 | MAX77686_RTC_WEEKDAY = 0x0A, |
153 | MAX77686_RTC_MONTH = 0x0B, |
154 | MAX77686_RTC_YEAR = 0x0C, |
155 | MAX77686_RTC_MONTHDAY = 0x0D, |
156 | MAX77686_ALARM1_SEC = 0x0E, |
157 | MAX77686_ALARM1_MIN = 0x0F, |
158 | MAX77686_ALARM1_HOUR = 0x10, |
159 | MAX77686_ALARM1_WEEKDAY = 0x11, |
160 | MAX77686_ALARM1_MONTH = 0x12, |
161 | MAX77686_ALARM1_YEAR = 0x13, |
162 | MAX77686_ALARM1_DATE = 0x14, |
163 | MAX77686_ALARM2_SEC = 0x15, |
164 | MAX77686_ALARM2_MIN = 0x16, |
165 | MAX77686_ALARM2_HOUR = 0x17, |
166 | MAX77686_ALARM2_WEEKDAY = 0x18, |
167 | MAX77686_ALARM2_MONTH = 0x19, |
168 | MAX77686_ALARM2_YEAR = 0x1A, |
169 | MAX77686_ALARM2_DATE = 0x1B, |
170 | }; |
171 | |
172 | /* MAX77802 PMIC registers */ |
173 | enum max77802_pmic_reg { |
174 | MAX77802_REG_DEVICE_ID = 0x00, |
175 | MAX77802_REG_INTSRC = 0x01, |
176 | MAX77802_REG_INT1 = 0x02, |
177 | MAX77802_REG_INT2 = 0x03, |
178 | |
179 | MAX77802_REG_INT1MSK = 0x04, |
180 | MAX77802_REG_INT2MSK = 0x05, |
181 | |
182 | MAX77802_REG_STATUS1 = 0x06, |
183 | MAX77802_REG_STATUS2 = 0x07, |
184 | |
185 | MAX77802_REG_PWRON = 0x08, |
186 | /* Reserved: 0x09 */ |
187 | MAX77802_REG_MRSTB = 0x0A, |
188 | MAX77802_REG_EPWRHOLD = 0x0B, |
189 | /* Reserved: 0x0C-0x0D */ |
190 | MAX77802_REG_BOOSTCTRL = 0x0E, |
191 | MAX77802_REG_BOOSTOUT = 0x0F, |
192 | |
193 | MAX77802_REG_BUCK1CTRL = 0x10, |
194 | MAX77802_REG_BUCK1DVS1 = 0x11, |
195 | MAX77802_REG_BUCK1DVS2 = 0x12, |
196 | MAX77802_REG_BUCK1DVS3 = 0x13, |
197 | MAX77802_REG_BUCK1DVS4 = 0x14, |
198 | MAX77802_REG_BUCK1DVS5 = 0x15, |
199 | MAX77802_REG_BUCK1DVS6 = 0x16, |
200 | MAX77802_REG_BUCK1DVS7 = 0x17, |
201 | MAX77802_REG_BUCK1DVS8 = 0x18, |
202 | /* Reserved: 0x19 */ |
203 | MAX77802_REG_BUCK2CTRL1 = 0x1A, |
204 | MAX77802_REG_BUCK2CTRL2 = 0x1B, |
205 | MAX77802_REG_BUCK2PHTRAN = 0x1C, |
206 | MAX77802_REG_BUCK2DVS1 = 0x1D, |
207 | MAX77802_REG_BUCK2DVS2 = 0x1E, |
208 | MAX77802_REG_BUCK2DVS3 = 0x1F, |
209 | MAX77802_REG_BUCK2DVS4 = 0x20, |
210 | MAX77802_REG_BUCK2DVS5 = 0x21, |
211 | MAX77802_REG_BUCK2DVS6 = 0x22, |
212 | MAX77802_REG_BUCK2DVS7 = 0x23, |
213 | MAX77802_REG_BUCK2DVS8 = 0x24, |
214 | /* Reserved: 0x25-0x26 */ |
215 | MAX77802_REG_BUCK3CTRL1 = 0x27, |
216 | MAX77802_REG_BUCK3DVS1 = 0x28, |
217 | MAX77802_REG_BUCK3DVS2 = 0x29, |
218 | MAX77802_REG_BUCK3DVS3 = 0x2A, |
219 | MAX77802_REG_BUCK3DVS4 = 0x2B, |
220 | MAX77802_REG_BUCK3DVS5 = 0x2C, |
221 | MAX77802_REG_BUCK3DVS6 = 0x2D, |
222 | MAX77802_REG_BUCK3DVS7 = 0x2E, |
223 | MAX77802_REG_BUCK3DVS8 = 0x2F, |
224 | /* Reserved: 0x30-0x36 */ |
225 | MAX77802_REG_BUCK4CTRL1 = 0x37, |
226 | MAX77802_REG_BUCK4DVS1 = 0x38, |
227 | MAX77802_REG_BUCK4DVS2 = 0x39, |
228 | MAX77802_REG_BUCK4DVS3 = 0x3A, |
229 | MAX77802_REG_BUCK4DVS4 = 0x3B, |
230 | MAX77802_REG_BUCK4DVS5 = 0x3C, |
231 | MAX77802_REG_BUCK4DVS6 = 0x3D, |
232 | MAX77802_REG_BUCK4DVS7 = 0x3E, |
233 | MAX77802_REG_BUCK4DVS8 = 0x3F, |
234 | /* Reserved: 0x40 */ |
235 | MAX77802_REG_BUCK5CTRL = 0x41, |
236 | MAX77802_REG_BUCK5OUT = 0x42, |
237 | /* Reserved: 0x43 */ |
238 | MAX77802_REG_BUCK6CTRL = 0x44, |
239 | MAX77802_REG_BUCK6DVS1 = 0x45, |
240 | MAX77802_REG_BUCK6DVS2 = 0x46, |
241 | MAX77802_REG_BUCK6DVS3 = 0x47, |
242 | MAX77802_REG_BUCK6DVS4 = 0x48, |
243 | MAX77802_REG_BUCK6DVS5 = 0x49, |
244 | MAX77802_REG_BUCK6DVS6 = 0x4A, |
245 | MAX77802_REG_BUCK6DVS7 = 0x4B, |
246 | MAX77802_REG_BUCK6DVS8 = 0x4C, |
247 | /* Reserved: 0x4D */ |
248 | MAX77802_REG_BUCK7CTRL = 0x4E, |
249 | MAX77802_REG_BUCK7OUT = 0x4F, |
250 | /* Reserved: 0x50 */ |
251 | MAX77802_REG_BUCK8CTRL = 0x51, |
252 | MAX77802_REG_BUCK8OUT = 0x52, |
253 | /* Reserved: 0x53 */ |
254 | MAX77802_REG_BUCK9CTRL = 0x54, |
255 | MAX77802_REG_BUCK9OUT = 0x55, |
256 | /* Reserved: 0x56 */ |
257 | MAX77802_REG_BUCK10CTRL = 0x57, |
258 | MAX77802_REG_BUCK10OUT = 0x58, |
259 | |
260 | /* Reserved: 0x59-0x5F */ |
261 | |
262 | MAX77802_REG_LDO1CTRL1 = 0x60, |
263 | MAX77802_REG_LDO2CTRL1 = 0x61, |
264 | MAX77802_REG_LDO3CTRL1 = 0x62, |
265 | MAX77802_REG_LDO4CTRL1 = 0x63, |
266 | MAX77802_REG_LDO5CTRL1 = 0x64, |
267 | MAX77802_REG_LDO6CTRL1 = 0x65, |
268 | MAX77802_REG_LDO7CTRL1 = 0x66, |
269 | MAX77802_REG_LDO8CTRL1 = 0x67, |
270 | MAX77802_REG_LDO9CTRL1 = 0x68, |
271 | MAX77802_REG_LDO10CTRL1 = 0x69, |
272 | MAX77802_REG_LDO11CTRL1 = 0x6A, |
273 | MAX77802_REG_LDO12CTRL1 = 0x6B, |
274 | MAX77802_REG_LDO13CTRL1 = 0x6C, |
275 | MAX77802_REG_LDO14CTRL1 = 0x6D, |
276 | MAX77802_REG_LDO15CTRL1 = 0x6E, |
277 | /* Reserved: 0x6F */ |
278 | MAX77802_REG_LDO17CTRL1 = 0x70, |
279 | MAX77802_REG_LDO18CTRL1 = 0x71, |
280 | MAX77802_REG_LDO19CTRL1 = 0x72, |
281 | MAX77802_REG_LDO20CTRL1 = 0x73, |
282 | MAX77802_REG_LDO21CTRL1 = 0x74, |
283 | MAX77802_REG_LDO22CTRL1 = 0x75, |
284 | MAX77802_REG_LDO23CTRL1 = 0x76, |
285 | MAX77802_REG_LDO24CTRL1 = 0x77, |
286 | MAX77802_REG_LDO25CTRL1 = 0x78, |
287 | MAX77802_REG_LDO26CTRL1 = 0x79, |
288 | MAX77802_REG_LDO27CTRL1 = 0x7A, |
289 | MAX77802_REG_LDO28CTRL1 = 0x7B, |
290 | MAX77802_REG_LDO29CTRL1 = 0x7C, |
291 | MAX77802_REG_LDO30CTRL1 = 0x7D, |
292 | /* Reserved: 0x7E */ |
293 | MAX77802_REG_LDO32CTRL1 = 0x7F, |
294 | MAX77802_REG_LDO33CTRL1 = 0x80, |
295 | MAX77802_REG_LDO34CTRL1 = 0x81, |
296 | MAX77802_REG_LDO35CTRL1 = 0x82, |
297 | /* Reserved: 0x83-0x8F */ |
298 | MAX77802_REG_LDO1CTRL2 = 0x90, |
299 | MAX77802_REG_LDO2CTRL2 = 0x91, |
300 | MAX77802_REG_LDO3CTRL2 = 0x92, |
301 | MAX77802_REG_LDO4CTRL2 = 0x93, |
302 | MAX77802_REG_LDO5CTRL2 = 0x94, |
303 | MAX77802_REG_LDO6CTRL2 = 0x95, |
304 | MAX77802_REG_LDO7CTRL2 = 0x96, |
305 | MAX77802_REG_LDO8CTRL2 = 0x97, |
306 | MAX77802_REG_LDO9CTRL2 = 0x98, |
307 | MAX77802_REG_LDO10CTRL2 = 0x99, |
308 | MAX77802_REG_LDO11CTRL2 = 0x9A, |
309 | MAX77802_REG_LDO12CTRL2 = 0x9B, |
310 | MAX77802_REG_LDO13CTRL2 = 0x9C, |
311 | MAX77802_REG_LDO14CTRL2 = 0x9D, |
312 | MAX77802_REG_LDO15CTRL2 = 0x9E, |
313 | /* Reserved: 0x9F */ |
314 | MAX77802_REG_LDO17CTRL2 = 0xA0, |
315 | MAX77802_REG_LDO18CTRL2 = 0xA1, |
316 | MAX77802_REG_LDO19CTRL2 = 0xA2, |
317 | MAX77802_REG_LDO20CTRL2 = 0xA3, |
318 | MAX77802_REG_LDO21CTRL2 = 0xA4, |
319 | MAX77802_REG_LDO22CTRL2 = 0xA5, |
320 | MAX77802_REG_LDO23CTRL2 = 0xA6, |
321 | MAX77802_REG_LDO24CTRL2 = 0xA7, |
322 | MAX77802_REG_LDO25CTRL2 = 0xA8, |
323 | MAX77802_REG_LDO26CTRL2 = 0xA9, |
324 | MAX77802_REG_LDO27CTRL2 = 0xAA, |
325 | MAX77802_REG_LDO28CTRL2 = 0xAB, |
326 | MAX77802_REG_LDO29CTRL2 = 0xAC, |
327 | MAX77802_REG_LDO30CTRL2 = 0xAD, |
328 | /* Reserved: 0xAE */ |
329 | MAX77802_REG_LDO32CTRL2 = 0xAF, |
330 | MAX77802_REG_LDO33CTRL2 = 0xB0, |
331 | MAX77802_REG_LDO34CTRL2 = 0xB1, |
332 | MAX77802_REG_LDO35CTRL2 = 0xB2, |
333 | /* Reserved: 0xB3 */ |
334 | |
335 | MAX77802_REG_BBAT_CHG = 0xB4, |
336 | MAX77802_REG_32KHZ = 0xB5, |
337 | |
338 | MAX77802_REG_PMIC_END = 0xB6, |
339 | }; |
340 | |
341 | enum max77802_rtc_reg { |
342 | MAX77802_RTC_INT = 0xC0, |
343 | MAX77802_RTC_INTM = 0xC1, |
344 | MAX77802_RTC_CONTROLM = 0xC2, |
345 | MAX77802_RTC_CONTROL = 0xC3, |
346 | MAX77802_RTC_UPDATE0 = 0xC4, |
347 | MAX77802_RTC_UPDATE1 = 0xC5, |
348 | MAX77802_WTSR_SMPL_CNTL = 0xC6, |
349 | MAX77802_RTC_SEC = 0xC7, |
350 | MAX77802_RTC_MIN = 0xC8, |
351 | MAX77802_RTC_HOUR = 0xC9, |
352 | MAX77802_RTC_WEEKDAY = 0xCA, |
353 | MAX77802_RTC_MONTH = 0xCB, |
354 | MAX77802_RTC_YEAR = 0xCC, |
355 | MAX77802_RTC_MONTHDAY = 0xCD, |
356 | MAX77802_RTC_AE1 = 0xCE, |
357 | MAX77802_ALARM1_SEC = 0xCF, |
358 | MAX77802_ALARM1_MIN = 0xD0, |
359 | MAX77802_ALARM1_HOUR = 0xD1, |
360 | MAX77802_ALARM1_WEEKDAY = 0xD2, |
361 | MAX77802_ALARM1_MONTH = 0xD3, |
362 | MAX77802_ALARM1_YEAR = 0xD4, |
363 | MAX77802_ALARM1_DATE = 0xD5, |
364 | MAX77802_RTC_AE2 = 0xD6, |
365 | MAX77802_ALARM2_SEC = 0xD7, |
366 | MAX77802_ALARM2_MIN = 0xD8, |
367 | MAX77802_ALARM2_HOUR = 0xD9, |
368 | MAX77802_ALARM2_WEEKDAY = 0xDA, |
369 | MAX77802_ALARM2_MONTH = 0xDB, |
370 | MAX77802_ALARM2_YEAR = 0xDC, |
371 | MAX77802_ALARM2_DATE = 0xDD, |
372 | |
373 | MAX77802_RTC_END = 0xDF, |
374 | }; |
375 | |
376 | enum max77686_irq_source { |
377 | PMIC_INT1 = 0, |
378 | PMIC_INT2, |
379 | RTC_INT, |
380 | |
381 | MAX77686_IRQ_GROUP_NR, |
382 | }; |
383 | |
384 | enum max77686_irq { |
385 | MAX77686_PMICIRQ_PWRONF, |
386 | MAX77686_PMICIRQ_PWRONR, |
387 | MAX77686_PMICIRQ_JIGONBF, |
388 | MAX77686_PMICIRQ_JIGONBR, |
389 | MAX77686_PMICIRQ_ACOKBF, |
390 | MAX77686_PMICIRQ_ACOKBR, |
391 | MAX77686_PMICIRQ_ONKEY1S, |
392 | MAX77686_PMICIRQ_MRSTB, |
393 | |
394 | MAX77686_PMICIRQ_140C, |
395 | MAX77686_PMICIRQ_120C, |
396 | |
397 | MAX77686_RTCIRQ_RTC60S = 0, |
398 | MAX77686_RTCIRQ_RTCA1, |
399 | MAX77686_RTCIRQ_RTCA2, |
400 | MAX77686_RTCIRQ_SMPL, |
401 | MAX77686_RTCIRQ_RTC1S, |
402 | MAX77686_RTCIRQ_WTSR, |
403 | }; |
404 | |
405 | #define MAX77686_INT1_PWRONF_MSK BIT(0) |
406 | #define MAX77686_INT1_PWRONR_MSK BIT(1) |
407 | #define MAX77686_INT1_JIGONBF_MSK BIT(2) |
408 | #define MAX77686_INT1_JIGONBR_MSK BIT(3) |
409 | #define MAX77686_INT1_ACOKBF_MSK BIT(4) |
410 | #define MAX77686_INT1_ACOKBR_MSK BIT(5) |
411 | #define MAX77686_INT1_ONKEY1S_MSK BIT(6) |
412 | #define MAX77686_INT1_MRSTB_MSK BIT(7) |
413 | |
414 | #define MAX77686_INT2_140C_MSK BIT(0) |
415 | #define MAX77686_INT2_120C_MSK BIT(1) |
416 | |
417 | #define MAX77686_RTCINT_RTC60S_MSK BIT(0) |
418 | #define MAX77686_RTCINT_RTCA1_MSK BIT(1) |
419 | #define MAX77686_RTCINT_RTCA2_MSK BIT(2) |
420 | #define MAX77686_RTCINT_SMPL_MSK BIT(3) |
421 | #define MAX77686_RTCINT_RTC1S_MSK BIT(4) |
422 | #define MAX77686_RTCINT_WTSR_MSK BIT(5) |
423 | |
424 | struct max77686_dev { |
425 | struct device *dev; |
426 | struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */ |
427 | |
428 | unsigned long type; |
429 | |
430 | struct regmap *regmap; /* regmap for mfd */ |
431 | struct regmap_irq_chip_data *irq_data; |
432 | |
433 | int irq; |
434 | struct mutex irqlock; |
435 | int irq_masks_cur[MAX77686_IRQ_GROUP_NR]; |
436 | int irq_masks_cache[MAX77686_IRQ_GROUP_NR]; |
437 | }; |
438 | |
439 | enum max77686_types { |
440 | TYPE_MAX77686, |
441 | TYPE_MAX77802, |
442 | }; |
443 | |
444 | #endif /* __LINUX_MFD_MAX77686_PRIV_H */ |
445 | |