1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * max77693-private.h - Voltage regulator driver for the Maxim 77693 |
4 | * |
5 | * Copyright (C) 2012 Samsung Electrnoics |
6 | * SangYoung Son <hello.son@samsung.com> |
7 | * |
8 | * This program is not provided / owned by Maxim Integrated Products. |
9 | */ |
10 | |
11 | #ifndef __LINUX_MFD_MAX77693_PRIV_H |
12 | #define __LINUX_MFD_MAX77693_PRIV_H |
13 | |
14 | #include <linux/i2c.h> |
15 | |
16 | #define MAX77693_REG_INVALID (0xff) |
17 | |
18 | /* Slave addr = 0xCC: PMIC, Charger, Flash LED */ |
19 | enum max77693_pmic_reg { |
20 | MAX77693_LED_REG_IFLASH1 = 0x00, |
21 | MAX77693_LED_REG_IFLASH2 = 0x01, |
22 | MAX77693_LED_REG_ITORCH = 0x02, |
23 | MAX77693_LED_REG_ITORCHTIMER = 0x03, |
24 | MAX77693_LED_REG_FLASH_TIMER = 0x04, |
25 | MAX77693_LED_REG_FLASH_EN = 0x05, |
26 | MAX77693_LED_REG_MAX_FLASH1 = 0x06, |
27 | MAX77693_LED_REG_MAX_FLASH2 = 0x07, |
28 | MAX77693_LED_REG_MAX_FLASH3 = 0x08, |
29 | MAX77693_LED_REG_MAX_FLASH4 = 0x09, |
30 | MAX77693_LED_REG_VOUT_CNTL = 0x0A, |
31 | MAX77693_LED_REG_VOUT_FLASH1 = 0x0B, |
32 | MAX77693_LED_REG_VOUT_FLASH2 = 0x0C, |
33 | MAX77693_LED_REG_FLASH_INT = 0x0E, |
34 | MAX77693_LED_REG_FLASH_INT_MASK = 0x0F, |
35 | MAX77693_LED_REG_FLASH_STATUS = 0x10, |
36 | |
37 | MAX77693_PMIC_REG_PMIC_ID1 = 0x20, |
38 | MAX77693_PMIC_REG_PMIC_ID2 = 0x21, |
39 | MAX77693_PMIC_REG_INTSRC = 0x22, |
40 | MAX77693_PMIC_REG_INTSRC_MASK = 0x23, |
41 | MAX77693_PMIC_REG_TOPSYS_INT = 0x24, |
42 | MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26, |
43 | MAX77693_PMIC_REG_TOPSYS_STAT = 0x28, |
44 | MAX77693_PMIC_REG_MAINCTRL1 = 0x2A, |
45 | MAX77693_PMIC_REG_LSCNFG = 0x2B, |
46 | |
47 | MAX77693_CHG_REG_CHG_INT = 0xB0, |
48 | MAX77693_CHG_REG_CHG_INT_MASK = 0xB1, |
49 | MAX77693_CHG_REG_CHG_INT_OK = 0xB2, |
50 | MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3, |
51 | MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4, |
52 | MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5, |
53 | MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6, |
54 | MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7, |
55 | MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8, |
56 | MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9, |
57 | MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA, |
58 | MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB, |
59 | MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC, |
60 | MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD, |
61 | MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE, |
62 | MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF, |
63 | MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0, |
64 | MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1, |
65 | MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2, |
66 | MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3, |
67 | MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4, |
68 | MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5, |
69 | MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6, |
70 | |
71 | MAX77693_PMIC_REG_END, |
72 | }; |
73 | |
74 | /* MAX77693 ITORCH register */ |
75 | #define TORCH_IOUT1_SHIFT 0 |
76 | #define TORCH_IOUT2_SHIFT 4 |
77 | #define TORCH_IOUT_MASK(x) (0xf << (x)) |
78 | #define TORCH_IOUT_MIN 15625 |
79 | #define TORCH_IOUT_MAX 250000 |
80 | #define TORCH_IOUT_STEP 15625 |
81 | |
82 | /* MAX77693 IFLASH1 and IFLASH2 registers */ |
83 | #define FLASH_IOUT_MIN 15625 |
84 | #define FLASH_IOUT_MAX_1LED 1000000 |
85 | #define FLASH_IOUT_MAX_2LEDS 625000 |
86 | #define FLASH_IOUT_STEP 15625 |
87 | |
88 | /* MAX77693 TORCH_TIMER register */ |
89 | #define TORCH_TMR_NO_TIMER 0x40 |
90 | #define TORCH_TIMEOUT_MIN 262000 |
91 | #define TORCH_TIMEOUT_MAX 15728000 |
92 | |
93 | /* MAX77693 FLASH_TIMER register */ |
94 | #define FLASH_TMR_LEVEL 0x80 |
95 | #define FLASH_TIMEOUT_MIN 62500 |
96 | #define FLASH_TIMEOUT_MAX 1000000 |
97 | #define FLASH_TIMEOUT_STEP 62500 |
98 | |
99 | /* MAX77693 FLASH_EN register */ |
100 | #define FLASH_EN_OFF 0x0 |
101 | #define FLASH_EN_FLASH 0x1 |
102 | #define FLASH_EN_TORCH 0x2 |
103 | #define FLASH_EN_ON 0x3 |
104 | #define FLASH_EN_SHIFT(x) (6 - (x) * 2) |
105 | #define TORCH_EN_SHIFT(x) (2 - (x) * 2) |
106 | |
107 | /* MAX77693 MAX_FLASH1 register */ |
108 | #define MAX_FLASH1_MAX_FL_EN 0x80 |
109 | #define MAX_FLASH1_VSYS_MIN 2400 |
110 | #define MAX_FLASH1_VSYS_MAX 3400 |
111 | #define MAX_FLASH1_VSYS_STEP 33 |
112 | |
113 | /* MAX77693 VOUT_CNTL register */ |
114 | #define FLASH_BOOST_FIXED 0x04 |
115 | #define FLASH_BOOST_LEDNUM_2 0x80 |
116 | |
117 | /* MAX77693 VOUT_FLASH1 register */ |
118 | #define FLASH_VOUT_MIN 3300 |
119 | #define FLASH_VOUT_MAX 5500 |
120 | #define FLASH_VOUT_STEP 25 |
121 | #define FLASH_VOUT_RMIN 0x0c |
122 | |
123 | /* MAX77693 FLASH_STATUS register */ |
124 | #define FLASH_STATUS_FLASH_ON BIT(3) |
125 | #define FLASH_STATUS_TORCH_ON BIT(2) |
126 | |
127 | /* MAX77693 FLASH_INT register */ |
128 | #define FLASH_INT_FLED2_OPEN BIT(0) |
129 | #define FLASH_INT_FLED2_SHORT BIT(1) |
130 | #define FLASH_INT_FLED1_OPEN BIT(2) |
131 | #define FLASH_INT_FLED1_SHORT BIT(3) |
132 | #define FLASH_INT_OVER_CURRENT BIT(4) |
133 | |
134 | /* Fast charge timer in hours */ |
135 | #define DEFAULT_FAST_CHARGE_TIMER 4 |
136 | /* microamps */ |
137 | #define DEFAULT_TOP_OFF_THRESHOLD_CURRENT 150000 |
138 | /* minutes */ |
139 | #define DEFAULT_TOP_OFF_TIMER 30 |
140 | /* microvolts */ |
141 | #define DEFAULT_CONSTANT_VOLT 4200000 |
142 | /* microvolts */ |
143 | #define DEFAULT_MIN_SYSTEM_VOLT 3600000 |
144 | /* celsius */ |
145 | #define DEFAULT_THERMAL_REGULATION_TEMP 100 |
146 | /* microamps */ |
147 | #define DEFAULT_BATTERY_OVERCURRENT 3500000 |
148 | /* microvolts */ |
149 | #define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT 4300000 |
150 | |
151 | /* MAX77693_CHG_REG_CHG_INT_OK register */ |
152 | #define CHG_INT_OK_BYP_SHIFT 0 |
153 | #define CHG_INT_OK_BAT_SHIFT 3 |
154 | #define CHG_INT_OK_CHG_SHIFT 4 |
155 | #define CHG_INT_OK_CHGIN_SHIFT 6 |
156 | #define CHG_INT_OK_DETBAT_SHIFT 7 |
157 | #define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT) |
158 | #define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT) |
159 | #define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT) |
160 | #define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT) |
161 | #define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT) |
162 | |
163 | /* MAX77693_CHG_REG_CHG_DETAILS_00 register */ |
164 | #define CHG_DETAILS_00_CHGIN_SHIFT 5 |
165 | #define CHG_DETAILS_00_CHGIN_MASK (0x3 << CHG_DETAILS_00_CHGIN_SHIFT) |
166 | |
167 | /* MAX77693_CHG_REG_CHG_DETAILS_01 register */ |
168 | #define CHG_DETAILS_01_CHG_SHIFT 0 |
169 | #define CHG_DETAILS_01_BAT_SHIFT 4 |
170 | #define CHG_DETAILS_01_TREG_SHIFT 7 |
171 | #define CHG_DETAILS_01_CHG_MASK (0xf << CHG_DETAILS_01_CHG_SHIFT) |
172 | #define CHG_DETAILS_01_BAT_MASK (0x7 << CHG_DETAILS_01_BAT_SHIFT) |
173 | #define CHG_DETAILS_01_TREG_MASK BIT(7) |
174 | |
175 | /* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */ |
176 | enum max77693_charger_charging_state { |
177 | MAX77693_CHARGING_PREQUALIFICATION = 0x0, |
178 | MAX77693_CHARGING_FAST_CONST_CURRENT, |
179 | MAX77693_CHARGING_FAST_CONST_VOLTAGE, |
180 | MAX77693_CHARGING_TOP_OFF, |
181 | MAX77693_CHARGING_DONE, |
182 | MAX77693_CHARGING_HIGH_TEMP, |
183 | MAX77693_CHARGING_TIMER_EXPIRED, |
184 | MAX77693_CHARGING_THERMISTOR_SUSPEND, |
185 | MAX77693_CHARGING_OFF, |
186 | MAX77693_CHARGING_RESERVED, |
187 | MAX77693_CHARGING_OVER_TEMP, |
188 | MAX77693_CHARGING_WATCHDOG_EXPIRED, |
189 | }; |
190 | |
191 | /* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */ |
192 | enum max77693_charger_battery_state { |
193 | MAX77693_BATTERY_NOBAT = 0x0, |
194 | /* Dead-battery or low-battery prequalification */ |
195 | MAX77693_BATTERY_PREQUALIFICATION, |
196 | MAX77693_BATTERY_TIMER_EXPIRED, |
197 | MAX77693_BATTERY_GOOD, |
198 | MAX77693_BATTERY_LOWVOLTAGE, |
199 | MAX77693_BATTERY_OVERVOLTAGE, |
200 | MAX77693_BATTERY_OVERCURRENT, |
201 | MAX77693_BATTERY_RESERVED, |
202 | }; |
203 | |
204 | /* MAX77693_CHG_REG_CHG_DETAILS_02 register */ |
205 | #define CHG_DETAILS_02_BYP_SHIFT 0 |
206 | #define CHG_DETAILS_02_BYP_MASK (0xf << CHG_DETAILS_02_BYP_SHIFT) |
207 | |
208 | /* MAX77693 CHG_CNFG_00 register */ |
209 | #define CHG_CNFG_00_CHG_MASK 0x1 |
210 | #define CHG_CNFG_00_BUCK_MASK 0x4 |
211 | |
212 | /* MAX77693_CHG_REG_CHG_CNFG_01 register */ |
213 | #define CHG_CNFG_01_FCHGTIME_SHIFT 0 |
214 | #define CHG_CNFG_01_CHGRSTRT_SHIFT 4 |
215 | #define CHG_CNFG_01_PQEN_SHIFT 7 |
216 | #define CHG_CNFG_01_FCHGTIME_MASK (0x7 << CHG_CNFG_01_FCHGTIME_SHIFT) |
217 | #define CHG_CNFG_01_CHGRSTRT_MASK (0x3 << CHG_CNFG_01_CHGRSTRT_SHIFT) |
218 | #define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT) |
219 | |
220 | /* MAX77693_CHG_REG_CHG_CNFG_03 register */ |
221 | #define CHG_CNFG_03_TOITH_SHIFT 0 |
222 | #define CHG_CNFG_03_TOTIME_SHIFT 3 |
223 | #define CHG_CNFG_03_TOITH_MASK (0x7 << CHG_CNFG_03_TOITH_SHIFT) |
224 | #define CHG_CNFG_03_TOTIME_MASK (0x7 << CHG_CNFG_03_TOTIME_SHIFT) |
225 | |
226 | /* MAX77693_CHG_REG_CHG_CNFG_04 register */ |
227 | #define CHG_CNFG_04_CHGCVPRM_SHIFT 0 |
228 | #define CHG_CNFG_04_MINVSYS_SHIFT 5 |
229 | #define CHG_CNFG_04_CHGCVPRM_MASK (0x1f << CHG_CNFG_04_CHGCVPRM_SHIFT) |
230 | #define CHG_CNFG_04_MINVSYS_MASK (0x7 << CHG_CNFG_04_MINVSYS_SHIFT) |
231 | |
232 | /* MAX77693_CHG_REG_CHG_CNFG_06 register */ |
233 | #define CHG_CNFG_06_CHGPROT_SHIFT 2 |
234 | #define CHG_CNFG_06_CHGPROT_MASK (0x3 << CHG_CNFG_06_CHGPROT_SHIFT) |
235 | |
236 | /* MAX77693_CHG_REG_CHG_CNFG_07 register */ |
237 | #define CHG_CNFG_07_REGTEMP_SHIFT 5 |
238 | #define CHG_CNFG_07_REGTEMP_MASK (0x3 << CHG_CNFG_07_REGTEMP_SHIFT) |
239 | |
240 | /* MAX77693_CHG_REG_CHG_CNFG_12 register */ |
241 | #define CHG_CNFG_12_B2SOVRC_SHIFT 0 |
242 | #define CHG_CNFG_12_VCHGINREG_SHIFT 3 |
243 | #define CHG_CNFG_12_B2SOVRC_MASK (0x7 << CHG_CNFG_12_B2SOVRC_SHIFT) |
244 | #define CHG_CNFG_12_VCHGINREG_MASK (0x3 << CHG_CNFG_12_VCHGINREG_SHIFT) |
245 | |
246 | /* MAX77693 CHG_CNFG_09 Register */ |
247 | #define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F |
248 | |
249 | /* MAX77693 CHG_CTRL Register */ |
250 | #define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3 |
251 | #define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC |
252 | #define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40 |
253 | #define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80 |
254 | |
255 | /* Slave addr = 0x4A: MUIC */ |
256 | enum max77693_muic_reg { |
257 | MAX77693_MUIC_REG_ID = 0x00, |
258 | MAX77693_MUIC_REG_INT1 = 0x01, |
259 | MAX77693_MUIC_REG_INT2 = 0x02, |
260 | MAX77693_MUIC_REG_INT3 = 0x03, |
261 | MAX77693_MUIC_REG_STATUS1 = 0x04, |
262 | MAX77693_MUIC_REG_STATUS2 = 0x05, |
263 | MAX77693_MUIC_REG_STATUS3 = 0x06, |
264 | MAX77693_MUIC_REG_INTMASK1 = 0x07, |
265 | MAX77693_MUIC_REG_INTMASK2 = 0x08, |
266 | MAX77693_MUIC_REG_INTMASK3 = 0x09, |
267 | MAX77693_MUIC_REG_CDETCTRL1 = 0x0A, |
268 | MAX77693_MUIC_REG_CDETCTRL2 = 0x0B, |
269 | MAX77693_MUIC_REG_CTRL1 = 0x0C, |
270 | MAX77693_MUIC_REG_CTRL2 = 0x0D, |
271 | MAX77693_MUIC_REG_CTRL3 = 0x0E, |
272 | |
273 | MAX77693_MUIC_REG_END, |
274 | }; |
275 | |
276 | /* MAX77693 INTMASK1~2 Register */ |
277 | #define INTMASK1_ADC1K_SHIFT 3 |
278 | #define INTMASK1_ADCERR_SHIFT 2 |
279 | #define INTMASK1_ADCLOW_SHIFT 1 |
280 | #define INTMASK1_ADC_SHIFT 0 |
281 | #define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT) |
282 | #define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT) |
283 | #define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT) |
284 | #define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT) |
285 | |
286 | #define INTMASK2_VIDRM_SHIFT 5 |
287 | #define INTMASK2_VBVOLT_SHIFT 4 |
288 | #define INTMASK2_DXOVP_SHIFT 3 |
289 | #define INTMASK2_DCDTMR_SHIFT 2 |
290 | #define INTMASK2_CHGDETRUN_SHIFT 1 |
291 | #define INTMASK2_CHGTYP_SHIFT 0 |
292 | #define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT) |
293 | #define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT) |
294 | #define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT) |
295 | #define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT) |
296 | #define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT) |
297 | #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT) |
298 | |
299 | /* MAX77693 MUIC - STATUS1~3 Register */ |
300 | #define MAX77693_STATUS1_ADC_SHIFT 0 |
301 | #define MAX77693_STATUS1_ADCLOW_SHIFT 5 |
302 | #define MAX77693_STATUS1_ADCERR_SHIFT 6 |
303 | #define MAX77693_STATUS1_ADC1K_SHIFT 7 |
304 | #define MAX77693_STATUS1_ADC_MASK (0x1f << MAX77693_STATUS1_ADC_SHIFT) |
305 | #define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT) |
306 | #define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT) |
307 | #define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT) |
308 | |
309 | #define MAX77693_STATUS2_CHGTYP_SHIFT 0 |
310 | #define MAX77693_STATUS2_CHGDETRUN_SHIFT 3 |
311 | #define MAX77693_STATUS2_DCDTMR_SHIFT 4 |
312 | #define MAX77693_STATUS2_DXOVP_SHIFT 5 |
313 | #define MAX77693_STATUS2_VBVOLT_SHIFT 6 |
314 | #define MAX77693_STATUS2_VIDRM_SHIFT 7 |
315 | #define MAX77693_STATUS2_CHGTYP_MASK (0x7 << MAX77693_STATUS2_CHGTYP_SHIFT) |
316 | #define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT) |
317 | #define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT) |
318 | #define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT) |
319 | #define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT) |
320 | #define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT) |
321 | |
322 | #define MAX77693_STATUS3_OVP_SHIFT 2 |
323 | #define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT) |
324 | |
325 | /* MAX77693 CDETCTRL1~2 register */ |
326 | #define CDETCTRL1_CHGDETEN_SHIFT (0) |
327 | #define CDETCTRL1_CHGTYPMAN_SHIFT (1) |
328 | #define CDETCTRL1_DCDEN_SHIFT (2) |
329 | #define CDETCTRL1_DCD2SCT_SHIFT (3) |
330 | #define CDETCTRL1_CDDELAY_SHIFT (4) |
331 | #define CDETCTRL1_DCDCPL_SHIFT (5) |
332 | #define CDETCTRL1_CDPDET_SHIFT (7) |
333 | #define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT) |
334 | #define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT) |
335 | #define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT) |
336 | #define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT) |
337 | #define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT) |
338 | #define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT) |
339 | #define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT) |
340 | |
341 | #define CDETCTRL2_VIDRMEN_SHIFT (1) |
342 | #define CDETCTRL2_DXOVPEN_SHIFT (3) |
343 | #define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT) |
344 | #define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT) |
345 | |
346 | /* MAX77693 MUIC - CONTROL1~3 register */ |
347 | #define COMN1SW_SHIFT (0) |
348 | #define COMP2SW_SHIFT (3) |
349 | #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) |
350 | #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) |
351 | #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK) |
352 | #define MAX77693_CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \ |
353 | | (1 << COMN1SW_SHIFT)) |
354 | #define MAX77693_CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ |
355 | | (2 << COMN1SW_SHIFT)) |
356 | #define MAX77693_CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \ |
357 | | (3 << COMN1SW_SHIFT)) |
358 | #define MAX77693_CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ |
359 | | (0 << COMN1SW_SHIFT)) |
360 | |
361 | #define MAX77693_CONTROL2_LOWPWR_SHIFT 0 |
362 | #define MAX77693_CONTROL2_ADCEN_SHIFT 1 |
363 | #define MAX77693_CONTROL2_CPEN_SHIFT 2 |
364 | #define MAX77693_CONTROL2_SFOUTASRT_SHIFT 3 |
365 | #define MAX77693_CONTROL2_SFOUTORD_SHIFT 4 |
366 | #define MAX77693_CONTROL2_ACCDET_SHIFT 5 |
367 | #define MAX77693_CONTROL2_USBCPINT_SHIFT 6 |
368 | #define MAX77693_CONTROL2_RCPS_SHIFT 7 |
369 | #define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT) |
370 | #define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT) |
371 | #define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT) |
372 | #define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT) |
373 | #define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT) |
374 | #define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT) |
375 | #define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT) |
376 | #define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT) |
377 | |
378 | #define MAX77693_CONTROL3_JIGSET_SHIFT 0 |
379 | #define MAX77693_CONTROL3_BTLDSET_SHIFT 2 |
380 | #define MAX77693_CONTROL3_ADCDBSET_SHIFT 4 |
381 | #define MAX77693_CONTROL3_JIGSET_MASK (0x3 << MAX77693_CONTROL3_JIGSET_SHIFT) |
382 | #define MAX77693_CONTROL3_BTLDSET_MASK (0x3 << MAX77693_CONTROL3_BTLDSET_SHIFT) |
383 | #define MAX77693_CONTROL3_ADCDBSET_MASK (0x3 << MAX77693_CONTROL3_ADCDBSET_SHIFT) |
384 | |
385 | /* Slave addr = 0x90: Haptic */ |
386 | enum max77693_haptic_reg { |
387 | MAX77693_HAPTIC_REG_STATUS = 0x00, |
388 | MAX77693_HAPTIC_REG_CONFIG1 = 0x01, |
389 | MAX77693_HAPTIC_REG_CONFIG2 = 0x02, |
390 | MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03, |
391 | MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04, |
392 | MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05, |
393 | MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06, |
394 | MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07, |
395 | MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08, |
396 | MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09, |
397 | MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A, |
398 | MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B, |
399 | MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C, |
400 | MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D, |
401 | MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E, |
402 | MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F, |
403 | MAX77693_HAPTIC_REG_REV = 0x10, |
404 | |
405 | MAX77693_HAPTIC_REG_END, |
406 | }; |
407 | |
408 | /* max77693-pmic LSCNFG configuration register */ |
409 | #define MAX77693_PMIC_LOW_SYS_MASK 0x80 |
410 | #define MAX77693_PMIC_LOW_SYS_SHIFT 7 |
411 | |
412 | /* max77693-haptic configuration register */ |
413 | #define MAX77693_CONFIG2_MODE 7 |
414 | #define MAX77693_CONFIG2_MEN 6 |
415 | #define MAX77693_CONFIG2_HTYP 5 |
416 | |
417 | enum max77693_irq_source { |
418 | LED_INT = 0, |
419 | TOPSYS_INT, |
420 | CHG_INT, |
421 | MUIC_INT1, |
422 | MUIC_INT2, |
423 | MUIC_INT3, |
424 | |
425 | MAX77693_IRQ_GROUP_NR, |
426 | }; |
427 | |
428 | #define SRC_IRQ_CHARGER BIT(0) |
429 | #define SRC_IRQ_TOP BIT(1) |
430 | #define SRC_IRQ_FLASH BIT(2) |
431 | #define SRC_IRQ_MUIC BIT(3) |
432 | #define SRC_IRQ_ALL (SRC_IRQ_CHARGER | SRC_IRQ_TOP \ |
433 | | SRC_IRQ_FLASH | SRC_IRQ_MUIC) |
434 | |
435 | #define LED_IRQ_FLED2_OPEN BIT(0) |
436 | #define LED_IRQ_FLED2_SHORT BIT(1) |
437 | #define LED_IRQ_FLED1_OPEN BIT(2) |
438 | #define LED_IRQ_FLED1_SHORT BIT(3) |
439 | #define LED_IRQ_MAX_FLASH BIT(4) |
440 | |
441 | #define TOPSYS_IRQ_T120C_INT BIT(0) |
442 | #define TOPSYS_IRQ_T140C_INT BIT(1) |
443 | #define TOPSYS_IRQ_LOWSYS_INT BIT(3) |
444 | |
445 | #define CHG_IRQ_BYP_I BIT(0) |
446 | #define CHG_IRQ_THM_I BIT(2) |
447 | #define CHG_IRQ_BAT_I BIT(3) |
448 | #define CHG_IRQ_CHG_I BIT(4) |
449 | #define CHG_IRQ_CHGIN_I BIT(6) |
450 | |
451 | #define MUIC_IRQ_INT1_ADC BIT(0) |
452 | #define MUIC_IRQ_INT1_ADC_LOW BIT(1) |
453 | #define MUIC_IRQ_INT1_ADC_ERR BIT(2) |
454 | #define MUIC_IRQ_INT1_ADC1K BIT(3) |
455 | |
456 | #define MUIC_IRQ_INT2_CHGTYP BIT(0) |
457 | #define MUIC_IRQ_INT2_CHGDETREUN BIT(1) |
458 | #define MUIC_IRQ_INT2_DCDTMR BIT(2) |
459 | #define MUIC_IRQ_INT2_DXOVP BIT(3) |
460 | #define MUIC_IRQ_INT2_VBVOLT BIT(4) |
461 | #define MUIC_IRQ_INT2_VIDRM BIT(5) |
462 | |
463 | #define MUIC_IRQ_INT3_EOC BIT(0) |
464 | #define MUIC_IRQ_INT3_CGMBC BIT(1) |
465 | #define MUIC_IRQ_INT3_OVP BIT(2) |
466 | #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3) |
467 | #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4) |
468 | #define MUIC_IRQ_INT3_BAT_DET BIT(5) |
469 | |
470 | enum max77693_irq { |
471 | /* PMIC - FLASH */ |
472 | MAX77693_LED_IRQ_FLED2_OPEN, |
473 | MAX77693_LED_IRQ_FLED2_SHORT, |
474 | MAX77693_LED_IRQ_FLED1_OPEN, |
475 | MAX77693_LED_IRQ_FLED1_SHORT, |
476 | MAX77693_LED_IRQ_MAX_FLASH, |
477 | |
478 | /* PMIC - TOPSYS */ |
479 | MAX77693_TOPSYS_IRQ_T120C_INT, |
480 | MAX77693_TOPSYS_IRQ_T140C_INT, |
481 | MAX77693_TOPSYS_IRQ_LOWSYS_INT, |
482 | |
483 | /* PMIC - Charger */ |
484 | MAX77693_CHG_IRQ_BYP_I, |
485 | MAX77693_CHG_IRQ_THM_I, |
486 | MAX77693_CHG_IRQ_BAT_I, |
487 | MAX77693_CHG_IRQ_CHG_I, |
488 | MAX77693_CHG_IRQ_CHGIN_I, |
489 | |
490 | MAX77693_IRQ_NR, |
491 | }; |
492 | |
493 | enum max77693_irq_muic { |
494 | /* MUIC INT1 */ |
495 | MAX77693_MUIC_IRQ_INT1_ADC, |
496 | MAX77693_MUIC_IRQ_INT1_ADC_LOW, |
497 | MAX77693_MUIC_IRQ_INT1_ADC_ERR, |
498 | MAX77693_MUIC_IRQ_INT1_ADC1K, |
499 | |
500 | /* MUIC INT2 */ |
501 | MAX77693_MUIC_IRQ_INT2_CHGTYP, |
502 | MAX77693_MUIC_IRQ_INT2_CHGDETREUN, |
503 | MAX77693_MUIC_IRQ_INT2_DCDTMR, |
504 | MAX77693_MUIC_IRQ_INT2_DXOVP, |
505 | MAX77693_MUIC_IRQ_INT2_VBVOLT, |
506 | MAX77693_MUIC_IRQ_INT2_VIDRM, |
507 | |
508 | /* MUIC INT3 */ |
509 | MAX77693_MUIC_IRQ_INT3_EOC, |
510 | MAX77693_MUIC_IRQ_INT3_CGMBC, |
511 | MAX77693_MUIC_IRQ_INT3_OVP, |
512 | MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, |
513 | MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, |
514 | MAX77693_MUIC_IRQ_INT3_BAT_DET, |
515 | |
516 | MAX77693_MUIC_IRQ_NR, |
517 | }; |
518 | |
519 | #endif /* __LINUX_MFD_MAX77693_PRIV_H */ |
520 | |