1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2022 BayLibre, SAS |
4 | * Author: Fabien Parent <fparent@baylibre.com> |
5 | */ |
6 | |
7 | #ifndef __MFD_MT6357_CORE_H__ |
8 | #define __MFD_MT6357_CORE_H__ |
9 | |
10 | enum mt6357_irq_top_status_shift { |
11 | MT6357_BUCK_TOP = 0, |
12 | MT6357_LDO_TOP, |
13 | MT6357_PSC_TOP, |
14 | MT6357_SCK_TOP, |
15 | MT6357_BM_TOP, |
16 | MT6357_HK_TOP, |
17 | MT6357_XPP_TOP, |
18 | MT6357_AUD_TOP, |
19 | MT6357_MISC_TOP, |
20 | }; |
21 | |
22 | enum mt6357_irq_numbers { |
23 | MT6357_IRQ_VPROC_OC = 0, |
24 | MT6357_IRQ_VCORE_OC, |
25 | MT6357_IRQ_VMODEM_OC, |
26 | MT6357_IRQ_VS1_OC, |
27 | MT6357_IRQ_VPA_OC, |
28 | MT6357_IRQ_VCORE_PREOC, |
29 | MT6357_IRQ_VFE28_OC = 16, |
30 | MT6357_IRQ_VXO22_OC, |
31 | MT6357_IRQ_VRF18_OC, |
32 | MT6357_IRQ_VRF12_OC, |
33 | MT6357_IRQ_VEFUSE_OC, |
34 | MT6357_IRQ_VCN33_OC, |
35 | MT6357_IRQ_VCN28_OC, |
36 | MT6357_IRQ_VCN18_OC, |
37 | MT6357_IRQ_VCAMA_OC, |
38 | MT6357_IRQ_VCAMD_OC, |
39 | MT6357_IRQ_VCAMIO_OC, |
40 | MT6357_IRQ_VLDO28_OC, |
41 | MT6357_IRQ_VUSB33_OC, |
42 | MT6357_IRQ_VAUX18_OC, |
43 | MT6357_IRQ_VAUD28_OC, |
44 | MT6357_IRQ_VIO28_OC, |
45 | MT6357_IRQ_VIO18_OC, |
46 | MT6357_IRQ_VSRAM_PROC_OC, |
47 | MT6357_IRQ_VSRAM_OTHERS_OC, |
48 | MT6357_IRQ_VIBR_OC, |
49 | MT6357_IRQ_VDRAM_OC, |
50 | MT6357_IRQ_VMC_OC, |
51 | MT6357_IRQ_VMCH_OC, |
52 | MT6357_IRQ_VEMC_OC, |
53 | MT6357_IRQ_VSIM1_OC, |
54 | MT6357_IRQ_VSIM2_OC, |
55 | MT6357_IRQ_PWRKEY = 48, |
56 | MT6357_IRQ_HOMEKEY, |
57 | MT6357_IRQ_PWRKEY_R, |
58 | MT6357_IRQ_HOMEKEY_R, |
59 | MT6357_IRQ_NI_LBAT_INT, |
60 | MT6357_IRQ_CHRDET, |
61 | MT6357_IRQ_CHRDET_EDGE, |
62 | MT6357_IRQ_VCDT_HV_DET, |
63 | MT6357_IRQ_WATCHDOG, |
64 | MT6357_IRQ_VBATON_UNDET, |
65 | MT6357_IRQ_BVALID_DET, |
66 | MT6357_IRQ_OV, |
67 | MT6357_IRQ_RTC = 64, |
68 | MT6357_IRQ_FG_BAT0_H = 80, |
69 | MT6357_IRQ_FG_BAT0_L, |
70 | MT6357_IRQ_FG_CUR_H, |
71 | MT6357_IRQ_FG_CUR_L, |
72 | MT6357_IRQ_FG_ZCV, |
73 | MT6357_IRQ_BATON_LV = 96, |
74 | MT6357_IRQ_BATON_HT, |
75 | MT6357_IRQ_BAT_H = 112, |
76 | MT6357_IRQ_BAT_L, |
77 | MT6357_IRQ_AUXADC_IMP, |
78 | MT6357_IRQ_NAG_C_DLTV, |
79 | MT6357_IRQ_AUDIO = 128, |
80 | MT6357_IRQ_ACCDET = 133, |
81 | MT6357_IRQ_ACCDET_EINT0, |
82 | MT6357_IRQ_ACCDET_EINT1, |
83 | MT6357_IRQ_SPI_CMD_ALERT = 144, |
84 | MT6357_IRQ_NR, |
85 | }; |
86 | |
87 | #define MT6357_IRQ_BUCK_BASE MT6357_IRQ_VPROC_OC |
88 | #define MT6357_IRQ_LDO_BASE MT6357_IRQ_VFE28_OC |
89 | #define MT6357_IRQ_PSC_BASE MT6357_IRQ_PWRKEY |
90 | #define MT6357_IRQ_SCK_BASE MT6357_IRQ_RTC |
91 | #define MT6357_IRQ_BM_BASE MT6357_IRQ_FG_BAT0_H |
92 | #define MT6357_IRQ_HK_BASE MT6357_IRQ_BAT_H |
93 | #define MT6357_IRQ_AUD_BASE MT6357_IRQ_AUDIO |
94 | #define MT6357_IRQ_MISC_BASE MT6357_IRQ_SPI_CMD_ALERT |
95 | |
96 | #define MT6357_IRQ_BUCK_BITS (MT6357_IRQ_VCORE_PREOC - MT6357_IRQ_BUCK_BASE + 1) |
97 | #define MT6357_IRQ_LDO_BITS (MT6357_IRQ_VSIM2_OC - MT6357_IRQ_LDO_BASE + 1) |
98 | #define MT6357_IRQ_PSC_BITS (MT6357_IRQ_VCDT_HV_DET - MT6357_IRQ_PSC_BASE + 1) |
99 | #define MT6357_IRQ_SCK_BITS (MT6357_IRQ_RTC - MT6357_IRQ_SCK_BASE + 1) |
100 | #define MT6357_IRQ_BM_BITS (MT6357_IRQ_BATON_HT - MT6357_IRQ_BM_BASE + 1) |
101 | #define MT6357_IRQ_HK_BITS (MT6357_IRQ_NAG_C_DLTV - MT6357_IRQ_HK_BASE + 1) |
102 | #define MT6357_IRQ_AUD_BITS (MT6357_IRQ_ACCDET_EINT1 - MT6357_IRQ_AUD_BASE + 1) |
103 | #define MT6357_IRQ_MISC_BITS \ |
104 | (MT6357_IRQ_SPI_CMD_ALERT - MT6357_IRQ_MISC_BASE + 1) |
105 | |
106 | #define MT6357_TOP_GEN(sp) \ |
107 | { \ |
108 | .hwirq_base = MT6357_IRQ_##sp##_BASE, \ |
109 | .num_int_regs = \ |
110 | ((MT6357_IRQ_##sp##_BITS - 1) / \ |
111 | MTK_PMIC_REG_WIDTH) + 1, \ |
112 | .en_reg = MT6357_##sp##_TOP_INT_CON0, \ |
113 | .en_reg_shift = 0x6, \ |
114 | .sta_reg = MT6357_##sp##_TOP_INT_STATUS0, \ |
115 | .sta_reg_shift = 0x2, \ |
116 | .top_offset = MT6357_##sp##_TOP, \ |
117 | } |
118 | |
119 | #endif /* __MFD_MT6357_CORE_H__ */ |
120 | |