1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* Copyright (C) 2021 ROHM Semiconductors */ |
3 | |
4 | #ifndef __LINUX_MFD_BD957X_H__ |
5 | #define __LINUX_MFD_BD957X_H__ |
6 | |
7 | enum { |
8 | BD957X_VD50, |
9 | BD957X_VD18, |
10 | BD957X_VDDDR, |
11 | BD957X_VD10, |
12 | BD957X_VOUTL1, |
13 | BD957X_VOUTS1, |
14 | }; |
15 | |
16 | /* |
17 | * The BD9576 has own IRQ 'blocks' for: |
18 | * - I2C/thermal, |
19 | * - Over voltage protection |
20 | * - Short-circuit protection |
21 | * - Over current protection |
22 | * - Over voltage detection |
23 | * - Under voltage detection |
24 | * - Under voltage protection |
25 | * - 'system interrupt'. |
26 | * |
27 | * Each of the blocks have a status register giving more accurate IRQ source |
28 | * information - for example which of the regulators have over-voltage. |
29 | * |
30 | * On top of this, there is "main IRQ" status register where each bit indicates |
31 | * which of sub-blocks have active IRQs. Fine. That would fit regmap-irq main |
32 | * status handling. Except that: |
33 | * - Only some sub-IRQs can be masked. |
34 | * - The IRQ informs us about fault-condition, not when fault state changes. |
35 | * The IRQ line it is kept asserted until the detected condition is acked |
36 | * AND cleared in HW. This is annoying for IRQs like the one informing high |
37 | * temperature because if IRQ is not disabled it keeps the CPU in IRQ |
38 | * handling loop. |
39 | * |
40 | * For now we do just use the main-IRQ register as source for our IRQ |
41 | * information and bind the regmap-irq to this. We leave fine-grained sub-IRQ |
42 | * register handling to handlers in sub-devices. The regulator driver shall |
43 | * read which regulators are source for problem - or if the detected error is |
44 | * regulator temperature error. The sub-drivers do also handle masking of "sub- |
45 | * IRQs" if this is supported/needed. |
46 | * |
47 | * To overcome the problem with HW keeping IRQ asserted we do call |
48 | * disable_irq_nosync() from sub-device handler and add a delayed work to |
49 | * re-enable IRQ roughly 1 second later. This should keep our CPU out of |
50 | * busy-loop. |
51 | */ |
52 | #define IRQS_SILENT_MS 1000 |
53 | |
54 | enum { |
55 | BD9576_INT_THERM, |
56 | BD9576_INT_OVP, |
57 | BD9576_INT_SCP, |
58 | BD9576_INT_OCP, |
59 | BD9576_INT_OVD, |
60 | BD9576_INT_UVD, |
61 | BD9576_INT_UVP, |
62 | BD9576_INT_SYS, |
63 | }; |
64 | |
65 | #define BD957X_REG_SMRB_ASSERT 0x15 |
66 | #define BD957X_REG_PMIC_INTERNAL_STAT 0x20 |
67 | #define BD957X_REG_INT_THERM_STAT 0x23 |
68 | #define BD957X_REG_INT_THERM_MASK 0x24 |
69 | #define BD957X_REG_INT_OVP_STAT 0x25 |
70 | #define BD957X_REG_INT_SCP_STAT 0x26 |
71 | #define BD957X_REG_INT_OCP_STAT 0x27 |
72 | #define BD957X_REG_INT_OVD_STAT 0x28 |
73 | #define BD957X_REG_INT_UVD_STAT 0x29 |
74 | #define BD957X_REG_INT_UVP_STAT 0x2a |
75 | #define BD957X_REG_INT_SYS_STAT 0x2b |
76 | #define BD957X_REG_INT_SYS_MASK 0x2c |
77 | #define BD957X_REG_INT_MAIN_STAT 0x30 |
78 | #define BD957X_REG_INT_MAIN_MASK 0x31 |
79 | |
80 | #define UVD_IRQ_VALID_MASK 0x6F |
81 | #define OVD_IRQ_VALID_MASK 0x2F |
82 | |
83 | #define BD957X_MASK_INT_MAIN_THERM BIT(0) |
84 | #define BD957X_MASK_INT_MAIN_OVP BIT(1) |
85 | #define BD957X_MASK_INT_MAIN_SCP BIT(2) |
86 | #define BD957X_MASK_INT_MAIN_OCP BIT(3) |
87 | #define BD957X_MASK_INT_MAIN_OVD BIT(4) |
88 | #define BD957X_MASK_INT_MAIN_UVD BIT(5) |
89 | #define BD957X_MASK_INT_MAIN_UVP BIT(6) |
90 | #define BD957X_MASK_INT_MAIN_SYS BIT(7) |
91 | #define BD957X_MASK_INT_ALL 0xff |
92 | |
93 | #define BD957X_REG_WDT_CONF 0x16 |
94 | |
95 | #define BD957X_REG_POW_TRIGGER1 0x41 |
96 | #define BD957X_REG_POW_TRIGGER2 0x42 |
97 | #define BD957X_REG_POW_TRIGGER3 0x43 |
98 | #define BD957X_REG_POW_TRIGGER4 0x44 |
99 | #define BD957X_REG_POW_TRIGGERL1 0x45 |
100 | #define BD957X_REG_POW_TRIGGERS1 0x46 |
101 | |
102 | #define BD957X_REGULATOR_EN_MASK 0xff |
103 | #define BD957X_REGULATOR_DIS_VAL 0xff |
104 | |
105 | #define BD957X_VSEL_REG_MASK 0xff |
106 | |
107 | #define BD957X_MASK_VOUT1_TUNE 0x87 |
108 | #define BD957X_MASK_VOUT2_TUNE 0x87 |
109 | #define BD957X_MASK_VOUT3_TUNE 0x1f |
110 | #define BD957X_MASK_VOUT4_TUNE 0x1f |
111 | #define BD957X_MASK_VOUTL1_TUNE 0x87 |
112 | |
113 | #define BD957X_REG_VOUT1_TUNE 0x50 |
114 | #define BD957X_REG_VOUT2_TUNE 0x53 |
115 | #define BD957X_REG_VOUT3_TUNE 0x56 |
116 | #define BD957X_REG_VOUT4_TUNE 0x59 |
117 | #define BD957X_REG_VOUTL1_TUNE 0x5c |
118 | |
119 | #define BD9576_REG_VOUT1_OVD 0x51 |
120 | #define BD9576_REG_VOUT1_UVD 0x52 |
121 | #define BD9576_REG_VOUT2_OVD 0x54 |
122 | #define BD9576_REG_VOUT2_UVD 0x55 |
123 | #define BD9576_REG_VOUT3_OVD 0x57 |
124 | #define BD9576_REG_VOUT3_UVD 0x58 |
125 | #define BD9576_REG_VOUT4_OVD 0x5a |
126 | #define BD9576_REG_VOUT4_UVD 0x5b |
127 | #define BD9576_REG_VOUTL1_OVD 0x5d |
128 | #define BD9576_REG_VOUTL1_UVD 0x5e |
129 | |
130 | #define BD9576_MASK_XVD 0x7f |
131 | |
132 | #define BD9576_REG_VOUT1S_OCW 0x5f |
133 | #define BD9576_REG_VOUT1S_OCP 0x60 |
134 | |
135 | #define BD9576_MASK_VOUT1S_OCW 0x3f |
136 | #define BD9576_MASK_VOUT1S_OCP 0x3f |
137 | |
138 | #define BD957X_MAX_REGISTER 0x61 |
139 | |
140 | #endif |
141 | |