1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
4 | */ |
5 | |
6 | #ifndef __LINUX_IMX6Q_IOMUXC_GPR_H |
7 | #define __LINUX_IMX6Q_IOMUXC_GPR_H |
8 | |
9 | #include <linux/bitops.h> |
10 | |
11 | #define IOMUXC_GPR0 0x00 |
12 | #define IOMUXC_GPR1 0x04 |
13 | #define IOMUXC_GPR2 0x08 |
14 | #define IOMUXC_GPR3 0x0c |
15 | #define IOMUXC_GPR4 0x10 |
16 | #define IOMUXC_GPR5 0x14 |
17 | #define IOMUXC_GPR6 0x18 |
18 | #define IOMUXC_GPR7 0x1c |
19 | #define IOMUXC_GPR8 0x20 |
20 | #define IOMUXC_GPR9 0x24 |
21 | #define IOMUXC_GPR10 0x28 |
22 | #define IOMUXC_GPR11 0x2c |
23 | #define IOMUXC_GPR12 0x30 |
24 | #define IOMUXC_GPR13 0x34 |
25 | |
26 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30) |
27 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30) |
28 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30) |
29 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30) |
30 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30) |
31 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28) |
32 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28) |
33 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28) |
34 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28) |
35 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26) |
36 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26) |
37 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26) |
38 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26) |
39 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26) |
40 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24) |
41 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24) |
42 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24) |
43 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24) |
44 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24) |
45 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22) |
46 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22) |
47 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22) |
48 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22) |
49 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22) |
50 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20) |
51 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20) |
52 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20) |
53 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20) |
54 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20) |
55 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18) |
56 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18) |
57 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18) |
58 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18) |
59 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18) |
60 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16) |
61 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16) |
62 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16) |
63 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16) |
64 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16) |
65 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14) |
66 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14) |
67 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14) |
68 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14) |
69 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7) |
70 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0 |
71 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7) |
72 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6) |
73 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0 |
74 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6) |
75 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5) |
76 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0 |
77 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5) |
78 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4) |
79 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0 |
80 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4) |
81 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3) |
82 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0 |
83 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3) |
84 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2) |
85 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0 |
86 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2) |
87 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1) |
88 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0 |
89 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1) |
90 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0) |
91 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0 |
92 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0) |
93 | |
94 | #define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30) |
95 | #define IMX6Q_GPR1_PCIE_SW_RST BIT(29) |
96 | #define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28) |
97 | #define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27) |
98 | #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) |
99 | #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) |
100 | #define IMX6Q_GPR1_DPI_OFF BIT(24) |
101 | #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) |
102 | #define IMX6Q_GPR1_EXC_MON_OKAY 0x0 |
103 | #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) |
104 | #define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21) |
105 | #define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0 |
106 | #define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21) |
107 | #define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20) |
108 | #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0 |
109 | #define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) |
110 | #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19) |
111 | #define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0 |
112 | #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) |
113 | #define IMX6Q_GPR1_PCIE_TEST_PD BIT(18) |
114 | #define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17) |
115 | #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0 |
116 | #define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17) |
117 | #define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16) |
118 | #define IMX6Q_GPR1_USB_EXP_MODE BIT(15) |
119 | #define IMX6Q_GPR1_PCIE_INT BIT(14) |
120 | #define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13) |
121 | #define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0 |
122 | #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13) |
123 | #define IMX6Q_GPR1_GINT BIT(12) |
124 | #define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10) |
125 | #define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10) |
126 | #define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10) |
127 | #define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10) |
128 | #define IMX6Q_GPR1_ACT_CS3 BIT(9) |
129 | #define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7) |
130 | #define IMX6Q_GPR1_ACT_CS2 BIT(6) |
131 | #define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4) |
132 | #define IMX6Q_GPR1_ACT_CS1 BIT(3) |
133 | #define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1) |
134 | #define IMX6Q_GPR1_ACT_CS0 BIT(0) |
135 | |
136 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20) |
137 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20) |
138 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20) |
139 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20) |
140 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20) |
141 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16) |
142 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16) |
143 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16) |
144 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16) |
145 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16) |
146 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16) |
147 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16) |
148 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16) |
149 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16) |
150 | #define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15) |
151 | #define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0 |
152 | #define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15) |
153 | #define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10) |
154 | #define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0 |
155 | #define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10) |
156 | #define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9) |
157 | #define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0 |
158 | #define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9) |
159 | #define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8) |
160 | #define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0 |
161 | #define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8) |
162 | #define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7) |
163 | #define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0 |
164 | #define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7) |
165 | #define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6) |
166 | #define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0 |
167 | #define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6) |
168 | #define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5) |
169 | #define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0 |
170 | #define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5) |
171 | #define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4) |
172 | #define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2) |
173 | #define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2) |
174 | #define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2) |
175 | #define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2) |
176 | #define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0) |
177 | #define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0) |
178 | #define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0) |
179 | #define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0) |
180 | |
181 | #define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29) |
182 | #define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29) |
183 | #define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29) |
184 | #define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29) |
185 | #define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28) |
186 | #define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27) |
187 | #define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26) |
188 | #define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25) |
189 | #define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21) |
190 | #define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17) |
191 | #define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16) |
192 | #define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15) |
193 | #define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14) |
194 | #define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13) |
195 | #define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12) |
196 | #define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11) |
197 | #define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10) |
198 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) |
199 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) |
200 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) |
201 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8) |
202 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8) |
203 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) |
204 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) |
205 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) |
206 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) |
207 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) |
208 | #define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 |
209 | #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) |
210 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) |
211 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) |
212 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4) |
213 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4) |
214 | #define IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT 2 |
215 | #define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2) |
216 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2) |
217 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2) |
218 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2) |
219 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2) |
220 | |
221 | #define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31) |
222 | #define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30) |
223 | #define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29) |
224 | #define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28) |
225 | #define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27) |
226 | #define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26) |
227 | #define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25) |
228 | #define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24) |
229 | #define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19) |
230 | #define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18) |
231 | #define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17) |
232 | #define IMX6Q_GPR4_ENET_STOP_ACK BIT(16) |
233 | #define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8) |
234 | #define IMX6Q_GPR4_SOC_VERSION_OFF 0x8 |
235 | #define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7) |
236 | #define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6) |
237 | #define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3) |
238 | #define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2) |
239 | #define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1) |
240 | #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) |
241 | |
242 | #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) |
243 | #define IMX6Q_GPR5_SATA_SW_PD BIT(10) |
244 | #define IMX6Q_GPR5_SATA_SW_RST BIT(11) |
245 | |
246 | #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) |
247 | #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) |
248 | #define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8) |
249 | #define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12) |
250 | #define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16) |
251 | #define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20) |
252 | #define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24) |
253 | #define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28) |
254 | |
255 | #define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0) |
256 | #define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4) |
257 | #define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8) |
258 | #define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12) |
259 | #define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16) |
260 | #define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20) |
261 | #define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24) |
262 | #define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28) |
263 | |
264 | #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) |
265 | #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) |
266 | #define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) |
267 | #define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) |
268 | #define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) |
269 | |
270 | #define IMX6Q_GPR9_TZASC2_BYP BIT(1) |
271 | #define IMX6Q_GPR9_TZASC1_BYP BIT(0) |
272 | |
273 | #define IMX6Q_GPR10_LOCK_DBG_EN BIT(29) |
274 | #define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28) |
275 | #define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27) |
276 | #define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21) |
277 | #define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20) |
278 | #define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18) |
279 | #define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16) |
280 | #define IMX6Q_GPR10_DBG_EN BIT(13) |
281 | #define IMX6Q_GPR10_DBG_CLK_EN BIT(12) |
282 | #define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11) |
283 | #define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0 |
284 | #define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11) |
285 | #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) |
286 | #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) |
287 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) |
288 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) |
289 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) |
290 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) |
291 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) |
292 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) |
293 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) |
294 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) |
295 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) |
296 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) |
297 | |
298 | #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) |
299 | #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) |
300 | #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) |
301 | #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) |
302 | #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) |
303 | #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) |
304 | #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) |
305 | |
306 | #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) |
307 | #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) |
308 | #define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28) |
309 | #define IMX6Q_GPR13_ENET_STOP_REQ BIT(27) |
310 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24) |
311 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24) |
312 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24) |
313 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24) |
314 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24) |
315 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24) |
316 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24) |
317 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24) |
318 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24) |
319 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19) |
320 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19) |
321 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19) |
322 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19) |
323 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19) |
324 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19) |
325 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19) |
326 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16) |
327 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16) |
328 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16) |
329 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16) |
330 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16) |
331 | #define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15) |
332 | #define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0 |
333 | #define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15) |
334 | #define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14) |
335 | #define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11) |
336 | #define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11) |
337 | #define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11) |
338 | #define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11) |
339 | #define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11) |
340 | #define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11) |
341 | #define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11) |
342 | #define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7) |
343 | #define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7) |
344 | #define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7) |
345 | #define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7) |
346 | #define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7) |
347 | #define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7) |
348 | #define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7) |
349 | #define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7) |
350 | #define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7) |
351 | #define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7) |
352 | #define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7) |
353 | #define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7) |
354 | #define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7) |
355 | #define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7) |
356 | #define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7) |
357 | #define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7) |
358 | #define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7) |
359 | #define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2) |
360 | #define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2) |
361 | #define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2) |
362 | #define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2) |
363 | #define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2) |
364 | #define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2) |
365 | #define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2) |
366 | #define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2) |
367 | #define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2) |
368 | #define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2) |
369 | #define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2) |
370 | #define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2) |
371 | #define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2) |
372 | #define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2) |
373 | #define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2) |
374 | #define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2) |
375 | #define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2) |
376 | #define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2) |
377 | #define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2) |
378 | #define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2) |
379 | #define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2) |
380 | #define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2) |
381 | #define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2) |
382 | #define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2) |
383 | #define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2) |
384 | #define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2) |
385 | #define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2) |
386 | #define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2) |
387 | #define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2) |
388 | #define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2) |
389 | #define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2) |
390 | #define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2) |
391 | #define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2) |
392 | #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) |
393 | #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) |
394 | |
395 | /* For imx6sl iomux gpr register field define */ |
396 | #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) |
397 | #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) |
398 | |
399 | /* For imx6sx iomux gpr register field define */ |
400 | #define IMX6SX_GPR1_VDEC_SW_RST_MASK (0x1 << 20) |
401 | #define IMX6SX_GPR1_VDEC_SW_RST_RESET (0x1 << 20) |
402 | #define IMX6SX_GPR1_VDEC_SW_RST_RELEASE (0x0 << 20) |
403 | #define IMX6SX_GPR1_VADC_SW_RST_MASK (0x1 << 19) |
404 | #define IMX6SX_GPR1_VADC_SW_RST_RESET (0x1 << 19) |
405 | #define IMX6SX_GPR1_VADC_SW_RST_RELEASE (0x0 << 19) |
406 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK (0x3 << 13) |
407 | #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17) |
408 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13) |
409 | |
410 | #define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26) |
411 | #define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26) |
412 | #define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25) |
413 | #define IMX6SX_GPR2_MQS_EN_SHIFT (25) |
414 | #define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24) |
415 | #define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24) |
416 | #define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16) |
417 | #define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16) |
418 | |
419 | #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3) |
420 | #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4) |
421 | |
422 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) |
423 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) |
424 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) |
425 | |
426 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK (0x3 << 27) |
427 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN (0x0 << 27) |
428 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD (0x1 << 27) |
429 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI (0x2 << 27) |
430 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_GND (0x3 << 27) |
431 | #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26) |
432 | #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26) |
433 | #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26) |
434 | #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19) |
435 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) |
436 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) |
437 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) |
438 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) |
439 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) |
440 | |
441 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2 (0x0 << 2) |
442 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS (0x1 << 2) |
443 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK (0x1 << 2) |
444 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1 (0x0 << 1) |
445 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) |
446 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) |
447 | |
448 | #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) |
449 | #define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) |
450 | #define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0) |
451 | #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) |
452 | |
453 | /* For imx6ul iomux gpr register field define */ |
454 | #define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) |
455 | #define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) |
456 | #define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) |
457 | #define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) |
458 | #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) |
459 | #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) |
460 | #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) |
461 | #define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17) |
462 | #define IMX6UL_GPR1_SAI1_MCLK_DIR (0x1 << 19) |
463 | #define IMX6UL_GPR1_SAI2_MCLK_DIR (0x1 << 20) |
464 | #define IMX6UL_GPR1_SAI3_MCLK_DIR (0x1 << 21) |
465 | #define IMX6UL_GPR1_SAI_MCLK_MASK (0x7 << 19) |
466 | #define MCLK_DIR(x) (x == 1 ? IMX6UL_GPR1_SAI1_MCLK_DIR : x == 2 ? \ |
467 | IMX6UL_GPR1_SAI2_MCLK_DIR : IMX6UL_GPR1_SAI3_MCLK_DIR) |
468 | |
469 | /* For imx6sll iomux gpr register field define */ |
470 | #define IMX6SLL_GPR5_AFCG_X_BYPASS_MASK (0x1f << 11) |
471 | |
472 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |
473 | |