1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * MFD driver for twl4030 audio submodule |
4 | * |
5 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
6 | * |
7 | * Copyright: (C) 2009 Nokia Corporation |
8 | */ |
9 | |
10 | #ifndef __TWL4030_CODEC_H__ |
11 | #define __TWL4030_CODEC_H__ |
12 | |
13 | /* Codec registers */ |
14 | #define TWL4030_REG_CODEC_MODE 0x01 |
15 | #define TWL4030_REG_OPTION 0x02 |
16 | #define TWL4030_REG_UNKNOWN 0x03 |
17 | #define TWL4030_REG_MICBIAS_CTL 0x04 |
18 | #define TWL4030_REG_ANAMICL 0x05 |
19 | #define TWL4030_REG_ANAMICR 0x06 |
20 | #define TWL4030_REG_AVADC_CTL 0x07 |
21 | #define TWL4030_REG_ADCMICSEL 0x08 |
22 | #define TWL4030_REG_DIGMIXING 0x09 |
23 | #define TWL4030_REG_ATXL1PGA 0x0A |
24 | #define TWL4030_REG_ATXR1PGA 0x0B |
25 | #define TWL4030_REG_AVTXL2PGA 0x0C |
26 | #define TWL4030_REG_AVTXR2PGA 0x0D |
27 | #define TWL4030_REG_AUDIO_IF 0x0E |
28 | #define TWL4030_REG_VOICE_IF 0x0F |
29 | #define TWL4030_REG_ARXR1PGA 0x10 |
30 | #define TWL4030_REG_ARXL1PGA 0x11 |
31 | #define TWL4030_REG_ARXR2PGA 0x12 |
32 | #define TWL4030_REG_ARXL2PGA 0x13 |
33 | #define TWL4030_REG_VRXPGA 0x14 |
34 | #define TWL4030_REG_VSTPGA 0x15 |
35 | #define TWL4030_REG_VRX2ARXPGA 0x16 |
36 | #define TWL4030_REG_AVDAC_CTL 0x17 |
37 | #define TWL4030_REG_ARX2VTXPGA 0x18 |
38 | #define TWL4030_REG_ARXL1_APGA_CTL 0x19 |
39 | #define TWL4030_REG_ARXR1_APGA_CTL 0x1A |
40 | #define TWL4030_REG_ARXL2_APGA_CTL 0x1B |
41 | #define TWL4030_REG_ARXR2_APGA_CTL 0x1C |
42 | #define TWL4030_REG_ATX2ARXPGA 0x1D |
43 | #define TWL4030_REG_BT_IF 0x1E |
44 | #define TWL4030_REG_BTPGA 0x1F |
45 | #define TWL4030_REG_BTSTPGA 0x20 |
46 | #define TWL4030_REG_EAR_CTL 0x21 |
47 | #define TWL4030_REG_HS_SEL 0x22 |
48 | #define TWL4030_REG_HS_GAIN_SET 0x23 |
49 | #define TWL4030_REG_HS_POPN_SET 0x24 |
50 | #define TWL4030_REG_PREDL_CTL 0x25 |
51 | #define TWL4030_REG_PREDR_CTL 0x26 |
52 | #define TWL4030_REG_PRECKL_CTL 0x27 |
53 | #define TWL4030_REG_PRECKR_CTL 0x28 |
54 | #define TWL4030_REG_HFL_CTL 0x29 |
55 | #define TWL4030_REG_HFR_CTL 0x2A |
56 | #define TWL4030_REG_ALC_CTL 0x2B |
57 | #define TWL4030_REG_ALC_SET1 0x2C |
58 | #define TWL4030_REG_ALC_SET2 0x2D |
59 | #define TWL4030_REG_BOOST_CTL 0x2E |
60 | #define TWL4030_REG_SOFTVOL_CTL 0x2F |
61 | #define TWL4030_REG_DTMF_FREQSEL 0x30 |
62 | #define TWL4030_REG_DTMF_TONEXT1H 0x31 |
63 | #define TWL4030_REG_DTMF_TONEXT1L 0x32 |
64 | #define TWL4030_REG_DTMF_TONEXT2H 0x33 |
65 | #define TWL4030_REG_DTMF_TONEXT2L 0x34 |
66 | #define TWL4030_REG_DTMF_TONOFF 0x35 |
67 | #define TWL4030_REG_DTMF_WANONOFF 0x36 |
68 | #define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 |
69 | #define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 |
70 | #define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 |
71 | #define TWL4030_REG_APLL_CTL 0x3A |
72 | #define TWL4030_REG_DTMF_CTL 0x3B |
73 | #define TWL4030_REG_DTMF_PGA_CTL2 0x3C |
74 | #define TWL4030_REG_DTMF_PGA_CTL1 0x3D |
75 | #define TWL4030_REG_MISC_SET_1 0x3E |
76 | #define TWL4030_REG_PCMBTMUX 0x3F |
77 | #define TWL4030_REG_RX_PATH_SEL 0x43 |
78 | #define TWL4030_REG_VDL_APGA_CTL 0x44 |
79 | #define TWL4030_REG_VIBRA_CTL 0x45 |
80 | #define TWL4030_REG_VIBRA_SET 0x46 |
81 | #define TWL4030_REG_VIBRA_PWM_SET 0x47 |
82 | #define TWL4030_REG_ANAMIC_GAIN 0x48 |
83 | #define TWL4030_REG_MISC_SET_2 0x49 |
84 | |
85 | /* Bitfield Definitions */ |
86 | |
87 | /* TWL4030_CODEC_MODE (0x01) Fields */ |
88 | #define TWL4030_APLL_RATE 0xF0 |
89 | #define TWL4030_APLL_RATE_8000 0x00 |
90 | #define TWL4030_APLL_RATE_11025 0x10 |
91 | #define TWL4030_APLL_RATE_12000 0x20 |
92 | #define TWL4030_APLL_RATE_16000 0x40 |
93 | #define TWL4030_APLL_RATE_22050 0x50 |
94 | #define TWL4030_APLL_RATE_24000 0x60 |
95 | #define TWL4030_APLL_RATE_32000 0x80 |
96 | #define TWL4030_APLL_RATE_44100 0x90 |
97 | #define TWL4030_APLL_RATE_48000 0xA0 |
98 | #define TWL4030_APLL_RATE_96000 0xE0 |
99 | #define TWL4030_SEL_16K 0x08 |
100 | #define TWL4030_CODECPDZ 0x02 |
101 | #define TWL4030_OPT_MODE 0x01 |
102 | #define TWL4030_OPTION_1 (1 << 0) |
103 | #define TWL4030_OPTION_2 (0 << 0) |
104 | |
105 | /* TWL4030_OPTION (0x02) Fields */ |
106 | #define TWL4030_ATXL1_EN (1 << 0) |
107 | #define TWL4030_ATXR1_EN (1 << 1) |
108 | #define TWL4030_ATXL2_VTXL_EN (1 << 2) |
109 | #define TWL4030_ATXR2_VTXR_EN (1 << 3) |
110 | #define TWL4030_ARXL1_VRX_EN (1 << 4) |
111 | #define TWL4030_ARXR1_EN (1 << 5) |
112 | #define TWL4030_ARXL2_EN (1 << 6) |
113 | #define TWL4030_ARXR2_EN (1 << 7) |
114 | |
115 | /* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ |
116 | #define TWL4030_MICBIAS2_CTL 0x40 |
117 | #define TWL4030_MICBIAS1_CTL 0x20 |
118 | #define TWL4030_HSMICBIAS_EN 0x04 |
119 | #define TWL4030_MICBIAS2_EN 0x02 |
120 | #define TWL4030_MICBIAS1_EN 0x01 |
121 | |
122 | /* ANAMICL (0x05) Fields */ |
123 | #define TWL4030_CNCL_OFFSET_START 0x80 |
124 | #define TWL4030_OFFSET_CNCL_SEL 0x60 |
125 | #define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 |
126 | #define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 |
127 | #define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 |
128 | #define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 |
129 | #define TWL4030_MICAMPL_EN 0x10 |
130 | #define TWL4030_CKMIC_EN 0x08 |
131 | #define TWL4030_AUXL_EN 0x04 |
132 | #define TWL4030_HSMIC_EN 0x02 |
133 | #define TWL4030_MAINMIC_EN 0x01 |
134 | |
135 | /* ANAMICR (0x06) Fields */ |
136 | #define TWL4030_MICAMPR_EN 0x10 |
137 | #define TWL4030_AUXR_EN 0x04 |
138 | #define TWL4030_SUBMIC_EN 0x01 |
139 | |
140 | /* AVADC_CTL (0x07) Fields */ |
141 | #define TWL4030_ADCL_EN 0x08 |
142 | #define TWL4030_AVADC_CLK_PRIORITY 0x04 |
143 | #define TWL4030_ADCR_EN 0x02 |
144 | |
145 | /* TWL4030_REG_ADCMICSEL (0x08) Fields */ |
146 | #define TWL4030_DIGMIC1_EN 0x08 |
147 | #define TWL4030_TX2IN_SEL 0x04 |
148 | #define TWL4030_DIGMIC0_EN 0x02 |
149 | #define TWL4030_TX1IN_SEL 0x01 |
150 | |
151 | /* AUDIO_IF (0x0E) Fields */ |
152 | #define TWL4030_AIF_SLAVE_EN 0x80 |
153 | #define TWL4030_DATA_WIDTH 0x60 |
154 | #define TWL4030_DATA_WIDTH_16S_16W 0x00 |
155 | #define TWL4030_DATA_WIDTH_32S_16W 0x40 |
156 | #define TWL4030_DATA_WIDTH_32S_24W 0x60 |
157 | #define TWL4030_AIF_FORMAT 0x18 |
158 | #define TWL4030_AIF_FORMAT_CODEC 0x00 |
159 | #define TWL4030_AIF_FORMAT_LEFT 0x08 |
160 | #define TWL4030_AIF_FORMAT_RIGHT 0x10 |
161 | #define TWL4030_AIF_FORMAT_TDM 0x18 |
162 | #define TWL4030_AIF_TRI_EN 0x04 |
163 | #define TWL4030_CLK256FS_EN 0x02 |
164 | #define TWL4030_AIF_EN 0x01 |
165 | |
166 | /* VOICE_IF (0x0F) Fields */ |
167 | #define TWL4030_VIF_SLAVE_EN 0x80 |
168 | #define TWL4030_VIF_DIN_EN 0x40 |
169 | #define TWL4030_VIF_DOUT_EN 0x20 |
170 | #define TWL4030_VIF_SWAP 0x10 |
171 | #define TWL4030_VIF_FORMAT 0x08 |
172 | #define TWL4030_VIF_TRI_EN 0x04 |
173 | #define TWL4030_VIF_SUB_EN 0x02 |
174 | #define TWL4030_VIF_EN 0x01 |
175 | |
176 | /* EAR_CTL (0x21) */ |
177 | #define TWL4030_EAR_GAIN 0x30 |
178 | |
179 | /* HS_GAIN_SET (0x23) Fields */ |
180 | #define TWL4030_HSR_GAIN 0x0C |
181 | #define TWL4030_HSR_GAIN_PWR_DOWN 0x00 |
182 | #define TWL4030_HSR_GAIN_PLUS_6DB 0x04 |
183 | #define TWL4030_HSR_GAIN_0DB 0x08 |
184 | #define TWL4030_HSR_GAIN_MINUS_6DB 0x0C |
185 | #define TWL4030_HSL_GAIN 0x03 |
186 | #define TWL4030_HSL_GAIN_PWR_DOWN 0x00 |
187 | #define TWL4030_HSL_GAIN_PLUS_6DB 0x01 |
188 | #define TWL4030_HSL_GAIN_0DB 0x02 |
189 | #define TWL4030_HSL_GAIN_MINUS_6DB 0x03 |
190 | |
191 | /* HS_POPN_SET (0x24) Fields */ |
192 | #define TWL4030_VMID_EN 0x40 |
193 | #define TWL4030_EXTMUTE 0x20 |
194 | #define TWL4030_RAMP_DELAY 0x1C |
195 | #define TWL4030_RAMP_DELAY_20MS 0x00 |
196 | #define TWL4030_RAMP_DELAY_40MS 0x04 |
197 | #define TWL4030_RAMP_DELAY_81MS 0x08 |
198 | #define TWL4030_RAMP_DELAY_161MS 0x0C |
199 | #define TWL4030_RAMP_DELAY_323MS 0x10 |
200 | #define TWL4030_RAMP_DELAY_645MS 0x14 |
201 | #define TWL4030_RAMP_DELAY_1291MS 0x18 |
202 | #define TWL4030_RAMP_DELAY_2581MS 0x1C |
203 | #define TWL4030_RAMP_EN 0x02 |
204 | |
205 | /* PREDL_CTL (0x25) */ |
206 | #define TWL4030_PREDL_GAIN 0x30 |
207 | |
208 | /* PREDR_CTL (0x26) */ |
209 | #define TWL4030_PREDR_GAIN 0x30 |
210 | |
211 | /* PRECKL_CTL (0x27) */ |
212 | #define TWL4030_PRECKL_GAIN 0x30 |
213 | |
214 | /* PRECKR_CTL (0x28) */ |
215 | #define TWL4030_PRECKR_GAIN 0x30 |
216 | |
217 | /* HFL_CTL (0x29, 0x2A) Fields */ |
218 | #define TWL4030_HF_CTL_HB_EN 0x04 |
219 | #define TWL4030_HF_CTL_LOOP_EN 0x08 |
220 | #define TWL4030_HF_CTL_RAMP_EN 0x10 |
221 | #define TWL4030_HF_CTL_REF_EN 0x20 |
222 | |
223 | /* APLL_CTL (0x3A) Fields */ |
224 | #define TWL4030_APLL_EN 0x10 |
225 | #define TWL4030_APLL_INFREQ 0x0F |
226 | #define TWL4030_APLL_INFREQ_19200KHZ 0x05 |
227 | #define TWL4030_APLL_INFREQ_26000KHZ 0x06 |
228 | #define TWL4030_APLL_INFREQ_38400KHZ 0x0F |
229 | |
230 | /* REG_MISC_SET_1 (0x3E) Fields */ |
231 | #define TWL4030_CLK64_EN 0x80 |
232 | #define TWL4030_SCRAMBLE_EN 0x40 |
233 | #define TWL4030_FMLOOP_EN 0x20 |
234 | #define TWL4030_SMOOTH_ANAVOL_EN 0x02 |
235 | #define TWL4030_DIGMIC_LR_SWAP_EN 0x01 |
236 | |
237 | /* VIBRA_CTL (0x45) */ |
238 | #define TWL4030_VIBRA_EN 0x01 |
239 | #define TWL4030_VIBRA_DIR 0x02 |
240 | #define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2) |
241 | #define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2) |
242 | #define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2) |
243 | #define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2) |
244 | #define TWL4030_VIBRA_SEL 0x10 |
245 | #define TWL4030_VIBRA_DIR_SEL 0x20 |
246 | |
247 | /* TWL4030 codec resource IDs */ |
248 | enum twl4030_audio_res { |
249 | TWL4030_AUDIO_RES_POWER = 0, |
250 | TWL4030_AUDIO_RES_APLL, |
251 | TWL4030_AUDIO_RES_MAX, |
252 | }; |
253 | |
254 | int twl4030_audio_disable_resource(enum twl4030_audio_res id); |
255 | int twl4030_audio_enable_resource(enum twl4030_audio_res id); |
256 | unsigned int twl4030_audio_get_mclk(void); |
257 | |
258 | #endif /* End of __TWL4030_CODEC_H__ */ |
259 | |