1	/*
2	* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3	*
4	* This software is available to you under a choice of one of two
5	* licenses. You may choose to be licensed under the terms of the GNU
6	* General Public License (GPL) Version 2, available from the file
7	* COPYING in the main directory of this source tree, or the
8	* OpenIB.org BSD license below:
9	*
10	* Redistribution and use in source and binary forms, with or
11	* without modification, are permitted provided that the following
12	* conditions are met:
13	*
14	* - Redistributions of source code must retain the above
15	* copyright notice, this list of conditions and the following
16	* disclaimer.
17	*
18	* - Redistributions in binary form must reproduce the above
19	* copyright notice, this list of conditions and the following
20	* disclaimer in the documentation and/or other materials
21	* provided with the distribution.
22	*
23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30	* SOFTWARE.
31	*/
32	#ifndef MLX5_IFC_H
33	#define MLX5_IFC_H
34
35	#include "mlx5_ifc_fpga.h"
36
37	enum {
38	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46	MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55	MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62	MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64	};
65
66	enum {
67	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
68	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1,
69	MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
70	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
71	MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
72	MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15,
73	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20,
74	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25,
75	};
76
77	enum {
78	MLX5_SHARED_RESOURCE_UID = 0xffff,
79	};
80
81	enum {
82	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23,
84	};
85
86	enum {
87	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
88	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
89	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
91	(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
92	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
93	};
94
95	enum {
96	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
97	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
98	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
99	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
100	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
101	MLX5_OBJ_TYPE_MKEY = 0xff01,
102	MLX5_OBJ_TYPE_QP = 0xff02,
103	MLX5_OBJ_TYPE_PSV = 0xff03,
104	MLX5_OBJ_TYPE_RMP = 0xff04,
105	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
106	MLX5_OBJ_TYPE_RQ = 0xff06,
107	MLX5_OBJ_TYPE_SQ = 0xff07,
108	MLX5_OBJ_TYPE_TIR = 0xff08,
109	MLX5_OBJ_TYPE_TIS = 0xff09,
110	MLX5_OBJ_TYPE_DCT = 0xff0a,
111	MLX5_OBJ_TYPE_XRQ = 0xff0b,
112	MLX5_OBJ_TYPE_RQT = 0xff0e,
113	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114	MLX5_OBJ_TYPE_CQ = 0xff10,
115	};
116
117	enum {
118	MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
119	MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
120	MLX5_CMD_OP_INIT_HCA = 0x102,
121	MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
122	MLX5_CMD_OP_ENABLE_HCA = 0x104,
123	MLX5_CMD_OP_DISABLE_HCA = 0x105,
124	MLX5_CMD_OP_QUERY_PAGES = 0x107,
125	MLX5_CMD_OP_MANAGE_PAGES = 0x108,
126	MLX5_CMD_OP_SET_HCA_CAP = 0x109,
127	MLX5_CMD_OP_QUERY_ISSI = 0x10a,
128	MLX5_CMD_OP_SET_ISSI = 0x10b,
129	MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
130	MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
131	MLX5_CMD_OP_ALLOC_SF = 0x113,
132	MLX5_CMD_OP_DEALLOC_SF = 0x114,
133	MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
134	MLX5_CMD_OP_RESUME_VHCA = 0x116,
135	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
136	MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
137	MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
138	MLX5_CMD_OP_CREATE_MKEY = 0x200,
139	MLX5_CMD_OP_QUERY_MKEY = 0x201,
140	MLX5_CMD_OP_DESTROY_MKEY = 0x202,
141	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
142	MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
143	MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
144	MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
145	MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
146	MLX5_CMD_OP_CREATE_EQ = 0x301,
147	MLX5_CMD_OP_DESTROY_EQ = 0x302,
148	MLX5_CMD_OP_QUERY_EQ = 0x303,
149	MLX5_CMD_OP_GEN_EQE = 0x304,
150	MLX5_CMD_OP_CREATE_CQ = 0x400,
151	MLX5_CMD_OP_DESTROY_CQ = 0x401,
152	MLX5_CMD_OP_QUERY_CQ = 0x402,
153	MLX5_CMD_OP_MODIFY_CQ = 0x403,
154	MLX5_CMD_OP_CREATE_QP = 0x500,
155	MLX5_CMD_OP_DESTROY_QP = 0x501,
156	MLX5_CMD_OP_RST2INIT_QP = 0x502,
157	MLX5_CMD_OP_INIT2RTR_QP = 0x503,
158	MLX5_CMD_OP_RTR2RTS_QP = 0x504,
159	MLX5_CMD_OP_RTS2RTS_QP = 0x505,
160	MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
161	MLX5_CMD_OP_2ERR_QP = 0x507,
162	MLX5_CMD_OP_2RST_QP = 0x50a,
163	MLX5_CMD_OP_QUERY_QP = 0x50b,
164	MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
165	MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
166	MLX5_CMD_OP_CREATE_PSV = 0x600,
167	MLX5_CMD_OP_DESTROY_PSV = 0x601,
168	MLX5_CMD_OP_CREATE_SRQ = 0x700,
169	MLX5_CMD_OP_DESTROY_SRQ = 0x701,
170	MLX5_CMD_OP_QUERY_SRQ = 0x702,
171	MLX5_CMD_OP_ARM_RQ = 0x703,
172	MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
173	MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
174	MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
175	MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
176	MLX5_CMD_OP_CREATE_DCT = 0x710,
177	MLX5_CMD_OP_DESTROY_DCT = 0x711,
178	MLX5_CMD_OP_DRAIN_DCT = 0x712,
179	MLX5_CMD_OP_QUERY_DCT = 0x713,
180	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
181	MLX5_CMD_OP_CREATE_XRQ = 0x717,
182	MLX5_CMD_OP_DESTROY_XRQ = 0x718,
183	MLX5_CMD_OP_QUERY_XRQ = 0x719,
184	MLX5_CMD_OP_ARM_XRQ = 0x71a,
185	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
186	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
187	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
188	MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
189	MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
190	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
191	MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
192	MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
193	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
194	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
195	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
196	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
197	MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
198	MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
199	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
200	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
201	MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
202	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
203	MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
204	MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
205	MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
206	MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
207	MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
208	MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
209	MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
210	MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
211	MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
212	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
213	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
214	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
215	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
216	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
217	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
218	MLX5_CMD_OP_ALLOC_PD = 0x800,
219	MLX5_CMD_OP_DEALLOC_PD = 0x801,
220	MLX5_CMD_OP_ALLOC_UAR = 0x802,
221	MLX5_CMD_OP_DEALLOC_UAR = 0x803,
222	MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
223	MLX5_CMD_OP_ACCESS_REG = 0x805,
224	MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
225	MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
226	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
227	MLX5_CMD_OP_MAD_IFC = 0x50d,
228	MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
229	MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
230	MLX5_CMD_OP_NOP = 0x80d,
231	MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
232	MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
233	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
234	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
235	MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
236	MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
237	MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
238	MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
239	MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
240	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
241	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
242	MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
243	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
244	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
245	MLX5_CMD_OP_SET_WOL_ROL = 0x830,
246	MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
247	MLX5_CMD_OP_CREATE_LAG = 0x840,
248	MLX5_CMD_OP_MODIFY_LAG = 0x841,
249	MLX5_CMD_OP_QUERY_LAG = 0x842,
250	MLX5_CMD_OP_DESTROY_LAG = 0x843,
251	MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
252	MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
253	MLX5_CMD_OP_CREATE_TIR = 0x900,
254	MLX5_CMD_OP_MODIFY_TIR = 0x901,
255	MLX5_CMD_OP_DESTROY_TIR = 0x902,
256	MLX5_CMD_OP_QUERY_TIR = 0x903,
257	MLX5_CMD_OP_CREATE_SQ = 0x904,
258	MLX5_CMD_OP_MODIFY_SQ = 0x905,
259	MLX5_CMD_OP_DESTROY_SQ = 0x906,
260	MLX5_CMD_OP_QUERY_SQ = 0x907,
261	MLX5_CMD_OP_CREATE_RQ = 0x908,
262	MLX5_CMD_OP_MODIFY_RQ = 0x909,
263	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
264	MLX5_CMD_OP_DESTROY_RQ = 0x90a,
265	MLX5_CMD_OP_QUERY_RQ = 0x90b,
266	MLX5_CMD_OP_CREATE_RMP = 0x90c,
267	MLX5_CMD_OP_MODIFY_RMP = 0x90d,
268	MLX5_CMD_OP_DESTROY_RMP = 0x90e,
269	MLX5_CMD_OP_QUERY_RMP = 0x90f,
270	MLX5_CMD_OP_CREATE_TIS = 0x912,
271	MLX5_CMD_OP_MODIFY_TIS = 0x913,
272	MLX5_CMD_OP_DESTROY_TIS = 0x914,
273	MLX5_CMD_OP_QUERY_TIS = 0x915,
274	MLX5_CMD_OP_CREATE_RQT = 0x916,
275	MLX5_CMD_OP_MODIFY_RQT = 0x917,
276	MLX5_CMD_OP_DESTROY_RQT = 0x918,
277	MLX5_CMD_OP_QUERY_RQT = 0x919,
278	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
279	MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
280	MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
281	MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
282	MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
283	MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
284	MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
285	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
286	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
287	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
288	MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
289	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
290	MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
291	MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
292	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
293	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
294	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
295	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
296	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
297	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
298	MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
299	MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
300	MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
301	MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
302	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
303	MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
304	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
305	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
306	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
307	MLX5_CMD_OP_CREATE_UCTX = 0xa04,
308	MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
309	MLX5_CMD_OP_CREATE_UMEM = 0xa08,
310	MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
311	MLX5_CMD_OP_SYNC_STEERING = 0xb00,
312	MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
313	MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
314	MLX5_CMD_OP_SYNC_CRYPTO = 0xb12,
315	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,
316	MLX5_CMD_OP_MAX
317	};
318
319	/* Valid range for general commands that don't work over an object */
320	enum {
321	MLX5_CMD_OP_GENERAL_START = 0xb00,
322	MLX5_CMD_OP_GENERAL_END = 0xd00,
323	};
324
325	enum {
326	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
327	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
328	};
329
330	enum {
331	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
332	};
333
334	struct mlx5_ifc_flow_table_fields_supported_bits {
335	u8 outer_dmac[0x1];
336	u8 outer_smac[0x1];
337	u8 outer_ether_type[0x1];
338	u8 outer_ip_version[0x1];
339	u8 outer_first_prio[0x1];
340	u8 outer_first_cfi[0x1];
341	u8 outer_first_vid[0x1];
342	u8 outer_ipv4_ttl[0x1];
343	u8 outer_second_prio[0x1];
344	u8 outer_second_cfi[0x1];
345	u8 outer_second_vid[0x1];
346	u8 reserved_at_b[0x1];
347	u8 outer_sip[0x1];
348	u8 outer_dip[0x1];
349	u8 outer_frag[0x1];
350	u8 outer_ip_protocol[0x1];
351	u8 outer_ip_ecn[0x1];
352	u8 outer_ip_dscp[0x1];
353	u8 outer_udp_sport[0x1];
354	u8 outer_udp_dport[0x1];
355	u8 outer_tcp_sport[0x1];
356	u8 outer_tcp_dport[0x1];
357	u8 outer_tcp_flags[0x1];
358	u8 outer_gre_protocol[0x1];
359	u8 outer_gre_key[0x1];
360	u8 outer_vxlan_vni[0x1];
361	u8 outer_geneve_vni[0x1];
362	u8 outer_geneve_oam[0x1];
363	u8 outer_geneve_protocol_type[0x1];
364	u8 outer_geneve_opt_len[0x1];
365	u8 source_vhca_port[0x1];
366	u8 source_eswitch_port[0x1];
367
368	u8 inner_dmac[0x1];
369	u8 inner_smac[0x1];
370	u8 inner_ether_type[0x1];
371	u8 inner_ip_version[0x1];
372	u8 inner_first_prio[0x1];
373	u8 inner_first_cfi[0x1];
374	u8 inner_first_vid[0x1];
375	u8 reserved_at_27[0x1];
376	u8 inner_second_prio[0x1];
377	u8 inner_second_cfi[0x1];
378	u8 inner_second_vid[0x1];
379	u8 reserved_at_2b[0x1];
380	u8 inner_sip[0x1];
381	u8 inner_dip[0x1];
382	u8 inner_frag[0x1];
383	u8 inner_ip_protocol[0x1];
384	u8 inner_ip_ecn[0x1];
385	u8 inner_ip_dscp[0x1];
386	u8 inner_udp_sport[0x1];
387	u8 inner_udp_dport[0x1];
388	u8 inner_tcp_sport[0x1];
389	u8 inner_tcp_dport[0x1];
390	u8 inner_tcp_flags[0x1];
391	u8 reserved_at_37[0x9];
392
393	u8 geneve_tlv_option_0_data[0x1];
394	u8 geneve_tlv_option_0_exist[0x1];
395	u8 reserved_at_42[0x3];
396	u8 outer_first_mpls_over_udp[0x4];
397	u8 outer_first_mpls_over_gre[0x4];
398	u8 inner_first_mpls[0x4];
399	u8 outer_first_mpls[0x4];
400	u8 reserved_at_55[0x2];
401	u8 outer_esp_spi[0x1];
402	u8 reserved_at_58[0x2];
403	u8 bth_dst_qp[0x1];
404	u8 reserved_at_5b[0x5];
405
406	u8 reserved_at_60[0x18];
407	u8 metadata_reg_c_7[0x1];
408	u8 metadata_reg_c_6[0x1];
409	u8 metadata_reg_c_5[0x1];
410	u8 metadata_reg_c_4[0x1];
411	u8 metadata_reg_c_3[0x1];
412	u8 metadata_reg_c_2[0x1];
413	u8 metadata_reg_c_1[0x1];
414	u8 metadata_reg_c_0[0x1];
415	};
416
417	/* Table 2170 - Flow Table Fields Supported 2 Format */
418	struct mlx5_ifc_flow_table_fields_supported_2_bits {
419	u8 reserved_at_0[0xe];
420	u8 bth_opcode[0x1];
421	u8 reserved_at_f[0x1];
422	u8 tunnel_header_0_1[0x1];
423	u8 reserved_at_11[0xf];
424
425	u8 reserved_at_20[0x60];
426	};
427
428	struct mlx5_ifc_flow_table_prop_layout_bits {
429	u8 ft_support[0x1];
430	u8 reserved_at_1[0x1];
431	u8 flow_counter[0x1];
432	u8 flow_modify_en[0x1];
433	u8 modify_root[0x1];
434	u8 identified_miss_table_mode[0x1];
435	u8 flow_table_modify[0x1];
436	u8 reformat[0x1];
437	u8 decap[0x1];
438	u8 reset_root_to_default[0x1];
439	u8 pop_vlan[0x1];
440	u8 push_vlan[0x1];
441	u8 reserved_at_c[0x1];
442	u8 pop_vlan_2[0x1];
443	u8 push_vlan_2[0x1];
444	u8 reformat_and_vlan_action[0x1];
445	u8 reserved_at_10[0x1];
446	u8 sw_owner[0x1];
447	u8 reformat_l3_tunnel_to_l2[0x1];
448	u8 reformat_l2_to_l3_tunnel[0x1];
449	u8 reformat_and_modify_action[0x1];
450	u8 ignore_flow_level[0x1];
451	u8 reserved_at_16[0x1];
452	u8 table_miss_action_domain[0x1];
453	u8 termination_table[0x1];
454	u8 reformat_and_fwd_to_table[0x1];
455	u8 reserved_at_1a[0x2];
456	u8 ipsec_encrypt[0x1];
457	u8 ipsec_decrypt[0x1];
458	u8 sw_owner_v2[0x1];
459	u8 reserved_at_1f[0x1];
460
461	u8 termination_table_raw_traffic[0x1];
462	u8 reserved_at_21[0x1];
463	u8 log_max_ft_size[0x6];
464	u8 log_max_modify_header_context[0x8];
465	u8 max_modify_header_actions[0x8];
466	u8 max_ft_level[0x8];
467
468	u8 reformat_add_esp_trasport[0x1];
469	u8 reformat_l2_to_l3_esp_tunnel[0x1];
470	u8 reformat_add_esp_transport_over_udp[0x1];
471	u8 reformat_del_esp_trasport[0x1];
472	u8 reformat_l3_esp_tunnel_to_l2[0x1];
473	u8 reformat_del_esp_transport_over_udp[0x1];
474	u8 execute_aso[0x1];
475	u8 reserved_at_47[0x19];
476
477	u8 reserved_at_60[0x2];
478	u8 reformat_insert[0x1];
479	u8 reformat_remove[0x1];
480	u8 macsec_encrypt[0x1];
481	u8 macsec_decrypt[0x1];
482	u8 reserved_at_66[0x2];
483	u8 reformat_add_macsec[0x1];
484	u8 reformat_remove_macsec[0x1];
485	u8 reserved_at_6a[0xe];
486	u8 log_max_ft_num[0x8];
487
488	u8 reserved_at_80[0x10];
489	u8 log_max_flow_counter[0x8];
490	u8 log_max_destination[0x8];
491
492	u8 reserved_at_a0[0x18];
493	u8 log_max_flow[0x8];
494
495	u8 reserved_at_c0[0x40];
496
497	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
498
499	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
500	};
501
502	struct mlx5_ifc_odp_per_transport_service_cap_bits {
503	u8 send[0x1];
504	u8 receive[0x1];
505	u8 write[0x1];
506	u8 read[0x1];
507	u8 atomic[0x1];
508	u8 srq_receive[0x1];
509	u8 reserved_at_6[0x1a];
510	};
511
512	struct mlx5_ifc_ipv4_layout_bits {
513	u8 reserved_at_0[0x60];
514
515	u8 ipv4[0x20];
516	};
517
518	struct mlx5_ifc_ipv6_layout_bits {
519	u8 ipv6[16][0x8];
520	};
521
522	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
523	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
524	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
525	u8 reserved_at_0[0x80];
526	};
527
528	struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
529	u8 smac_47_16[0x20];
530
531	u8 smac_15_0[0x10];
532	u8 ethertype[0x10];
533
534	u8 dmac_47_16[0x20];
535
536	u8 dmac_15_0[0x10];
537	u8 first_prio[0x3];
538	u8 first_cfi[0x1];
539	u8 first_vid[0xc];
540
541	u8 ip_protocol[0x8];
542	u8 ip_dscp[0x6];
543	u8 ip_ecn[0x2];
544	u8 cvlan_tag[0x1];
545	u8 svlan_tag[0x1];
546	u8 frag[0x1];
547	u8 ip_version[0x4];
548	u8 tcp_flags[0x9];
549
550	u8 tcp_sport[0x10];
551	u8 tcp_dport[0x10];
552
553	u8 reserved_at_c0[0x10];
554	u8 ipv4_ihl[0x4];
555	u8 reserved_at_c4[0x4];
556
557	u8 ttl_hoplimit[0x8];
558
559	u8 udp_sport[0x10];
560	u8 udp_dport[0x10];
561
562	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
563
564	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
565	};
566
567	struct mlx5_ifc_nvgre_key_bits {
568	u8 hi[0x18];
569	u8 lo[0x8];
570	};
571
572	union mlx5_ifc_gre_key_bits {
573	struct mlx5_ifc_nvgre_key_bits nvgre;
574	u8 key[0x20];
575	};
576
577	struct mlx5_ifc_fte_match_set_misc_bits {
578	u8 gre_c_present[0x1];
579	u8 reserved_at_1[0x1];
580	u8 gre_k_present[0x1];
581	u8 gre_s_present[0x1];
582	u8 source_vhca_port[0x4];
583	u8 source_sqn[0x18];
584
585	u8 source_eswitch_owner_vhca_id[0x10];
586	u8 source_port[0x10];
587
588	u8 outer_second_prio[0x3];
589	u8 outer_second_cfi[0x1];
590	u8 outer_second_vid[0xc];
591	u8 inner_second_prio[0x3];
592	u8 inner_second_cfi[0x1];
593	u8 inner_second_vid[0xc];
594
595	u8 outer_second_cvlan_tag[0x1];
596	u8 inner_second_cvlan_tag[0x1];
597	u8 outer_second_svlan_tag[0x1];
598	u8 inner_second_svlan_tag[0x1];
599	u8 reserved_at_64[0xc];
600	u8 gre_protocol[0x10];
601
602	union mlx5_ifc_gre_key_bits gre_key;
603
604	u8 vxlan_vni[0x18];
605	u8 bth_opcode[0x8];
606
607	u8 geneve_vni[0x18];
608	u8 reserved_at_d8[0x6];
609	u8 geneve_tlv_option_0_exist[0x1];
610	u8 geneve_oam[0x1];
611
612	u8 reserved_at_e0[0xc];
613	u8 outer_ipv6_flow_label[0x14];
614
615	u8 reserved_at_100[0xc];
616	u8 inner_ipv6_flow_label[0x14];
617
618	u8 reserved_at_120[0xa];
619	u8 geneve_opt_len[0x6];
620	u8 geneve_protocol_type[0x10];
621
622	u8 reserved_at_140[0x8];
623	u8 bth_dst_qp[0x18];
624	u8 inner_esp_spi[0x20];
625	u8 outer_esp_spi[0x20];
626	u8 reserved_at_1a0[0x60];
627	};
628
629	struct mlx5_ifc_fte_match_mpls_bits {
630	u8 mpls_label[0x14];
631	u8 mpls_exp[0x3];
632	u8 mpls_s_bos[0x1];
633	u8 mpls_ttl[0x8];
634	};
635
636	struct mlx5_ifc_fte_match_set_misc2_bits {
637	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
638
639	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
640
641	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
642
643	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
644
645	u8 metadata_reg_c_7[0x20];
646
647	u8 metadata_reg_c_6[0x20];
648
649	u8 metadata_reg_c_5[0x20];
650
651	u8 metadata_reg_c_4[0x20];
652
653	u8 metadata_reg_c_3[0x20];
654
655	u8 metadata_reg_c_2[0x20];
656
657	u8 metadata_reg_c_1[0x20];
658
659	u8 metadata_reg_c_0[0x20];
660
661	u8 metadata_reg_a[0x20];
662
663	u8 reserved_at_1a0[0x8];
664
665	u8 macsec_syndrome[0x8];
666	u8 ipsec_syndrome[0x8];
667	u8 reserved_at_1b8[0x8];
668
669	u8 reserved_at_1c0[0x40];
670	};
671
672	struct mlx5_ifc_fte_match_set_misc3_bits {
673	u8 inner_tcp_seq_num[0x20];
674
675	u8 outer_tcp_seq_num[0x20];
676
677	u8 inner_tcp_ack_num[0x20];
678
679	u8 outer_tcp_ack_num[0x20];
680
681	u8 reserved_at_80[0x8];
682	u8 outer_vxlan_gpe_vni[0x18];
683
684	u8 outer_vxlan_gpe_next_protocol[0x8];
685	u8 outer_vxlan_gpe_flags[0x8];
686	u8 reserved_at_b0[0x10];
687
688	u8 icmp_header_data[0x20];
689
690	u8 icmpv6_header_data[0x20];
691
692	u8 icmp_type[0x8];
693	u8 icmp_code[0x8];
694	u8 icmpv6_type[0x8];
695	u8 icmpv6_code[0x8];
696
697	u8 geneve_tlv_option_0_data[0x20];
698
699	u8 gtpu_teid[0x20];
700
701	u8 gtpu_msg_type[0x8];
702	u8 gtpu_msg_flags[0x8];
703	u8 reserved_at_170[0x10];
704
705	u8 gtpu_dw_2[0x20];
706
707	u8 gtpu_first_ext_dw_0[0x20];
708
709	u8 gtpu_dw_0[0x20];
710
711	u8 reserved_at_1e0[0x20];
712	};
713
714	struct mlx5_ifc_fte_match_set_misc4_bits {
715	u8 prog_sample_field_value_0[0x20];
716
717	u8 prog_sample_field_id_0[0x20];
718
719	u8 prog_sample_field_value_1[0x20];
720
721	u8 prog_sample_field_id_1[0x20];
722
723	u8 prog_sample_field_value_2[0x20];
724
725	u8 prog_sample_field_id_2[0x20];
726
727	u8 prog_sample_field_value_3[0x20];
728
729	u8 prog_sample_field_id_3[0x20];
730
731	u8 reserved_at_100[0x100];
732	};
733
734	struct mlx5_ifc_fte_match_set_misc5_bits {
735	u8 macsec_tag_0[0x20];
736
737	u8 macsec_tag_1[0x20];
738
739	u8 macsec_tag_2[0x20];
740
741	u8 macsec_tag_3[0x20];
742
743	u8 tunnel_header_0[0x20];
744
745	u8 tunnel_header_1[0x20];
746
747	u8 tunnel_header_2[0x20];
748
749	u8 tunnel_header_3[0x20];
750
751	u8 reserved_at_100[0x100];
752	};
753
754	struct mlx5_ifc_cmd_pas_bits {
755	u8 pa_h[0x20];
756
757	u8 pa_l[0x14];
758	u8 reserved_at_34[0xc];
759	};
760
761	struct mlx5_ifc_uint64_bits {
762	u8 hi[0x20];
763
764	u8 lo[0x20];
765	};
766
767	enum {
768	MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
769	MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
770	MLX5_ADS_STAT_RATE_10GBPS = 0x8,
771	MLX5_ADS_STAT_RATE_30GBPS = 0x9,
772	MLX5_ADS_STAT_RATE_5GBPS = 0xa,
773	MLX5_ADS_STAT_RATE_20GBPS = 0xb,
774	MLX5_ADS_STAT_RATE_40GBPS = 0xc,
775	MLX5_ADS_STAT_RATE_60GBPS = 0xd,
776	MLX5_ADS_STAT_RATE_80GBPS = 0xe,
777	MLX5_ADS_STAT_RATE_120GBPS = 0xf,
778	};
779
780	struct mlx5_ifc_ads_bits {
781	u8 fl[0x1];
782	u8 free_ar[0x1];
783	u8 reserved_at_2[0xe];
784	u8 pkey_index[0x10];
785
786	u8 reserved_at_20[0x8];
787	u8 grh[0x1];
788	u8 mlid[0x7];
789	u8 rlid[0x10];
790
791	u8 ack_timeout[0x5];
792	u8 reserved_at_45[0x3];
793	u8 src_addr_index[0x8];
794	u8 reserved_at_50[0x4];
795	u8 stat_rate[0x4];
796	u8 hop_limit[0x8];
797
798	u8 reserved_at_60[0x4];
799	u8 tclass[0x8];
800	u8 flow_label[0x14];
801
802	u8 rgid_rip[16][0x8];
803
804	u8 reserved_at_100[0x4];
805	u8 f_dscp[0x1];
806	u8 f_ecn[0x1];
807	u8 reserved_at_106[0x1];
808	u8 f_eth_prio[0x1];
809	u8 ecn[0x2];
810	u8 dscp[0x6];
811	u8 udp_sport[0x10];
812
813	u8 dei_cfi[0x1];
814	u8 eth_prio[0x3];
815	u8 sl[0x4];
816	u8 vhca_port_num[0x8];
817	u8 rmac_47_32[0x10];
818
819	u8 rmac_31_0[0x20];
820	};
821
822	struct mlx5_ifc_flow_table_nic_cap_bits {
823	u8 nic_rx_multi_path_tirs[0x1];
824	u8 nic_rx_multi_path_tirs_fts[0x1];
825	u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
826	u8 reserved_at_3[0x4];
827	u8 sw_owner_reformat_supported[0x1];
828	u8 reserved_at_8[0x18];
829
830	u8 encap_general_header[0x1];
831	u8 reserved_at_21[0xa];
832	u8 log_max_packet_reformat_context[0x5];
833	u8 reserved_at_30[0x6];
834	u8 max_encap_header_size[0xa];
835	u8 reserved_at_40[0x1c0];
836
837	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
838
839	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
840
841	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
842
843	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
844
845	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
846
847	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
848
849	u8 reserved_at_e00[0x700];
850
851	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
852
853	u8 reserved_at_1580[0x280];
854
855	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
856
857	u8 reserved_at_1880[0x780];
858
859	u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
860
861	u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
862
863	u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
864
865	u8 reserved_at_20c0[0x5f40];
866	};
867
868	struct mlx5_ifc_port_selection_cap_bits {
869	u8 reserved_at_0[0x10];
870	u8 port_select_flow_table[0x1];
871	u8 reserved_at_11[0x1];
872	u8 port_select_flow_table_bypass[0x1];
873	u8 reserved_at_13[0xd];
874
875	u8 reserved_at_20[0x1e0];
876
877	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
878
879	u8 reserved_at_400[0x7c00];
880	};
881
882	enum {
883	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
884	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
885	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
886	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
887	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
888	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
889	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
890	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
891	};
892
893	struct mlx5_ifc_flow_table_eswitch_cap_bits {
894	u8 fdb_to_vport_reg_c_id[0x8];
895	u8 reserved_at_8[0x5];
896	u8 fdb_uplink_hairpin[0x1];
897	u8 fdb_multi_path_any_table_limit_regc[0x1];
898	u8 reserved_at_f[0x3];
899	u8 fdb_multi_path_any_table[0x1];
900	u8 reserved_at_13[0x2];
901	u8 fdb_modify_header_fwd_to_table[0x1];
902	u8 fdb_ipv4_ttl_modify[0x1];
903	u8 flow_source[0x1];
904	u8 reserved_at_18[0x2];
905	u8 multi_fdb_encap[0x1];
906	u8 egress_acl_forward_to_vport[0x1];
907	u8 fdb_multi_path_to_table[0x1];
908	u8 reserved_at_1d[0x3];
909
910	u8 reserved_at_20[0x1e0];
911
912	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
913
914	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
915
916	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
917
918	u8 reserved_at_800[0xC00];
919
920	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
921
922	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
923
924	u8 reserved_at_1500[0x300];
925
926	u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
927
928	u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
929
930	u8 sw_steering_uplink_icm_address_rx[0x40];
931
932	u8 sw_steering_uplink_icm_address_tx[0x40];
933
934	u8 reserved_at_1900[0x6700];
935	};
936
937	enum {
938	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
939	MLX5_COUNTER_FLOW_ESWITCH = 0x1,
940	};
941
942	struct mlx5_ifc_e_switch_cap_bits {
943	u8 vport_svlan_strip[0x1];
944	u8 vport_cvlan_strip[0x1];
945	u8 vport_svlan_insert[0x1];
946	u8 vport_cvlan_insert_if_not_exist[0x1];
947	u8 vport_cvlan_insert_overwrite[0x1];
948	u8 reserved_at_5[0x1];
949	u8 vport_cvlan_insert_always[0x1];
950	u8 esw_shared_ingress_acl[0x1];
951	u8 esw_uplink_ingress_acl[0x1];
952	u8 root_ft_on_other_esw[0x1];
953	u8 reserved_at_a[0xf];
954	u8 esw_functions_changed[0x1];
955	u8 reserved_at_1a[0x1];
956	u8 ecpf_vport_exists[0x1];
957	u8 counter_eswitch_affinity[0x1];
958	u8 merged_eswitch[0x1];
959	u8 nic_vport_node_guid_modify[0x1];
960	u8 nic_vport_port_guid_modify[0x1];
961
962	u8 vxlan_encap_decap[0x1];
963	u8 nvgre_encap_decap[0x1];
964	u8 reserved_at_22[0x1];
965	u8 log_max_fdb_encap_uplink[0x5];
966	u8 reserved_at_21[0x3];
967	u8 log_max_packet_reformat_context[0x5];
968	u8 reserved_2b[0x6];
969	u8 max_encap_header_size[0xa];
970
971	u8 reserved_at_40[0xb];
972	u8 log_max_esw_sf[0x5];
973	u8 esw_sf_base_id[0x10];
974
975	u8 reserved_at_60[0x7a0];
976
977	};
978
979	struct mlx5_ifc_qos_cap_bits {
980	u8 packet_pacing[0x1];
981	u8 esw_scheduling[0x1];
982	u8 esw_bw_share[0x1];
983	u8 esw_rate_limit[0x1];
984	u8 reserved_at_4[0x1];
985	u8 packet_pacing_burst_bound[0x1];
986	u8 packet_pacing_typical_size[0x1];
987	u8 reserved_at_7[0x1];
988	u8 nic_sq_scheduling[0x1];
989	u8 nic_bw_share[0x1];
990	u8 nic_rate_limit[0x1];
991	u8 packet_pacing_uid[0x1];
992	u8 log_esw_max_sched_depth[0x4];
993	u8 reserved_at_10[0x10];
994
995	u8 reserved_at_20[0xb];
996	u8 log_max_qos_nic_queue_group[0x5];
997	u8 reserved_at_30[0x10];
998
999	u8 packet_pacing_max_rate[0x20];
1000
1001	u8 packet_pacing_min_rate[0x20];
1002
1003	u8 reserved_at_80[0x10];
1004	u8 packet_pacing_rate_table_size[0x10];
1005
1006	u8 esw_element_type[0x10];
1007	u8 esw_tsar_type[0x10];
1008
1009	u8 reserved_at_c0[0x10];
1010	u8 max_qos_para_vport[0x10];
1011
1012	u8 max_tsar_bw_share[0x20];
1013
1014	u8 reserved_at_100[0x20];
1015
1016	u8 reserved_at_120[0x3];
1017	u8 log_meter_aso_granularity[0x5];
1018	u8 reserved_at_128[0x3];
1019	u8 log_meter_aso_max_alloc[0x5];
1020	u8 reserved_at_130[0x3];
1021	u8 log_max_num_meter_aso[0x5];
1022	u8 reserved_at_138[0x8];
1023
1024	u8 reserved_at_140[0x6c0];
1025	};
1026
1027	struct mlx5_ifc_debug_cap_bits {
1028	u8 core_dump_general[0x1];
1029	u8 core_dump_qp[0x1];
1030	u8 reserved_at_2[0x7];
1031	u8 resource_dump[0x1];
1032	u8 reserved_at_a[0x16];
1033
1034	u8 reserved_at_20[0x2];
1035	u8 stall_detect[0x1];
1036	u8 reserved_at_23[0x1d];
1037
1038	u8 reserved_at_40[0x7c0];
1039	};
1040
1041	struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1042	u8 csum_cap[0x1];
1043	u8 vlan_cap[0x1];
1044	u8 lro_cap[0x1];
1045	u8 lro_psh_flag[0x1];
1046	u8 lro_time_stamp[0x1];
1047	u8 reserved_at_5[0x2];
1048	u8 wqe_vlan_insert[0x1];
1049	u8 self_lb_en_modifiable[0x1];
1050	u8 reserved_at_9[0x2];
1051	u8 max_lso_cap[0x5];
1052	u8 multi_pkt_send_wqe[0x2];
1053	u8 wqe_inline_mode[0x2];
1054	u8 rss_ind_tbl_cap[0x4];
1055	u8 reg_umr_sq[0x1];
1056	u8 scatter_fcs[0x1];
1057	u8 enhanced_multi_pkt_send_wqe[0x1];
1058	u8 tunnel_lso_const_out_ip_id[0x1];
1059	u8 tunnel_lro_gre[0x1];
1060	u8 tunnel_lro_vxlan[0x1];
1061	u8 tunnel_stateless_gre[0x1];
1062	u8 tunnel_stateless_vxlan[0x1];
1063
1064	u8 swp[0x1];
1065	u8 swp_csum[0x1];
1066	u8 swp_lso[0x1];
1067	u8 cqe_checksum_full[0x1];
1068	u8 tunnel_stateless_geneve_tx[0x1];
1069	u8 tunnel_stateless_mpls_over_udp[0x1];
1070	u8 tunnel_stateless_mpls_over_gre[0x1];
1071	u8 tunnel_stateless_vxlan_gpe[0x1];
1072	u8 tunnel_stateless_ipv4_over_vxlan[0x1];
1073	u8 tunnel_stateless_ip_over_ip[0x1];
1074	u8 insert_trailer[0x1];
1075	u8 reserved_at_2b[0x1];
1076	u8 tunnel_stateless_ip_over_ip_rx[0x1];
1077	u8 tunnel_stateless_ip_over_ip_tx[0x1];
1078	u8 reserved_at_2e[0x2];
1079	u8 max_vxlan_udp_ports[0x8];
1080	u8 reserved_at_38[0x6];
1081	u8 max_geneve_opt_len[0x1];
1082	u8 tunnel_stateless_geneve_rx[0x1];
1083
1084	u8 reserved_at_40[0x10];
1085	u8 lro_min_mss_size[0x10];
1086
1087	u8 reserved_at_60[0x120];
1088
1089	u8 lro_timer_supported_periods[4][0x20];
1090
1091	u8 reserved_at_200[0x600];
1092	};
1093
1094	enum {
1095	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1096	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1097	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1098	};
1099
1100	struct mlx5_ifc_roce_cap_bits {
1101	u8 roce_apm[0x1];
1102	u8 reserved_at_1[0x3];
1103	u8 sw_r_roce_src_udp_port[0x1];
1104	u8 fl_rc_qp_when_roce_disabled[0x1];
1105	u8 fl_rc_qp_when_roce_enabled[0x1];
1106	u8 roce_cc_general[0x1];
1107	u8 qp_ooo_transmit_default[0x1];
1108	u8 reserved_at_9[0x15];
1109	u8 qp_ts_format[0x2];
1110
1111	u8 reserved_at_20[0x60];
1112
1113	u8 reserved_at_80[0xc];
1114	u8 l3_type[0x4];
1115	u8 reserved_at_90[0x8];
1116	u8 roce_version[0x8];
1117
1118	u8 reserved_at_a0[0x10];
1119	u8 r_roce_dest_udp_port[0x10];
1120
1121	u8 r_roce_max_src_udp_port[0x10];
1122	u8 r_roce_min_src_udp_port[0x10];
1123
1124	u8 reserved_at_e0[0x10];
1125	u8 roce_address_table_size[0x10];
1126
1127	u8 reserved_at_100[0x700];
1128	};
1129
1130	struct mlx5_ifc_sync_steering_in_bits {
1131	u8 opcode[0x10];
1132	u8 uid[0x10];
1133
1134	u8 reserved_at_20[0x10];
1135	u8 op_mod[0x10];
1136
1137	u8 reserved_at_40[0xc0];
1138	};
1139
1140	struct mlx5_ifc_sync_steering_out_bits {
1141	u8 status[0x8];
1142	u8 reserved_at_8[0x18];
1143
1144	u8 syndrome[0x20];
1145
1146	u8 reserved_at_40[0x40];
1147	};
1148
1149	struct mlx5_ifc_sync_crypto_in_bits {
1150	u8 opcode[0x10];
1151	u8 uid[0x10];
1152
1153	u8 reserved_at_20[0x10];
1154	u8 op_mod[0x10];
1155
1156	u8 reserved_at_40[0x20];
1157
1158	u8 reserved_at_60[0x10];
1159	u8 crypto_type[0x10];
1160
1161	u8 reserved_at_80[0x80];
1162	};
1163
1164	struct mlx5_ifc_sync_crypto_out_bits {
1165	u8 status[0x8];
1166	u8 reserved_at_8[0x18];
1167
1168	u8 syndrome[0x20];
1169
1170	u8 reserved_at_40[0x40];
1171	};
1172
1173	struct mlx5_ifc_device_mem_cap_bits {
1174	u8 memic[0x1];
1175	u8 reserved_at_1[0x1f];
1176
1177	u8 reserved_at_20[0xb];
1178	u8 log_min_memic_alloc_size[0x5];
1179	u8 reserved_at_30[0x8];
1180	u8 log_max_memic_addr_alignment[0x8];
1181
1182	u8 memic_bar_start_addr[0x40];
1183
1184	u8 memic_bar_size[0x20];
1185
1186	u8 max_memic_size[0x20];
1187
1188	u8 steering_sw_icm_start_address[0x40];
1189
1190	u8 reserved_at_100[0x8];
1191	u8 log_header_modify_sw_icm_size[0x8];
1192	u8 reserved_at_110[0x2];
1193	u8 log_sw_icm_alloc_granularity[0x6];
1194	u8 log_steering_sw_icm_size[0x8];
1195
1196	u8 log_indirect_encap_sw_icm_size[0x8];
1197	u8 reserved_at_128[0x10];
1198	u8 log_header_modify_pattern_sw_icm_size[0x8];
1199
1200	u8 header_modify_sw_icm_start_address[0x40];
1201
1202	u8 reserved_at_180[0x40];
1203
1204	u8 header_modify_pattern_sw_icm_start_address[0x40];
1205
1206	u8 memic_operations[0x20];
1207
1208	u8 reserved_at_220[0x20];
1209
1210	u8 indirect_encap_sw_icm_start_address[0x40];
1211
1212	u8 reserved_at_280[0x580];
1213	};
1214
1215	struct mlx5_ifc_device_event_cap_bits {
1216	u8 user_affiliated_events[4][0x40];
1217
1218	u8 user_unaffiliated_events[4][0x40];
1219	};
1220
1221	struct mlx5_ifc_virtio_emulation_cap_bits {
1222	u8 desc_tunnel_offload_type[0x1];
1223	u8 eth_frame_offload_type[0x1];
1224	u8 virtio_version_1_0[0x1];
1225	u8 device_features_bits_mask[0xd];
1226	u8 event_mode[0x8];
1227	u8 virtio_queue_type[0x8];
1228
1229	u8 max_tunnel_desc[0x10];
1230	u8 reserved_at_30[0x3];
1231	u8 log_doorbell_stride[0x5];
1232	u8 reserved_at_38[0x3];
1233	u8 log_doorbell_bar_size[0x5];
1234
1235	u8 doorbell_bar_offset[0x40];
1236
1237	u8 max_emulated_devices[0x8];
1238	u8 max_num_virtio_queues[0x18];
1239
1240	u8 reserved_at_a0[0x20];
1241
1242	u8 reserved_at_c0[0x13];
1243	u8 desc_group_mkey_supported[0x1];
1244	u8 freeze_to_rdy_supported[0x1];
1245	u8 reserved_at_d5[0xb];
1246
1247	u8 reserved_at_e0[0x20];
1248
1249	u8 umem_1_buffer_param_a[0x20];
1250
1251	u8 umem_1_buffer_param_b[0x20];
1252
1253	u8 umem_2_buffer_param_a[0x20];
1254
1255	u8 umem_2_buffer_param_b[0x20];
1256
1257	u8 umem_3_buffer_param_a[0x20];
1258
1259	u8 umem_3_buffer_param_b[0x20];
1260
1261	u8 reserved_at_1c0[0x640];
1262	};
1263
1264	enum {
1265	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1266	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1267	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1268	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1269	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1270	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1271	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1272	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1273	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1274	};
1275
1276	enum {
1277	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1278	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1279	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1280	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1281	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1282	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1283	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1284	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1285	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1286	};
1287
1288	struct mlx5_ifc_atomic_caps_bits {
1289	u8 reserved_at_0[0x40];
1290
1291	u8 atomic_req_8B_endianness_mode[0x2];
1292	u8 reserved_at_42[0x4];
1293	u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1294
1295	u8 reserved_at_47[0x19];
1296
1297	u8 reserved_at_60[0x20];
1298
1299	u8 reserved_at_80[0x10];
1300	u8 atomic_operations[0x10];
1301
1302	u8 reserved_at_a0[0x10];
1303	u8 atomic_size_qp[0x10];
1304
1305	u8 reserved_at_c0[0x10];
1306	u8 atomic_size_dc[0x10];
1307
1308	u8 reserved_at_e0[0x720];
1309	};
1310
1311	struct mlx5_ifc_odp_cap_bits {
1312	u8 reserved_at_0[0x40];
1313
1314	u8 sig[0x1];
1315	u8 reserved_at_41[0x1f];
1316
1317	u8 reserved_at_60[0x20];
1318
1319	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1320
1321	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1322
1323	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1324
1325	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1326
1327	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1328
1329	u8 reserved_at_120[0x6E0];
1330	};
1331
1332	struct mlx5_ifc_tls_cap_bits {
1333	u8 tls_1_2_aes_gcm_128[0x1];
1334	u8 tls_1_3_aes_gcm_128[0x1];
1335	u8 tls_1_2_aes_gcm_256[0x1];
1336	u8 tls_1_3_aes_gcm_256[0x1];
1337	u8 reserved_at_4[0x1c];
1338
1339	u8 reserved_at_20[0x7e0];
1340	};
1341
1342	struct mlx5_ifc_ipsec_cap_bits {
1343	u8 ipsec_full_offload[0x1];
1344	u8 ipsec_crypto_offload[0x1];
1345	u8 ipsec_esn[0x1];
1346	u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1347	u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1348	u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1349	u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1350	u8 reserved_at_7[0x4];
1351	u8 log_max_ipsec_offload[0x5];
1352	u8 reserved_at_10[0x10];
1353
1354	u8 min_log_ipsec_full_replay_window[0x8];
1355	u8 max_log_ipsec_full_replay_window[0x8];
1356	u8 reserved_at_30[0x7d0];
1357	};
1358
1359	struct mlx5_ifc_macsec_cap_bits {
1360	u8 macsec_epn[0x1];
1361	u8 reserved_at_1[0x2];
1362	u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1363	u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1364	u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1365	u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1366	u8 reserved_at_7[0x4];
1367	u8 log_max_macsec_offload[0x5];
1368	u8 reserved_at_10[0x10];
1369
1370	u8 min_log_macsec_full_replay_window[0x8];
1371	u8 max_log_macsec_full_replay_window[0x8];
1372	u8 reserved_at_30[0x10];
1373
1374	u8 reserved_at_40[0x7c0];
1375	};
1376
1377	enum {
1378	MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1379	MLX5_WQ_TYPE_CYCLIC = 0x1,
1380	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1381	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1382	};
1383
1384	enum {
1385	MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1386	MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1387	};
1388
1389	enum {
1390	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1391	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1392	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1393	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1394	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1395	};
1396
1397	enum {
1398	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1399	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1400	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1401	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1402	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1403	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1404	};
1405
1406	enum {
1407	MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1408	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1409	};
1410
1411	enum {
1412	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1413	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1414	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1415	};
1416
1417	enum {
1418	MLX5_CAP_PORT_TYPE_IB = 0x0,
1419	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1420	};
1421
1422	enum {
1423	MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1424	MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1425	MLX5_CAP_UMR_FENCE_NONE = 0x2,
1426	};
1427
1428	enum {
1429	MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1430	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
1431	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
1432	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1433	MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1434	MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1435	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1436	MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1437	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1438	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1439	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1440	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
1441	};
1442
1443	enum {
1444	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1445	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1446	};
1447
1448	#define MLX5_FC_BULK_SIZE_FACTOR 128
1449
1450	enum mlx5_fc_bulk_alloc_bitmask {
1451	MLX5_FC_BULK_128 = (1 << 0),
1452	MLX5_FC_BULK_256 = (1 << 1),
1453	MLX5_FC_BULK_512 = (1 << 2),
1454	MLX5_FC_BULK_1024 = (1 << 3),
1455	MLX5_FC_BULK_2048 = (1 << 4),
1456	MLX5_FC_BULK_4096 = (1 << 5),
1457	MLX5_FC_BULK_8192 = (1 << 6),
1458	MLX5_FC_BULK_16384 = (1 << 7),
1459	};
1460
1461	#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1462
1463	#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1464
1465	enum {
1466	MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1467	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1468	MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
1469	};
1470
1471	struct mlx5_ifc_cmd_hca_cap_bits {
1472	u8 reserved_at_0[0x10];
1473	u8 shared_object_to_user_object_allowed[0x1];
1474	u8 reserved_at_13[0xe];
1475	u8 vhca_resource_manager[0x1];
1476
1477	u8 hca_cap_2[0x1];
1478	u8 create_lag_when_not_master_up[0x1];
1479	u8 dtor[0x1];
1480	u8 event_on_vhca_state_teardown_request[0x1];
1481	u8 event_on_vhca_state_in_use[0x1];
1482	u8 event_on_vhca_state_active[0x1];
1483	u8 event_on_vhca_state_allocated[0x1];
1484	u8 event_on_vhca_state_invalid[0x1];
1485	u8 reserved_at_28[0x8];
1486	u8 vhca_id[0x10];
1487
1488	u8 reserved_at_40[0x40];
1489
1490	u8 log_max_srq_sz[0x8];
1491	u8 log_max_qp_sz[0x8];
1492	u8 event_cap[0x1];
1493	u8 reserved_at_91[0x2];
1494	u8 isolate_vl_tc_new[0x1];
1495	u8 reserved_at_94[0x4];
1496	u8 prio_tag_required[0x1];
1497	u8 reserved_at_99[0x2];
1498	u8 log_max_qp[0x5];
1499
1500	u8 reserved_at_a0[0x3];
1501	u8 ece_support[0x1];
1502	u8 reserved_at_a4[0x5];
1503	u8 reg_c_preserve[0x1];
1504	u8 reserved_at_aa[0x1];
1505	u8 log_max_srq[0x5];
1506	u8 reserved_at_b0[0x1];
1507	u8 uplink_follow[0x1];
1508	u8 ts_cqe_to_dest_cqn[0x1];
1509	u8 reserved_at_b3[0x6];
1510	u8 go_back_n[0x1];
1511	u8 shampo[0x1];
1512	u8 reserved_at_bb[0x5];
1513
1514	u8 max_sgl_for_optimized_performance[0x8];
1515	u8 log_max_cq_sz[0x8];
1516	u8 relaxed_ordering_write_umr[0x1];
1517	u8 relaxed_ordering_read_umr[0x1];
1518	u8 reserved_at_d2[0x7];
1519	u8 virtio_net_device_emualtion_manager[0x1];
1520	u8 virtio_blk_device_emualtion_manager[0x1];
1521	u8 log_max_cq[0x5];
1522
1523	u8 log_max_eq_sz[0x8];
1524	u8 relaxed_ordering_write[0x1];
1525	u8 relaxed_ordering_read_pci_enabled[0x1];
1526	u8 log_max_mkey[0x6];
1527	u8 reserved_at_f0[0x6];
1528	u8 terminate_scatter_list_mkey[0x1];
1529	u8 repeated_mkey[0x1];
1530	u8 dump_fill_mkey[0x1];
1531	u8 reserved_at_f9[0x2];
1532	u8 fast_teardown[0x1];
1533	u8 log_max_eq[0x4];
1534
1535	u8 max_indirection[0x8];
1536	u8 fixed_buffer_size[0x1];
1537	u8 log_max_mrw_sz[0x7];
1538	u8 force_teardown[0x1];
1539	u8 reserved_at_111[0x1];
1540	u8 log_max_bsf_list_size[0x6];
1541	u8 umr_extended_translation_offset[0x1];
1542	u8 null_mkey[0x1];
1543	u8 log_max_klm_list_size[0x6];
1544
1545	u8 reserved_at_120[0x2];
1546	u8 qpc_extension[0x1];
1547	u8 reserved_at_123[0x7];
1548	u8 log_max_ra_req_dc[0x6];
1549	u8 reserved_at_130[0x2];
1550	u8 eth_wqe_too_small[0x1];
1551	u8 reserved_at_133[0x6];
1552	u8 vnic_env_cq_overrun[0x1];
1553	u8 log_max_ra_res_dc[0x6];
1554
1555	u8 reserved_at_140[0x5];
1556	u8 release_all_pages[0x1];
1557	u8 must_not_use[0x1];
1558	u8 reserved_at_147[0x2];
1559	u8 roce_accl[0x1];
1560	u8 log_max_ra_req_qp[0x6];
1561	u8 reserved_at_150[0xa];
1562	u8 log_max_ra_res_qp[0x6];
1563
1564	u8 end_pad[0x1];
1565	u8 cc_query_allowed[0x1];
1566	u8 cc_modify_allowed[0x1];
1567	u8 start_pad[0x1];
1568	u8 cache_line_128byte[0x1];
1569	u8 reserved_at_165[0x4];
1570	u8 rts2rts_qp_counters_set_id[0x1];
1571	u8 reserved_at_16a[0x2];
1572	u8 vnic_env_int_rq_oob[0x1];
1573	u8 sbcam_reg[0x1];
1574	u8 reserved_at_16e[0x1];
1575	u8 qcam_reg[0x1];
1576	u8 gid_table_size[0x10];
1577
1578	u8 out_of_seq_cnt[0x1];
1579	u8 vport_counters[0x1];
1580	u8 retransmission_q_counters[0x1];
1581	u8 debug[0x1];
1582	u8 modify_rq_counter_set_id[0x1];
1583	u8 rq_delay_drop[0x1];
1584	u8 max_qp_cnt[0xa];
1585	u8 pkey_table_size[0x10];
1586
1587	u8 vport_group_manager[0x1];
1588	u8 vhca_group_manager[0x1];
1589	u8 ib_virt[0x1];
1590	u8 eth_virt[0x1];
1591	u8 vnic_env_queue_counters[0x1];
1592	u8 ets[0x1];
1593	u8 nic_flow_table[0x1];
1594	u8 eswitch_manager[0x1];
1595	u8 device_memory[0x1];
1596	u8 mcam_reg[0x1];
1597	u8 pcam_reg[0x1];
1598	u8 local_ca_ack_delay[0x5];
1599	u8 port_module_event[0x1];
1600	u8 enhanced_error_q_counters[0x1];
1601	u8 ports_check[0x1];
1602	u8 reserved_at_1b3[0x1];
1603	u8 disable_link_up[0x1];
1604	u8 beacon_led[0x1];
1605	u8 port_type[0x2];
1606	u8 num_ports[0x8];
1607
1608	u8 reserved_at_1c0[0x1];
1609	u8 pps[0x1];
1610	u8 pps_modify[0x1];
1611	u8 log_max_msg[0x5];
1612	u8 reserved_at_1c8[0x4];
1613	u8 max_tc[0x4];
1614	u8 temp_warn_event[0x1];
1615	u8 dcbx[0x1];
1616	u8 general_notification_event[0x1];
1617	u8 reserved_at_1d3[0x2];
1618	u8 fpga[0x1];
1619	u8 rol_s[0x1];
1620	u8 rol_g[0x1];
1621	u8 reserved_at_1d8[0x1];
1622	u8 wol_s[0x1];
1623	u8 wol_g[0x1];
1624	u8 wol_a[0x1];
1625	u8 wol_b[0x1];
1626	u8 wol_m[0x1];
1627	u8 wol_u[0x1];
1628	u8 wol_p[0x1];
1629
1630	u8 stat_rate_support[0x10];
1631	u8 reserved_at_1f0[0x1];
1632	u8 pci_sync_for_fw_update_event[0x1];
1633	u8 reserved_at_1f2[0x6];
1634	u8 init2_lag_tx_port_affinity[0x1];
1635	u8 reserved_at_1fa[0x3];
1636	u8 cqe_version[0x4];
1637
1638	u8 compact_address_vector[0x1];
1639	u8 striding_rq[0x1];
1640	u8 reserved_at_202[0x1];
1641	u8 ipoib_enhanced_offloads[0x1];
1642	u8 ipoib_basic_offloads[0x1];
1643	u8 reserved_at_205[0x1];
1644	u8 repeated_block_disabled[0x1];
1645	u8 umr_modify_entity_size_disabled[0x1];
1646	u8 umr_modify_atomic_disabled[0x1];
1647	u8 umr_indirect_mkey_disabled[0x1];
1648	u8 umr_fence[0x2];
1649	u8 dc_req_scat_data_cqe[0x1];
1650	u8 reserved_at_20d[0x2];
1651	u8 drain_sigerr[0x1];
1652	u8 cmdif_checksum[0x2];
1653	u8 sigerr_cqe[0x1];
1654	u8 reserved_at_213[0x1];
1655	u8 wq_signature[0x1];
1656	u8 sctr_data_cqe[0x1];
1657	u8 reserved_at_216[0x1];
1658	u8 sho[0x1];
1659	u8 tph[0x1];
1660	u8 rf[0x1];
1661	u8 dct[0x1];
1662	u8 qos[0x1];
1663	u8 eth_net_offloads[0x1];
1664	u8 roce[0x1];
1665	u8 atomic[0x1];
1666	u8 reserved_at_21f[0x1];
1667
1668	u8 cq_oi[0x1];
1669	u8 cq_resize[0x1];
1670	u8 cq_moderation[0x1];
1671	u8 reserved_at_223[0x3];
1672	u8 cq_eq_remap[0x1];
1673	u8 pg[0x1];
1674	u8 block_lb_mc[0x1];
1675	u8 reserved_at_229[0x1];
1676	u8 scqe_break_moderation[0x1];
1677	u8 cq_period_start_from_cqe[0x1];
1678	u8 cd[0x1];
1679	u8 reserved_at_22d[0x1];
1680	u8 apm[0x1];
1681	u8 vector_calc[0x1];
1682	u8 umr_ptr_rlky[0x1];
1683	u8 imaicl[0x1];
1684	u8 qp_packet_based[0x1];
1685	u8 reserved_at_233[0x3];
1686	u8 qkv[0x1];
1687	u8 pkv[0x1];
1688	u8 set_deth_sqpn[0x1];
1689	u8 reserved_at_239[0x3];
1690	u8 xrc[0x1];
1691	u8 ud[0x1];
1692	u8 uc[0x1];
1693	u8 rc[0x1];
1694
1695	u8 uar_4k[0x1];
1696	u8 reserved_at_241[0x7];
1697	u8 fl_rc_qp_when_roce_disabled[0x1];
1698	u8 regexp_params[0x1];
1699	u8 uar_sz[0x6];
1700	u8 port_selection_cap[0x1];
1701	u8 reserved_at_251[0x1];
1702	u8 umem_uid_0[0x1];
1703	u8 reserved_at_253[0x5];
1704	u8 log_pg_sz[0x8];
1705
1706	u8 bf[0x1];
1707	u8 driver_version[0x1];
1708	u8 pad_tx_eth_packet[0x1];
1709	u8 reserved_at_263[0x3];
1710	u8 mkey_by_name[0x1];
1711	u8 reserved_at_267[0x4];
1712
1713	u8 log_bf_reg_size[0x5];
1714
1715	u8 reserved_at_270[0x3];
1716	u8 qp_error_syndrome[0x1];
1717	u8 reserved_at_274[0x2];
1718	u8 lag_dct[0x2];
1719	u8 lag_tx_port_affinity[0x1];
1720	u8 lag_native_fdb_selection[0x1];
1721	u8 reserved_at_27a[0x1];
1722	u8 lag_master[0x1];
1723	u8 num_lag_ports[0x4];
1724
1725	u8 reserved_at_280[0x10];
1726	u8 max_wqe_sz_sq[0x10];
1727
1728	u8 reserved_at_2a0[0x10];
1729	u8 max_wqe_sz_rq[0x10];
1730
1731	u8 max_flow_counter_31_16[0x10];
1732	u8 max_wqe_sz_sq_dc[0x10];
1733
1734	u8 reserved_at_2e0[0x7];
1735	u8 max_qp_mcg[0x19];
1736
1737	u8 reserved_at_300[0x10];
1738	u8 flow_counter_bulk_alloc[0x8];
1739	u8 log_max_mcg[0x8];
1740
1741	u8 reserved_at_320[0x3];
1742	u8 log_max_transport_domain[0x5];
1743	u8 reserved_at_328[0x2];
1744	u8 relaxed_ordering_read[0x1];
1745	u8 log_max_pd[0x5];
1746	u8 reserved_at_330[0x6];
1747	u8 pci_sync_for_fw_update_with_driver_unload[0x1];
1748	u8 vnic_env_cnt_steering_fail[0x1];
1749	u8 vport_counter_local_loopback[0x1];
1750	u8 q_counter_aggregation[0x1];
1751	u8 q_counter_other_vport[0x1];
1752	u8 log_max_xrcd[0x5];
1753
1754	u8 nic_receive_steering_discard[0x1];
1755	u8 receive_discard_vport_down[0x1];
1756	u8 transmit_discard_vport_down[0x1];
1757	u8 eq_overrun_count[0x1];
1758	u8 reserved_at_344[0x1];
1759	u8 invalid_command_count[0x1];
1760	u8 quota_exceeded_count[0x1];
1761	u8 reserved_at_347[0x1];
1762	u8 log_max_flow_counter_bulk[0x8];
1763	u8 max_flow_counter_15_0[0x10];
1764
1765
1766	u8 reserved_at_360[0x3];
1767	u8 log_max_rq[0x5];
1768	u8 reserved_at_368[0x3];
1769	u8 log_max_sq[0x5];
1770	u8 reserved_at_370[0x3];
1771	u8 log_max_tir[0x5];
1772	u8 reserved_at_378[0x3];
1773	u8 log_max_tis[0x5];
1774
1775	u8 basic_cyclic_rcv_wqe[0x1];
1776	u8 reserved_at_381[0x2];
1777	u8 log_max_rmp[0x5];
1778	u8 reserved_at_388[0x3];
1779	u8 log_max_rqt[0x5];
1780	u8 reserved_at_390[0x3];
1781	u8 log_max_rqt_size[0x5];
1782	u8 reserved_at_398[0x3];
1783	u8 log_max_tis_per_sq[0x5];
1784
1785	u8 ext_stride_num_range[0x1];
1786	u8 roce_rw_supported[0x1];
1787	u8 log_max_current_uc_list_wr_supported[0x1];
1788	u8 log_max_stride_sz_rq[0x5];
1789	u8 reserved_at_3a8[0x3];
1790	u8 log_min_stride_sz_rq[0x5];
1791	u8 reserved_at_3b0[0x3];
1792	u8 log_max_stride_sz_sq[0x5];
1793	u8 reserved_at_3b8[0x3];
1794	u8 log_min_stride_sz_sq[0x5];
1795
1796	u8 hairpin[0x1];
1797	u8 reserved_at_3c1[0x2];
1798	u8 log_max_hairpin_queues[0x5];
1799	u8 reserved_at_3c8[0x3];
1800	u8 log_max_hairpin_wq_data_sz[0x5];
1801	u8 reserved_at_3d0[0x3];
1802	u8 log_max_hairpin_num_packets[0x5];
1803	u8 reserved_at_3d8[0x3];
1804	u8 log_max_wq_sz[0x5];
1805
1806	u8 nic_vport_change_event[0x1];
1807	u8 disable_local_lb_uc[0x1];
1808	u8 disable_local_lb_mc[0x1];
1809	u8 log_min_hairpin_wq_data_sz[0x5];
1810	u8 reserved_at_3e8[0x1];
1811	u8 silent_mode[0x1];
1812	u8 vhca_state[0x1];
1813	u8 log_max_vlan_list[0x5];
1814	u8 reserved_at_3f0[0x3];
1815	u8 log_max_current_mc_list[0x5];
1816	u8 reserved_at_3f8[0x3];
1817	u8 log_max_current_uc_list[0x5];
1818
1819	u8 general_obj_types[0x40];
1820
1821	u8 sq_ts_format[0x2];
1822	u8 rq_ts_format[0x2];
1823	u8 steering_format_version[0x4];
1824	u8 create_qp_start_hint[0x18];
1825
1826	u8 reserved_at_460[0x1];
1827	u8 ats[0x1];
1828	u8 cross_vhca_rqt[0x1];
1829	u8 log_max_uctx[0x5];
1830	u8 reserved_at_468[0x1];
1831	u8 crypto[0x1];
1832	u8 ipsec_offload[0x1];
1833	u8 log_max_umem[0x5];
1834	u8 max_num_eqs[0x10];
1835
1836	u8 reserved_at_480[0x1];
1837	u8 tls_tx[0x1];
1838	u8 tls_rx[0x1];
1839	u8 log_max_l2_table[0x5];
1840	u8 reserved_at_488[0x8];
1841	u8 log_uar_page_sz[0x10];
1842
1843	u8 reserved_at_4a0[0x20];
1844	u8 device_frequency_mhz[0x20];
1845	u8 device_frequency_khz[0x20];
1846
1847	u8 reserved_at_500[0x20];
1848	u8 num_of_uars_per_page[0x20];
1849
1850	u8 flex_parser_protocols[0x20];
1851
1852	u8 max_geneve_tlv_options[0x8];
1853	u8 reserved_at_568[0x3];
1854	u8 max_geneve_tlv_option_data_len[0x5];
1855	u8 reserved_at_570[0x9];
1856	u8 adv_virtualization[0x1];
1857	u8 reserved_at_57a[0x6];
1858
1859	u8 reserved_at_580[0xb];
1860	u8 log_max_dci_stream_channels[0x5];
1861	u8 reserved_at_590[0x3];
1862	u8 log_max_dci_errored_streams[0x5];
1863	u8 reserved_at_598[0x8];
1864
1865	u8 reserved_at_5a0[0x10];
1866	u8 enhanced_cqe_compression[0x1];
1867	u8 reserved_at_5b1[0x2];
1868	u8 log_max_dek[0x5];
1869	u8 reserved_at_5b8[0x4];
1870	u8 mini_cqe_resp_stride_index[0x1];
1871	u8 cqe_128_always[0x1];
1872	u8 cqe_compression_128[0x1];
1873	u8 cqe_compression[0x1];
1874
1875	u8 cqe_compression_timeout[0x10];
1876	u8 cqe_compression_max_num[0x10];
1877
1878	u8 reserved_at_5e0[0x8];
1879	u8 flex_parser_id_gtpu_dw_0[0x4];
1880	u8 reserved_at_5ec[0x4];
1881	u8 tag_matching[0x1];
1882	u8 rndv_offload_rc[0x1];
1883	u8 rndv_offload_dc[0x1];
1884	u8 log_tag_matching_list_sz[0x5];
1885	u8 reserved_at_5f8[0x3];
1886	u8 log_max_xrq[0x5];
1887
1888	u8 affiliate_nic_vport_criteria[0x8];
1889	u8 native_port_num[0x8];
1890	u8 num_vhca_ports[0x8];
1891	u8 flex_parser_id_gtpu_teid[0x4];
1892	u8 reserved_at_61c[0x2];
1893	u8 sw_owner_id[0x1];
1894	u8 reserved_at_61f[0x1];
1895
1896	u8 max_num_of_monitor_counters[0x10];
1897	u8 num_ppcnt_monitor_counters[0x10];
1898
1899	u8 max_num_sf[0x10];
1900	u8 num_q_monitor_counters[0x10];
1901
1902	u8 reserved_at_660[0x20];
1903
1904	u8 sf[0x1];
1905	u8 sf_set_partition[0x1];
1906	u8 reserved_at_682[0x1];
1907	u8 log_max_sf[0x5];
1908	u8 apu[0x1];
1909	u8 reserved_at_689[0x4];
1910	u8 migration[0x1];
1911	u8 reserved_at_68e[0x2];
1912	u8 log_min_sf_size[0x8];
1913	u8 max_num_sf_partitions[0x8];
1914
1915	u8 uctx_cap[0x20];
1916
1917	u8 reserved_at_6c0[0x4];
1918	u8 flex_parser_id_geneve_tlv_option_0[0x4];
1919	u8 flex_parser_id_icmp_dw1[0x4];
1920	u8 flex_parser_id_icmp_dw0[0x4];
1921	u8 flex_parser_id_icmpv6_dw1[0x4];
1922	u8 flex_parser_id_icmpv6_dw0[0x4];
1923	u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1924	u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1925
1926	u8 max_num_match_definer[0x10];
1927	u8 sf_base_id[0x10];
1928
1929	u8 flex_parser_id_gtpu_dw_2[0x4];
1930	u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
1931	u8 num_total_dynamic_vf_msix[0x18];
1932	u8 reserved_at_720[0x14];
1933	u8 dynamic_msix_table_size[0xc];
1934	u8 reserved_at_740[0xc];
1935	u8 min_dynamic_vf_msix_table_size[0x4];
1936	u8 reserved_at_750[0x4];
1937	u8 max_dynamic_vf_msix_table_size[0xc];
1938
1939	u8 reserved_at_760[0x3];
1940	u8 log_max_num_header_modify_argument[0x5];
1941	u8 reserved_at_768[0x4];
1942	u8 log_header_modify_argument_granularity[0x4];
1943	u8 reserved_at_770[0x3];
1944	u8 log_header_modify_argument_max_alloc[0x5];
1945	u8 reserved_at_778[0x8];
1946
1947	u8 vhca_tunnel_commands[0x40];
1948	u8 match_definer_format_supported[0x40];
1949	};
1950
1951	enum {
1952	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000,
1953	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20),
1954	};
1955
1956	enum {
1957	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200,
1958	};
1959
1960	struct mlx5_ifc_cmd_hca_cap_2_bits {
1961	u8 reserved_at_0[0x80];
1962
1963	u8 migratable[0x1];
1964	u8 reserved_at_81[0x1f];
1965
1966	u8 max_reformat_insert_size[0x8];
1967	u8 max_reformat_insert_offset[0x8];
1968	u8 max_reformat_remove_size[0x8];
1969	u8 max_reformat_remove_offset[0x8];
1970
1971	u8 reserved_at_c0[0x8];
1972	u8 migration_multi_load[0x1];
1973	u8 migration_tracking_state[0x1];
1974	u8 reserved_at_ca[0x6];
1975	u8 migration_in_chunks[0x1];
1976	u8 reserved_at_d1[0xf];
1977
1978	u8 cross_vhca_object_to_object_supported[0x20];
1979
1980	u8 allowed_object_for_other_vhca_access[0x40];
1981
1982	u8 reserved_at_140[0x60];
1983
1984	u8 flow_table_type_2_type[0x8];
1985	u8 reserved_at_1a8[0x3];
1986	u8 log_min_mkey_entity_size[0x5];
1987	u8 reserved_at_1b0[0x10];
1988
1989	u8 reserved_at_1c0[0x60];
1990
1991	u8 reserved_at_220[0x1];
1992	u8 sw_vhca_id_valid[0x1];
1993	u8 sw_vhca_id[0xe];
1994	u8 reserved_at_230[0x10];
1995
1996	u8 reserved_at_240[0xb];
1997	u8 ts_cqe_metadata_size2wqe_counter[0x5];
1998	u8 reserved_at_250[0x10];
1999
2000	u8 reserved_at_260[0x120];
2001	u8 reserved_at_380[0x10];
2002	u8 ec_vf_vport_base[0x10];
2003
2004	u8 reserved_at_3a0[0x10];
2005	u8 max_rqt_vhca_id[0x10];
2006
2007	u8 reserved_at_3c0[0x440];
2008	};
2009
2010	enum mlx5_ifc_flow_destination_type {
2011	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
2012	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
2013	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
2014	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2015	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
2016	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
2017	};
2018
2019	enum mlx5_flow_table_miss_action {
2020	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2021	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2022	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2023	};
2024
2025	struct mlx5_ifc_dest_format_struct_bits {
2026	u8 destination_type[0x8];
2027	u8 destination_id[0x18];
2028
2029	u8 destination_eswitch_owner_vhca_id_valid[0x1];
2030	u8 packet_reformat[0x1];
2031	u8 reserved_at_22[0x6];
2032	u8 destination_table_type[0x8];
2033	u8 destination_eswitch_owner_vhca_id[0x10];
2034	};
2035
2036	struct mlx5_ifc_flow_counter_list_bits {
2037	u8 flow_counter_id[0x20];
2038
2039	u8 reserved_at_20[0x20];
2040	};
2041
2042	struct mlx5_ifc_extended_dest_format_bits {
2043	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2044
2045	u8 packet_reformat_id[0x20];
2046
2047	u8 reserved_at_60[0x20];
2048	};
2049
2050	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2051	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2052	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2053	};
2054
2055	struct mlx5_ifc_fte_match_param_bits {
2056	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2057
2058	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2059
2060	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2061
2062	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2063
2064	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2065
2066	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2067
2068	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2069
2070	u8 reserved_at_e00[0x200];
2071	};
2072
2073	enum {
2074	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2075	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2076	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2077	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2078	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2079	};
2080
2081	struct mlx5_ifc_rx_hash_field_select_bits {
2082	u8 l3_prot_type[0x1];
2083	u8 l4_prot_type[0x1];
2084	u8 selected_fields[0x1e];
2085	};
2086
2087	enum {
2088	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
2089	MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
2090	};
2091
2092	enum {
2093	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
2094	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
2095	};
2096
2097	struct mlx5_ifc_wq_bits {
2098	u8 wq_type[0x4];
2099	u8 wq_signature[0x1];
2100	u8 end_padding_mode[0x2];
2101	u8 cd_slave[0x1];
2102	u8 reserved_at_8[0x18];
2103
2104	u8 hds_skip_first_sge[0x1];
2105	u8 log2_hds_buf_size[0x3];
2106	u8 reserved_at_24[0x7];
2107	u8 page_offset[0x5];
2108	u8 lwm[0x10];
2109
2110	u8 reserved_at_40[0x8];
2111	u8 pd[0x18];
2112
2113	u8 reserved_at_60[0x8];
2114	u8 uar_page[0x18];
2115
2116	u8 dbr_addr[0x40];
2117
2118	u8 hw_counter[0x20];
2119
2120	u8 sw_counter[0x20];
2121
2122	u8 reserved_at_100[0xc];
2123	u8 log_wq_stride[0x4];
2124	u8 reserved_at_110[0x3];
2125	u8 log_wq_pg_sz[0x5];
2126	u8 reserved_at_118[0x3];
2127	u8 log_wq_sz[0x5];
2128
2129	u8 dbr_umem_valid[0x1];
2130	u8 wq_umem_valid[0x1];
2131	u8 reserved_at_122[0x1];
2132	u8 log_hairpin_num_packets[0x5];
2133	u8 reserved_at_128[0x3];
2134	u8 log_hairpin_data_sz[0x5];
2135
2136	u8 reserved_at_130[0x4];
2137	u8 log_wqe_num_of_strides[0x4];
2138	u8 two_byte_shift_en[0x1];
2139	u8 reserved_at_139[0x4];
2140	u8 log_wqe_stride_size[0x3];
2141
2142	u8 reserved_at_140[0x80];
2143
2144	u8 headers_mkey[0x20];
2145
2146	u8 shampo_enable[0x1];
2147	u8 reserved_at_1e1[0x4];
2148	u8 log_reservation_size[0x3];
2149	u8 reserved_at_1e8[0x5];
2150	u8 log_max_num_of_packets_per_reservation[0x3];
2151	u8 reserved_at_1f0[0x6];
2152	u8 log_headers_entry_size[0x2];
2153	u8 reserved_at_1f8[0x4];
2154	u8 log_headers_buffer_entry_num[0x4];
2155
2156	u8 reserved_at_200[0x400];
2157
2158	struct mlx5_ifc_cmd_pas_bits pas[];
2159	};
2160
2161	struct mlx5_ifc_rq_num_bits {
2162	u8 reserved_at_0[0x8];
2163	u8 rq_num[0x18];
2164	};
2165
2166	struct mlx5_ifc_rq_vhca_bits {
2167	u8 reserved_at_0[0x8];
2168	u8 rq_num[0x18];
2169	u8 reserved_at_20[0x10];
2170	u8 rq_vhca_id[0x10];
2171	};
2172
2173	struct mlx5_ifc_mac_address_layout_bits {
2174	u8 reserved_at_0[0x10];
2175	u8 mac_addr_47_32[0x10];
2176
2177	u8 mac_addr_31_0[0x20];
2178	};
2179
2180	struct mlx5_ifc_vlan_layout_bits {
2181	u8 reserved_at_0[0x14];
2182	u8 vlan[0x0c];
2183
2184	u8 reserved_at_20[0x20];
2185	};
2186
2187	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2188	u8 reserved_at_0[0xa0];
2189
2190	u8 min_time_between_cnps[0x20];
2191
2192	u8 reserved_at_c0[0x12];
2193	u8 cnp_dscp[0x6];
2194	u8 reserved_at_d8[0x4];
2195	u8 cnp_prio_mode[0x1];
2196	u8 cnp_802p_prio[0x3];
2197
2198	u8 reserved_at_e0[0x720];
2199	};
2200
2201	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2202	u8 reserved_at_0[0x60];
2203
2204	u8 reserved_at_60[0x4];
2205	u8 clamp_tgt_rate[0x1];
2206	u8 reserved_at_65[0x3];
2207	u8 clamp_tgt_rate_after_time_inc[0x1];
2208	u8 reserved_at_69[0x17];
2209
2210	u8 reserved_at_80[0x20];
2211
2212	u8 rpg_time_reset[0x20];
2213
2214	u8 rpg_byte_reset[0x20];
2215
2216	u8 rpg_threshold[0x20];
2217
2218	u8 rpg_max_rate[0x20];
2219
2220	u8 rpg_ai_rate[0x20];
2221
2222	u8 rpg_hai_rate[0x20];
2223
2224	u8 rpg_gd[0x20];
2225
2226	u8 rpg_min_dec_fac[0x20];
2227
2228	u8 rpg_min_rate[0x20];
2229
2230	u8 reserved_at_1c0[0xe0];
2231
2232	u8 rate_to_set_on_first_cnp[0x20];
2233
2234	u8 dce_tcp_g[0x20];
2235
2236	u8 dce_tcp_rtt[0x20];
2237
2238	u8 rate_reduce_monitor_period[0x20];
2239
2240	u8 reserved_at_320[0x20];
2241
2242	u8 initial_alpha_value[0x20];
2243
2244	u8 reserved_at_360[0x4a0];
2245	};
2246
2247	struct mlx5_ifc_cong_control_r_roce_general_bits {
2248	u8 reserved_at_0[0x80];
2249
2250	u8 reserved_at_80[0x10];
2251	u8 rtt_resp_dscp_valid[0x1];
2252	u8 reserved_at_91[0x9];
2253	u8 rtt_resp_dscp[0x6];
2254
2255	u8 reserved_at_a0[0x760];
2256	};
2257
2258	struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2259	u8 reserved_at_0[0x80];
2260
2261	u8 rppp_max_rps[0x20];
2262
2263	u8 rpg_time_reset[0x20];
2264
2265	u8 rpg_byte_reset[0x20];
2266
2267	u8 rpg_threshold[0x20];
2268
2269	u8 rpg_max_rate[0x20];
2270
2271	u8 rpg_ai_rate[0x20];
2272
2273	u8 rpg_hai_rate[0x20];
2274
2275	u8 rpg_gd[0x20];
2276
2277	u8 rpg_min_dec_fac[0x20];
2278
2279	u8 rpg_min_rate[0x20];
2280
2281	u8 reserved_at_1c0[0x640];
2282	};
2283
2284	enum {
2285	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2286	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2287	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2288	};
2289
2290	struct mlx5_ifc_resize_field_select_bits {
2291	u8 resize_field_select[0x20];
2292	};
2293
2294	struct mlx5_ifc_resource_dump_bits {
2295	u8 more_dump[0x1];
2296	u8 inline_dump[0x1];
2297	u8 reserved_at_2[0xa];
2298	u8 seq_num[0x4];
2299	u8 segment_type[0x10];
2300
2301	u8 reserved_at_20[0x10];
2302	u8 vhca_id[0x10];
2303
2304	u8 index1[0x20];
2305
2306	u8 index2[0x20];
2307
2308	u8 num_of_obj1[0x10];
2309	u8 num_of_obj2[0x10];
2310
2311	u8 reserved_at_a0[0x20];
2312
2313	u8 device_opaque[0x40];
2314
2315	u8 mkey[0x20];
2316
2317	u8 size[0x20];
2318
2319	u8 address[0x40];
2320
2321	u8 inline_data[52][0x20];
2322	};
2323
2324	struct mlx5_ifc_resource_dump_menu_record_bits {
2325	u8 reserved_at_0[0x4];
2326	u8 num_of_obj2_supports_active[0x1];
2327	u8 num_of_obj2_supports_all[0x1];
2328	u8 must_have_num_of_obj2[0x1];
2329	u8 support_num_of_obj2[0x1];
2330	u8 num_of_obj1_supports_active[0x1];
2331	u8 num_of_obj1_supports_all[0x1];
2332	u8 must_have_num_of_obj1[0x1];
2333	u8 support_num_of_obj1[0x1];
2334	u8 must_have_index2[0x1];
2335	u8 support_index2[0x1];
2336	u8 must_have_index1[0x1];
2337	u8 support_index1[0x1];
2338	u8 segment_type[0x10];
2339
2340	u8 segment_name[4][0x20];
2341
2342	u8 index1_name[4][0x20];
2343
2344	u8 index2_name[4][0x20];
2345	};
2346
2347	struct mlx5_ifc_resource_dump_segment_header_bits {
2348	u8 length_dw[0x10];
2349	u8 segment_type[0x10];
2350	};
2351
2352	struct mlx5_ifc_resource_dump_command_segment_bits {
2353	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2354
2355	u8 segment_called[0x10];
2356	u8 vhca_id[0x10];
2357
2358	u8 index1[0x20];
2359
2360	u8 index2[0x20];
2361
2362	u8 num_of_obj1[0x10];
2363	u8 num_of_obj2[0x10];
2364	};
2365
2366	struct mlx5_ifc_resource_dump_error_segment_bits {
2367	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2368
2369	u8 reserved_at_20[0x10];
2370	u8 syndrome_id[0x10];
2371
2372	u8 reserved_at_40[0x40];
2373
2374	u8 error[8][0x20];
2375	};
2376
2377	struct mlx5_ifc_resource_dump_info_segment_bits {
2378	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2379
2380	u8 reserved_at_20[0x18];
2381	u8 dump_version[0x8];
2382
2383	u8 hw_version[0x20];
2384
2385	u8 fw_version[0x20];
2386	};
2387
2388	struct mlx5_ifc_resource_dump_menu_segment_bits {
2389	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2390
2391	u8 reserved_at_20[0x10];
2392	u8 num_of_records[0x10];
2393
2394	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2395	};
2396
2397	struct mlx5_ifc_resource_dump_resource_segment_bits {
2398	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2399
2400	u8 reserved_at_20[0x20];
2401
2402	u8 index1[0x20];
2403
2404	u8 index2[0x20];
2405
2406	u8 payload[][0x20];
2407	};
2408
2409	struct mlx5_ifc_resource_dump_terminate_segment_bits {
2410	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2411	};
2412
2413	struct mlx5_ifc_menu_resource_dump_response_bits {
2414	struct mlx5_ifc_resource_dump_info_segment_bits info;
2415	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2416	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2417	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2418	};
2419
2420	enum {
2421	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2422	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2423	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2424	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2425	};
2426
2427	struct mlx5_ifc_modify_field_select_bits {
2428	u8 modify_field_select[0x20];
2429	};
2430
2431	struct mlx5_ifc_field_select_r_roce_np_bits {
2432	u8 field_select_r_roce_np[0x20];
2433	};
2434
2435	struct mlx5_ifc_field_select_r_roce_rp_bits {
2436	u8 field_select_r_roce_rp[0x20];
2437	};
2438
2439	enum {
2440	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2441	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2442	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2443	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2444	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2445	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2446	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2447	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2448	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2449	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2450	};
2451
2452	struct mlx5_ifc_field_select_802_1qau_rp_bits {
2453	u8 field_select_8021qaurp[0x20];
2454	};
2455
2456	struct mlx5_ifc_phys_layer_cntrs_bits {
2457	u8 time_since_last_clear_high[0x20];
2458
2459	u8 time_since_last_clear_low[0x20];
2460
2461	u8 symbol_errors_high[0x20];
2462
2463	u8 symbol_errors_low[0x20];
2464
2465	u8 sync_headers_errors_high[0x20];
2466
2467	u8 sync_headers_errors_low[0x20];
2468
2469	u8 edpl_bip_errors_lane0_high[0x20];
2470
2471	u8 edpl_bip_errors_lane0_low[0x20];
2472
2473	u8 edpl_bip_errors_lane1_high[0x20];
2474
2475	u8 edpl_bip_errors_lane1_low[0x20];
2476
2477	u8 edpl_bip_errors_lane2_high[0x20];
2478
2479	u8 edpl_bip_errors_lane2_low[0x20];
2480
2481	u8 edpl_bip_errors_lane3_high[0x20];
2482
2483	u8 edpl_bip_errors_lane3_low[0x20];
2484
2485	u8 fc_fec_corrected_blocks_lane0_high[0x20];
2486
2487	u8 fc_fec_corrected_blocks_lane0_low[0x20];
2488
2489	u8 fc_fec_corrected_blocks_lane1_high[0x20];
2490
2491	u8 fc_fec_corrected_blocks_lane1_low[0x20];
2492
2493	u8 fc_fec_corrected_blocks_lane2_high[0x20];
2494
2495	u8 fc_fec_corrected_blocks_lane2_low[0x20];
2496
2497	u8 fc_fec_corrected_blocks_lane3_high[0x20];
2498
2499	u8 fc_fec_corrected_blocks_lane3_low[0x20];
2500
2501	u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2502
2503	u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2504
2505	u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2506
2507	u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2508
2509	u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2510
2511	u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2512
2513	u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2514
2515	u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2516
2517	u8 rs_fec_corrected_blocks_high[0x20];
2518
2519	u8 rs_fec_corrected_blocks_low[0x20];
2520
2521	u8 rs_fec_uncorrectable_blocks_high[0x20];
2522
2523	u8 rs_fec_uncorrectable_blocks_low[0x20];
2524
2525	u8 rs_fec_no_errors_blocks_high[0x20];
2526
2527	u8 rs_fec_no_errors_blocks_low[0x20];
2528
2529	u8 rs_fec_single_error_blocks_high[0x20];
2530
2531	u8 rs_fec_single_error_blocks_low[0x20];
2532
2533	u8 rs_fec_corrected_symbols_total_high[0x20];
2534
2535	u8 rs_fec_corrected_symbols_total_low[0x20];
2536
2537	u8 rs_fec_corrected_symbols_lane0_high[0x20];
2538
2539	u8 rs_fec_corrected_symbols_lane0_low[0x20];
2540
2541	u8 rs_fec_corrected_symbols_lane1_high[0x20];
2542
2543	u8 rs_fec_corrected_symbols_lane1_low[0x20];
2544
2545	u8 rs_fec_corrected_symbols_lane2_high[0x20];
2546
2547	u8 rs_fec_corrected_symbols_lane2_low[0x20];
2548
2549	u8 rs_fec_corrected_symbols_lane3_high[0x20];
2550
2551	u8 rs_fec_corrected_symbols_lane3_low[0x20];
2552
2553	u8 link_down_events[0x20];
2554
2555	u8 successful_recovery_events[0x20];
2556
2557	u8 reserved_at_640[0x180];
2558	};
2559
2560	struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2561	u8 time_since_last_clear_high[0x20];
2562
2563	u8 time_since_last_clear_low[0x20];
2564
2565	u8 phy_received_bits_high[0x20];
2566
2567	u8 phy_received_bits_low[0x20];
2568
2569	u8 phy_symbol_errors_high[0x20];
2570
2571	u8 phy_symbol_errors_low[0x20];
2572
2573	u8 phy_corrected_bits_high[0x20];
2574
2575	u8 phy_corrected_bits_low[0x20];
2576
2577	u8 phy_corrected_bits_lane0_high[0x20];
2578
2579	u8 phy_corrected_bits_lane0_low[0x20];
2580
2581	u8 phy_corrected_bits_lane1_high[0x20];
2582
2583	u8 phy_corrected_bits_lane1_low[0x20];
2584
2585	u8 phy_corrected_bits_lane2_high[0x20];
2586
2587	u8 phy_corrected_bits_lane2_low[0x20];
2588
2589	u8 phy_corrected_bits_lane3_high[0x20];
2590
2591	u8 phy_corrected_bits_lane3_low[0x20];
2592
2593	u8 reserved_at_200[0x5c0];
2594	};
2595
2596	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2597	u8 symbol_error_counter[0x10];
2598
2599	u8 link_error_recovery_counter[0x8];
2600
2601	u8 link_downed_counter[0x8];
2602
2603	u8 port_rcv_errors[0x10];
2604
2605	u8 port_rcv_remote_physical_errors[0x10];
2606
2607	u8 port_rcv_switch_relay_errors[0x10];
2608
2609	u8 port_xmit_discards[0x10];
2610
2611	u8 port_xmit_constraint_errors[0x8];
2612
2613	u8 port_rcv_constraint_errors[0x8];
2614
2615	u8 reserved_at_70[0x8];
2616
2617	u8 link_overrun_errors[0x8];
2618
2619	u8 reserved_at_80[0x10];
2620
2621	u8 vl_15_dropped[0x10];
2622
2623	u8 reserved_at_a0[0x80];
2624
2625	u8 port_xmit_wait[0x20];
2626	};
2627
2628	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2629	u8 transmit_queue_high[0x20];
2630
2631	u8 transmit_queue_low[0x20];
2632
2633	u8 no_buffer_discard_uc_high[0x20];
2634
2635	u8 no_buffer_discard_uc_low[0x20];
2636
2637	u8 reserved_at_80[0x740];
2638	};
2639
2640	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2641	u8 wred_discard_high[0x20];
2642
2643	u8 wred_discard_low[0x20];
2644
2645	u8 ecn_marked_tc_high[0x20];
2646
2647	u8 ecn_marked_tc_low[0x20];
2648
2649	u8 reserved_at_80[0x740];
2650	};
2651
2652	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2653	u8 rx_octets_high[0x20];
2654
2655	u8 rx_octets_low[0x20];
2656
2657	u8 reserved_at_40[0xc0];
2658
2659	u8 rx_frames_high[0x20];
2660
2661	u8 rx_frames_low[0x20];
2662
2663	u8 tx_octets_high[0x20];
2664
2665	u8 tx_octets_low[0x20];
2666
2667	u8 reserved_at_180[0xc0];
2668
2669	u8 tx_frames_high[0x20];
2670
2671	u8 tx_frames_low[0x20];
2672
2673	u8 rx_pause_high[0x20];
2674
2675	u8 rx_pause_low[0x20];
2676
2677	u8 rx_pause_duration_high[0x20];
2678
2679	u8 rx_pause_duration_low[0x20];
2680
2681	u8 tx_pause_high[0x20];
2682
2683	u8 tx_pause_low[0x20];
2684
2685	u8 tx_pause_duration_high[0x20];
2686
2687	u8 tx_pause_duration_low[0x20];
2688
2689	u8 rx_pause_transition_high[0x20];
2690
2691	u8 rx_pause_transition_low[0x20];
2692
2693	u8 rx_discards_high[0x20];
2694
2695	u8 rx_discards_low[0x20];
2696
2697	u8 device_stall_minor_watermark_cnt_high[0x20];
2698
2699	u8 device_stall_minor_watermark_cnt_low[0x20];
2700
2701	u8 device_stall_critical_watermark_cnt_high[0x20];
2702
2703	u8 device_stall_critical_watermark_cnt_low[0x20];
2704
2705	u8 reserved_at_480[0x340];
2706	};
2707
2708	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2709	u8 port_transmit_wait_high[0x20];
2710
2711	u8 port_transmit_wait_low[0x20];
2712
2713	u8 reserved_at_40[0x100];
2714
2715	u8 rx_buffer_almost_full_high[0x20];
2716
2717	u8 rx_buffer_almost_full_low[0x20];
2718
2719	u8 rx_buffer_full_high[0x20];
2720
2721	u8 rx_buffer_full_low[0x20];
2722
2723	u8 rx_icrc_encapsulated_high[0x20];
2724
2725	u8 rx_icrc_encapsulated_low[0x20];
2726
2727	u8 reserved_at_200[0x5c0];
2728	};
2729
2730	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2731	u8 dot3stats_alignment_errors_high[0x20];
2732
2733	u8 dot3stats_alignment_errors_low[0x20];
2734
2735	u8 dot3stats_fcs_errors_high[0x20];
2736
2737	u8 dot3stats_fcs_errors_low[0x20];
2738
2739	u8 dot3stats_single_collision_frames_high[0x20];
2740
2741	u8 dot3stats_single_collision_frames_low[0x20];
2742
2743	u8 dot3stats_multiple_collision_frames_high[0x20];
2744
2745	u8 dot3stats_multiple_collision_frames_low[0x20];
2746
2747	u8 dot3stats_sqe_test_errors_high[0x20];
2748
2749	u8 dot3stats_sqe_test_errors_low[0x20];
2750
2751	u8 dot3stats_deferred_transmissions_high[0x20];
2752
2753	u8 dot3stats_deferred_transmissions_low[0x20];
2754
2755	u8 dot3stats_late_collisions_high[0x20];
2756
2757	u8 dot3stats_late_collisions_low[0x20];
2758
2759	u8 dot3stats_excessive_collisions_high[0x20];
2760
2761	u8 dot3stats_excessive_collisions_low[0x20];
2762
2763	u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2764
2765	u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2766
2767	u8 dot3stats_carrier_sense_errors_high[0x20];
2768
2769	u8 dot3stats_carrier_sense_errors_low[0x20];
2770
2771	u8 dot3stats_frame_too_longs_high[0x20];
2772
2773	u8 dot3stats_frame_too_longs_low[0x20];
2774
2775	u8 dot3stats_internal_mac_receive_errors_high[0x20];
2776
2777	u8 dot3stats_internal_mac_receive_errors_low[0x20];
2778
2779	u8 dot3stats_symbol_errors_high[0x20];
2780
2781	u8 dot3stats_symbol_errors_low[0x20];
2782
2783	u8 dot3control_in_unknown_opcodes_high[0x20];
2784
2785	u8 dot3control_in_unknown_opcodes_low[0x20];
2786
2787	u8 dot3in_pause_frames_high[0x20];
2788
2789	u8 dot3in_pause_frames_low[0x20];
2790
2791	u8 dot3out_pause_frames_high[0x20];
2792
2793	u8 dot3out_pause_frames_low[0x20];
2794
2795	u8 reserved_at_400[0x3c0];
2796	};
2797
2798	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2799	u8 ether_stats_drop_events_high[0x20];
2800
2801	u8 ether_stats_drop_events_low[0x20];
2802
2803	u8 ether_stats_octets_high[0x20];
2804
2805	u8 ether_stats_octets_low[0x20];
2806
2807	u8 ether_stats_pkts_high[0x20];
2808
2809	u8 ether_stats_pkts_low[0x20];
2810
2811	u8 ether_stats_broadcast_pkts_high[0x20];
2812
2813	u8 ether_stats_broadcast_pkts_low[0x20];
2814
2815	u8 ether_stats_multicast_pkts_high[0x20];
2816
2817	u8 ether_stats_multicast_pkts_low[0x20];
2818
2819	u8 ether_stats_crc_align_errors_high[0x20];
2820
2821	u8 ether_stats_crc_align_errors_low[0x20];
2822
2823	u8 ether_stats_undersize_pkts_high[0x20];
2824
2825	u8 ether_stats_undersize_pkts_low[0x20];
2826
2827	u8 ether_stats_oversize_pkts_high[0x20];
2828
2829	u8 ether_stats_oversize_pkts_low[0x20];
2830
2831	u8 ether_stats_fragments_high[0x20];
2832
2833	u8 ether_stats_fragments_low[0x20];
2834
2835	u8 ether_stats_jabbers_high[0x20];
2836
2837	u8 ether_stats_jabbers_low[0x20];
2838
2839	u8 ether_stats_collisions_high[0x20];
2840
2841	u8 ether_stats_collisions_low[0x20];
2842
2843	u8 ether_stats_pkts64octets_high[0x20];
2844
2845	u8 ether_stats_pkts64octets_low[0x20];
2846
2847	u8 ether_stats_pkts65to127octets_high[0x20];
2848
2849	u8 ether_stats_pkts65to127octets_low[0x20];
2850
2851	u8 ether_stats_pkts128to255octets_high[0x20];
2852
2853	u8 ether_stats_pkts128to255octets_low[0x20];
2854
2855	u8 ether_stats_pkts256to511octets_high[0x20];
2856
2857	u8 ether_stats_pkts256to511octets_low[0x20];
2858
2859	u8 ether_stats_pkts512to1023octets_high[0x20];
2860
2861	u8 ether_stats_pkts512to1023octets_low[0x20];
2862
2863	u8 ether_stats_pkts1024to1518octets_high[0x20];
2864
2865	u8 ether_stats_pkts1024to1518octets_low[0x20];
2866
2867	u8 ether_stats_pkts1519to2047octets_high[0x20];
2868
2869	u8 ether_stats_pkts1519to2047octets_low[0x20];
2870
2871	u8 ether_stats_pkts2048to4095octets_high[0x20];
2872
2873	u8 ether_stats_pkts2048to4095octets_low[0x20];
2874
2875	u8 ether_stats_pkts4096to8191octets_high[0x20];
2876
2877	u8 ether_stats_pkts4096to8191octets_low[0x20];
2878
2879	u8 ether_stats_pkts8192to10239octets_high[0x20];
2880
2881	u8 ether_stats_pkts8192to10239octets_low[0x20];
2882
2883	u8 reserved_at_540[0x280];
2884	};
2885
2886	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2887	u8 if_in_octets_high[0x20];
2888
2889	u8 if_in_octets_low[0x20];
2890
2891	u8 if_in_ucast_pkts_high[0x20];
2892
2893	u8 if_in_ucast_pkts_low[0x20];
2894
2895	u8 if_in_discards_high[0x20];
2896
2897	u8 if_in_discards_low[0x20];
2898
2899	u8 if_in_errors_high[0x20];
2900
2901	u8 if_in_errors_low[0x20];
2902
2903	u8 if_in_unknown_protos_high[0x20];
2904
2905	u8 if_in_unknown_protos_low[0x20];
2906
2907	u8 if_out_octets_high[0x20];
2908
2909	u8 if_out_octets_low[0x20];
2910
2911	u8 if_out_ucast_pkts_high[0x20];
2912
2913	u8 if_out_ucast_pkts_low[0x20];
2914
2915	u8 if_out_discards_high[0x20];
2916
2917	u8 if_out_discards_low[0x20];
2918
2919	u8 if_out_errors_high[0x20];
2920
2921	u8 if_out_errors_low[0x20];
2922
2923	u8 if_in_multicast_pkts_high[0x20];
2924
2925	u8 if_in_multicast_pkts_low[0x20];
2926
2927	u8 if_in_broadcast_pkts_high[0x20];
2928
2929	u8 if_in_broadcast_pkts_low[0x20];
2930
2931	u8 if_out_multicast_pkts_high[0x20];
2932
2933	u8 if_out_multicast_pkts_low[0x20];
2934
2935	u8 if_out_broadcast_pkts_high[0x20];
2936
2937	u8 if_out_broadcast_pkts_low[0x20];
2938
2939	u8 reserved_at_340[0x480];
2940	};
2941
2942	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2943	u8 a_frames_transmitted_ok_high[0x20];
2944
2945	u8 a_frames_transmitted_ok_low[0x20];
2946
2947	u8 a_frames_received_ok_high[0x20];
2948
2949	u8 a_frames_received_ok_low[0x20];
2950
2951	u8 a_frame_check_sequence_errors_high[0x20];
2952
2953	u8 a_frame_check_sequence_errors_low[0x20];
2954
2955	u8 a_alignment_errors_high[0x20];
2956
2957	u8 a_alignment_errors_low[0x20];
2958
2959	u8 a_octets_transmitted_ok_high[0x20];
2960
2961	u8 a_octets_transmitted_ok_low[0x20];
2962
2963	u8 a_octets_received_ok_high[0x20];
2964
2965	u8 a_octets_received_ok_low[0x20];
2966
2967	u8 a_multicast_frames_xmitted_ok_high[0x20];
2968
2969	u8 a_multicast_frames_xmitted_ok_low[0x20];
2970
2971	u8 a_broadcast_frames_xmitted_ok_high[0x20];
2972
2973	u8 a_broadcast_frames_xmitted_ok_low[0x20];
2974
2975	u8 a_multicast_frames_received_ok_high[0x20];
2976
2977	u8 a_multicast_frames_received_ok_low[0x20];
2978
2979	u8 a_broadcast_frames_received_ok_high[0x20];
2980
2981	u8 a_broadcast_frames_received_ok_low[0x20];
2982
2983	u8 a_in_range_length_errors_high[0x20];
2984
2985	u8 a_in_range_length_errors_low[0x20];
2986
2987	u8 a_out_of_range_length_field_high[0x20];
2988
2989	u8 a_out_of_range_length_field_low[0x20];
2990
2991	u8 a_frame_too_long_errors_high[0x20];
2992
2993	u8 a_frame_too_long_errors_low[0x20];
2994
2995	u8 a_symbol_error_during_carrier_high[0x20];
2996
2997	u8 a_symbol_error_during_carrier_low[0x20];
2998
2999	u8 a_mac_control_frames_transmitted_high[0x20];
3000
3001	u8 a_mac_control_frames_transmitted_low[0x20];
3002
3003	u8 a_mac_control_frames_received_high[0x20];
3004
3005	u8 a_mac_control_frames_received_low[0x20];
3006
3007	u8 a_unsupported_opcodes_received_high[0x20];
3008
3009	u8 a_unsupported_opcodes_received_low[0x20];
3010
3011	u8 a_pause_mac_ctrl_frames_received_high[0x20];
3012
3013	u8 a_pause_mac_ctrl_frames_received_low[0x20];
3014
3015	u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
3016
3017	u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
3018
3019	u8 reserved_at_4c0[0x300];
3020	};
3021
3022	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3023	u8 life_time_counter_high[0x20];
3024
3025	u8 life_time_counter_low[0x20];
3026
3027	u8 rx_errors[0x20];
3028
3029	u8 tx_errors[0x20];
3030
3031	u8 l0_to_recovery_eieos[0x20];
3032
3033	u8 l0_to_recovery_ts[0x20];
3034
3035	u8 l0_to_recovery_framing[0x20];
3036
3037	u8 l0_to_recovery_retrain[0x20];
3038
3039	u8 crc_error_dllp[0x20];
3040
3041	u8 crc_error_tlp[0x20];
3042
3043	u8 tx_overflow_buffer_pkt_high[0x20];
3044
3045	u8 tx_overflow_buffer_pkt_low[0x20];
3046
3047	u8 outbound_stalled_reads[0x20];
3048
3049	u8 outbound_stalled_writes[0x20];
3050
3051	u8 outbound_stalled_reads_events[0x20];
3052
3053	u8 outbound_stalled_writes_events[0x20];
3054
3055	u8 reserved_at_200[0x5c0];
3056	};
3057
3058	struct mlx5_ifc_cmd_inter_comp_event_bits {
3059	u8 command_completion_vector[0x20];
3060
3061	u8 reserved_at_20[0xc0];
3062	};
3063
3064	struct mlx5_ifc_stall_vl_event_bits {
3065	u8 reserved_at_0[0x18];
3066	u8 port_num[0x1];
3067	u8 reserved_at_19[0x3];
3068	u8 vl[0x4];
3069
3070	u8 reserved_at_20[0xa0];
3071	};
3072
3073	struct mlx5_ifc_db_bf_congestion_event_bits {
3074	u8 event_subtype[0x8];
3075	u8 reserved_at_8[0x8];
3076	u8 congestion_level[0x8];
3077	u8 reserved_at_18[0x8];
3078
3079	u8 reserved_at_20[0xa0];
3080	};
3081
3082	struct mlx5_ifc_gpio_event_bits {
3083	u8 reserved_at_0[0x60];
3084
3085	u8 gpio_event_hi[0x20];
3086
3087	u8 gpio_event_lo[0x20];
3088
3089	u8 reserved_at_a0[0x40];
3090	};
3091
3092	struct mlx5_ifc_port_state_change_event_bits {
3093	u8 reserved_at_0[0x40];
3094
3095	u8 port_num[0x4];
3096	u8 reserved_at_44[0x1c];
3097
3098	u8 reserved_at_60[0x80];
3099	};
3100
3101	struct mlx5_ifc_dropped_packet_logged_bits {
3102	u8 reserved_at_0[0xe0];
3103	};
3104
3105	struct mlx5_ifc_default_timeout_bits {
3106	u8 to_multiplier[0x3];
3107	u8 reserved_at_3[0x9];
3108	u8 to_value[0x14];
3109	};
3110
3111	struct mlx5_ifc_dtor_reg_bits {
3112	u8 reserved_at_0[0x20];
3113
3114	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3115
3116	u8 reserved_at_40[0x60];
3117
3118	struct mlx5_ifc_default_timeout_bits health_poll_to;
3119
3120	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3121
3122	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3123
3124	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3125
3126	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3127
3128	struct mlx5_ifc_default_timeout_bits tear_down_to;
3129
3130	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3131
3132	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3133
3134	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3135
3136	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3137
3138	u8 reserved_at_1c0[0x20];
3139	};
3140
3141	enum {
3142	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3143	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3144	};
3145
3146	struct mlx5_ifc_cq_error_bits {
3147	u8 reserved_at_0[0x8];
3148	u8 cqn[0x18];
3149
3150	u8 reserved_at_20[0x20];
3151
3152	u8 reserved_at_40[0x18];
3153	u8 syndrome[0x8];
3154
3155	u8 reserved_at_60[0x80];
3156	};
3157
3158	struct mlx5_ifc_rdma_page_fault_event_bits {
3159	u8 bytes_committed[0x20];
3160
3161	u8 r_key[0x20];
3162
3163	u8 reserved_at_40[0x10];
3164	u8 packet_len[0x10];
3165
3166	u8 rdma_op_len[0x20];
3167
3168	u8 rdma_va[0x40];
3169
3170	u8 reserved_at_c0[0x5];
3171	u8 rdma[0x1];
3172	u8 write[0x1];
3173	u8 requestor[0x1];
3174	u8 qp_number[0x18];
3175	};
3176
3177	struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3178	u8 bytes_committed[0x20];
3179
3180	u8 reserved_at_20[0x10];
3181	u8 wqe_index[0x10];
3182
3183	u8 reserved_at_40[0x10];
3184	u8 len[0x10];
3185
3186	u8 reserved_at_60[0x60];
3187
3188	u8 reserved_at_c0[0x5];
3189	u8 rdma[0x1];
3190	u8 write_read[0x1];
3191	u8 requestor[0x1];
3192	u8 qpn[0x18];
3193	};
3194
3195	struct mlx5_ifc_qp_events_bits {
3196	u8 reserved_at_0[0xa0];
3197
3198	u8 type[0x8];
3199	u8 reserved_at_a8[0x18];
3200
3201	u8 reserved_at_c0[0x8];
3202	u8 qpn_rqn_sqn[0x18];
3203	};
3204
3205	struct mlx5_ifc_dct_events_bits {
3206	u8 reserved_at_0[0xc0];
3207
3208	u8 reserved_at_c0[0x8];
3209	u8 dct_number[0x18];
3210	};
3211
3212	struct mlx5_ifc_comp_event_bits {
3213	u8 reserved_at_0[0xc0];
3214
3215	u8 reserved_at_c0[0x8];
3216	u8 cq_number[0x18];
3217	};
3218
3219	enum {
3220	MLX5_QPC_STATE_RST = 0x0,
3221	MLX5_QPC_STATE_INIT = 0x1,
3222	MLX5_QPC_STATE_RTR = 0x2,
3223	MLX5_QPC_STATE_RTS = 0x3,
3224	MLX5_QPC_STATE_SQER = 0x4,
3225	MLX5_QPC_STATE_ERR = 0x6,
3226	MLX5_QPC_STATE_SQD = 0x7,
3227	MLX5_QPC_STATE_SUSPENDED = 0x9,
3228	};
3229
3230	enum {
3231	MLX5_QPC_ST_RC = 0x0,
3232	MLX5_QPC_ST_UC = 0x1,
3233	MLX5_QPC_ST_UD = 0x2,
3234	MLX5_QPC_ST_XRC = 0x3,
3235	MLX5_QPC_ST_DCI = 0x5,
3236	MLX5_QPC_ST_QP0 = 0x7,
3237	MLX5_QPC_ST_QP1 = 0x8,
3238	MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3239	MLX5_QPC_ST_REG_UMR = 0xc,
3240	};
3241
3242	enum {
3243	MLX5_QPC_PM_STATE_ARMED = 0x0,
3244	MLX5_QPC_PM_STATE_REARM = 0x1,
3245	MLX5_QPC_PM_STATE_RESERVED = 0x2,
3246	MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3247	};
3248
3249	enum {
3250	MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3251	};
3252
3253	enum {
3254	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3255	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3256	};
3257
3258	enum {
3259	MLX5_QPC_MTU_256_BYTES = 0x1,
3260	MLX5_QPC_MTU_512_BYTES = 0x2,
3261	MLX5_QPC_MTU_1K_BYTES = 0x3,
3262	MLX5_QPC_MTU_2K_BYTES = 0x4,
3263	MLX5_QPC_MTU_4K_BYTES = 0x5,
3264	MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3265	};
3266
3267	enum {
3268	MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3269	MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3270	MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3271	MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3272	MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3273	MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3274	MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3275	MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3276	};
3277
3278	enum {
3279	MLX5_QPC_CS_REQ_DISABLE = 0x0,
3280	MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3281	MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3282	};
3283
3284	enum {
3285	MLX5_QPC_CS_RES_DISABLE = 0x0,
3286	MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3287	MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3288	};
3289
3290	enum {
3291	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3292	MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3293	MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3294	};
3295
3296	struct mlx5_ifc_qpc_bits {
3297	u8 state[0x4];
3298	u8 lag_tx_port_affinity[0x4];
3299	u8 st[0x8];
3300	u8 reserved_at_10[0x2];
3301	u8 isolate_vl_tc[0x1];
3302	u8 pm_state[0x2];
3303	u8 reserved_at_15[0x1];
3304	u8 req_e2e_credit_mode[0x2];
3305	u8 offload_type[0x4];
3306	u8 end_padding_mode[0x2];
3307	u8 reserved_at_1e[0x2];
3308
3309	u8 wq_signature[0x1];
3310	u8 block_lb_mc[0x1];
3311	u8 atomic_like_write_en[0x1];
3312	u8 latency_sensitive[0x1];
3313	u8 reserved_at_24[0x1];
3314	u8 drain_sigerr[0x1];
3315	u8 reserved_at_26[0x2];
3316	u8 pd[0x18];
3317
3318	u8 mtu[0x3];
3319	u8 log_msg_max[0x5];
3320	u8 reserved_at_48[0x1];
3321	u8 log_rq_size[0x4];
3322	u8 log_rq_stride[0x3];
3323	u8 no_sq[0x1];
3324	u8 log_sq_size[0x4];
3325	u8 reserved_at_55[0x1];
3326	u8 retry_mode[0x2];
3327	u8 ts_format[0x2];
3328	u8 reserved_at_5a[0x1];
3329	u8 rlky[0x1];
3330	u8 ulp_stateless_offload_mode[0x4];
3331
3332	u8 counter_set_id[0x8];
3333	u8 uar_page[0x18];
3334
3335	u8 reserved_at_80[0x8];
3336	u8 user_index[0x18];
3337
3338	u8 reserved_at_a0[0x3];
3339	u8 log_page_size[0x5];
3340	u8 remote_qpn[0x18];
3341
3342	struct mlx5_ifc_ads_bits primary_address_path;
3343
3344	struct mlx5_ifc_ads_bits secondary_address_path;
3345
3346	u8 log_ack_req_freq[0x4];
3347	u8 reserved_at_384[0x4];
3348	u8 log_sra_max[0x3];
3349	u8 reserved_at_38b[0x2];
3350	u8 retry_count[0x3];
3351	u8 rnr_retry[0x3];
3352	u8 reserved_at_393[0x1];
3353	u8 fre[0x1];
3354	u8 cur_rnr_retry[0x3];
3355	u8 cur_retry_count[0x3];
3356	u8 reserved_at_39b[0x5];
3357
3358	u8 reserved_at_3a0[0x20];
3359
3360	u8 reserved_at_3c0[0x8];
3361	u8 next_send_psn[0x18];
3362
3363	u8 reserved_at_3e0[0x3];
3364	u8 log_num_dci_stream_channels[0x5];
3365	u8 cqn_snd[0x18];
3366
3367	u8 reserved_at_400[0x3];
3368	u8 log_num_dci_errored_streams[0x5];
3369	u8 deth_sqpn[0x18];
3370
3371	u8 reserved_at_420[0x20];
3372
3373	u8 reserved_at_440[0x8];
3374	u8 last_acked_psn[0x18];
3375
3376	u8 reserved_at_460[0x8];
3377	u8 ssn[0x18];
3378
3379	u8 reserved_at_480[0x8];
3380	u8 log_rra_max[0x3];
3381	u8 reserved_at_48b[0x1];
3382	u8 atomic_mode[0x4];
3383	u8 rre[0x1];
3384	u8 rwe[0x1];
3385	u8 rae[0x1];
3386	u8 reserved_at_493[0x1];
3387	u8 page_offset[0x6];
3388	u8 reserved_at_49a[0x3];
3389	u8 cd_slave_receive[0x1];
3390	u8 cd_slave_send[0x1];
3391	u8 cd_master[0x1];
3392
3393	u8 reserved_at_4a0[0x3];
3394	u8 min_rnr_nak[0x5];
3395	u8 next_rcv_psn[0x18];
3396
3397	u8 reserved_at_4c0[0x8];
3398	u8 xrcd[0x18];
3399
3400	u8 reserved_at_4e0[0x8];
3401	u8 cqn_rcv[0x18];
3402
3403	u8 dbr_addr[0x40];
3404
3405	u8 q_key[0x20];
3406
3407	u8 reserved_at_560[0x5];
3408	u8 rq_type[0x3];
3409	u8 srqn_rmpn_xrqn[0x18];
3410
3411	u8 reserved_at_580[0x8];
3412	u8 rmsn[0x18];
3413
3414	u8 hw_sq_wqebb_counter[0x10];
3415	u8 sw_sq_wqebb_counter[0x10];
3416
3417	u8 hw_rq_counter[0x20];
3418
3419	u8 sw_rq_counter[0x20];
3420
3421	u8 reserved_at_600[0x20];
3422
3423	u8 reserved_at_620[0xf];
3424	u8 cgs[0x1];
3425	u8 cs_req[0x8];
3426	u8 cs_res[0x8];
3427
3428	u8 dc_access_key[0x40];
3429
3430	u8 reserved_at_680[0x3];
3431	u8 dbr_umem_valid[0x1];
3432
3433	u8 reserved_at_684[0xbc];
3434	};
3435
3436	struct mlx5_ifc_roce_addr_layout_bits {
3437	u8 source_l3_address[16][0x8];
3438
3439	u8 reserved_at_80[0x3];
3440	u8 vlan_valid[0x1];
3441	u8 vlan_id[0xc];
3442	u8 source_mac_47_32[0x10];
3443
3444	u8 source_mac_31_0[0x20];
3445
3446	u8 reserved_at_c0[0x14];
3447	u8 roce_l3_type[0x4];
3448	u8 roce_version[0x8];
3449
3450	u8 reserved_at_e0[0x20];
3451	};
3452
3453	struct mlx5_ifc_crypto_cap_bits {
3454	u8 reserved_at_0[0x3];
3455	u8 synchronize_dek[0x1];
3456	u8 int_kek_manual[0x1];
3457	u8 int_kek_auto[0x1];
3458	u8 reserved_at_6[0x1a];
3459
3460	u8 reserved_at_20[0x3];
3461	u8 log_dek_max_alloc[0x5];
3462	u8 reserved_at_28[0x3];
3463	u8 log_max_num_deks[0x5];
3464	u8 reserved_at_30[0x10];
3465
3466	u8 reserved_at_40[0x20];
3467
3468	u8 reserved_at_60[0x3];
3469	u8 log_dek_granularity[0x5];
3470	u8 reserved_at_68[0x3];
3471	u8 log_max_num_int_kek[0x5];
3472	u8 sw_wrapped_dek[0x10];
3473
3474	u8 reserved_at_80[0x780];
3475	};
3476
3477	union mlx5_ifc_hca_cap_union_bits {
3478	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3479	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3480	struct mlx5_ifc_odp_cap_bits odp_cap;
3481	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3482	struct mlx5_ifc_roce_cap_bits roce_cap;
3483	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3484	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3485	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3486	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3487	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3488	struct mlx5_ifc_qos_cap_bits qos_cap;
3489	struct mlx5_ifc_debug_cap_bits debug_cap;
3490	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3491	struct mlx5_ifc_tls_cap_bits tls_cap;
3492	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3493	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3494	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3495	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3496	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3497	u8 reserved_at_0[0x8000];
3498	};
3499
3500	enum {
3501	MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3502	MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3503	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3504	MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3505	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3506	MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3507	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3508	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3509	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3510	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3511	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3512	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3513	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3514	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3515	};
3516
3517	enum {
3518	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3519	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3520	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3521	};
3522
3523	enum {
3524	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
3525	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
3526	};
3527
3528	struct mlx5_ifc_vlan_bits {
3529	u8 ethtype[0x10];
3530	u8 prio[0x3];
3531	u8 cfi[0x1];
3532	u8 vid[0xc];
3533	};
3534
3535	enum {
3536	MLX5_FLOW_METER_COLOR_RED = 0x0,
3537	MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3538	MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3539	MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3540	};
3541
3542	enum {
3543	MLX5_EXE_ASO_FLOW_METER = 0x2,
3544	};
3545
3546	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3547	u8 return_reg_id[0x4];
3548	u8 aso_type[0x4];
3549	u8 reserved_at_8[0x14];
3550	u8 action[0x1];
3551	u8 init_color[0x2];
3552	u8 meter_id[0x1];
3553	};
3554
3555	union mlx5_ifc_exe_aso_ctrl {
3556	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3557	};
3558
3559	struct mlx5_ifc_execute_aso_bits {
3560	u8 valid[0x1];
3561	u8 reserved_at_1[0x7];
3562	u8 aso_object_id[0x18];
3563
3564	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3565	};
3566
3567	struct mlx5_ifc_flow_context_bits {
3568	struct mlx5_ifc_vlan_bits push_vlan;
3569
3570	u8 group_id[0x20];
3571
3572	u8 reserved_at_40[0x8];
3573	u8 flow_tag[0x18];
3574
3575	u8 reserved_at_60[0x10];
3576	u8 action[0x10];
3577
3578	u8 extended_destination[0x1];
3579	u8 uplink_hairpin_en[0x1];
3580	u8 flow_source[0x2];
3581	u8 encrypt_decrypt_type[0x4];
3582	u8 destination_list_size[0x18];
3583
3584	u8 reserved_at_a0[0x8];
3585	u8 flow_counter_list_size[0x18];
3586
3587	u8 packet_reformat_id[0x20];
3588
3589	u8 modify_header_id[0x20];
3590
3591	struct mlx5_ifc_vlan_bits push_vlan_2;
3592
3593	u8 encrypt_decrypt_obj_id[0x20];
3594	u8 reserved_at_140[0xc0];
3595
3596	struct mlx5_ifc_fte_match_param_bits match_value;
3597
3598	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3599
3600	u8 reserved_at_1300[0x500];
3601
3602	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3603	};
3604
3605	enum {
3606	MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3607	MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3608	};
3609
3610	struct mlx5_ifc_xrc_srqc_bits {
3611	u8 state[0x4];
3612	u8 log_xrc_srq_size[0x4];
3613	u8 reserved_at_8[0x18];
3614
3615	u8 wq_signature[0x1];
3616	u8 cont_srq[0x1];
3617	u8 reserved_at_22[0x1];
3618	u8 rlky[0x1];
3619	u8 basic_cyclic_rcv_wqe[0x1];
3620	u8 log_rq_stride[0x3];
3621	u8 xrcd[0x18];
3622
3623	u8 page_offset[0x6];
3624	u8 reserved_at_46[0x1];
3625	u8 dbr_umem_valid[0x1];
3626	u8 cqn[0x18];
3627
3628	u8 reserved_at_60[0x20];
3629
3630	u8 user_index_equal_xrc_srqn[0x1];
3631	u8 reserved_at_81[0x1];
3632	u8 log_page_size[0x6];
3633	u8 user_index[0x18];
3634
3635	u8 reserved_at_a0[0x20];
3636
3637	u8 reserved_at_c0[0x8];
3638	u8 pd[0x18];
3639
3640	u8 lwm[0x10];
3641	u8 wqe_cnt[0x10];
3642
3643	u8 reserved_at_100[0x40];
3644
3645	u8 db_record_addr_h[0x20];
3646
3647	u8 db_record_addr_l[0x1e];
3648	u8 reserved_at_17e[0x2];
3649
3650	u8 reserved_at_180[0x80];
3651	};
3652
3653	struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3654	u8 counter_error_queues[0x20];
3655
3656	u8 total_error_queues[0x20];
3657
3658	u8 send_queue_priority_update_flow[0x20];
3659
3660	u8 reserved_at_60[0x20];
3661
3662	u8 nic_receive_steering_discard[0x40];
3663
3664	u8 receive_discard_vport_down[0x40];
3665
3666	u8 transmit_discard_vport_down[0x40];
3667
3668	u8 async_eq_overrun[0x20];
3669
3670	u8 comp_eq_overrun[0x20];
3671
3672	u8 reserved_at_180[0x20];
3673
3674	u8 invalid_command[0x20];
3675
3676	u8 quota_exceeded_command[0x20];
3677
3678	u8 internal_rq_out_of_buffer[0x20];
3679
3680	u8 cq_overrun[0x20];
3681
3682	u8 eth_wqe_too_small[0x20];
3683
3684	u8 reserved_at_220[0xc0];
3685
3686	u8 generated_pkt_steering_fail[0x40];
3687
3688	u8 handled_pkt_steering_fail[0x40];
3689
3690	u8 reserved_at_360[0xc80];
3691	};
3692
3693	struct mlx5_ifc_traffic_counter_bits {
3694	u8 packets[0x40];
3695
3696	u8 octets[0x40];
3697	};
3698
3699	struct mlx5_ifc_tisc_bits {
3700	u8 strict_lag_tx_port_affinity[0x1];
3701	u8 tls_en[0x1];
3702	u8 reserved_at_2[0x2];
3703	u8 lag_tx_port_affinity[0x04];
3704
3705	u8 reserved_at_8[0x4];
3706	u8 prio[0x4];
3707	u8 reserved_at_10[0x10];
3708
3709	u8 reserved_at_20[0x100];
3710
3711	u8 reserved_at_120[0x8];
3712	u8 transport_domain[0x18];
3713
3714	u8 reserved_at_140[0x8];
3715	u8 underlay_qpn[0x18];
3716
3717	u8 reserved_at_160[0x8];
3718	u8 pd[0x18];
3719
3720	u8 reserved_at_180[0x380];
3721	};
3722
3723	enum {
3724	MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3725	MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3726	};
3727
3728	enum {
3729	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3730	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
3731	};
3732
3733	enum {
3734	MLX5_RX_HASH_FN_NONE = 0x0,
3735	MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3736	MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3737	};
3738
3739	enum {
3740	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3741	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3742	};
3743
3744	struct mlx5_ifc_tirc_bits {
3745	u8 reserved_at_0[0x20];
3746
3747	u8 disp_type[0x4];
3748	u8 tls_en[0x1];
3749	u8 reserved_at_25[0x1b];
3750
3751	u8 reserved_at_40[0x40];
3752
3753	u8 reserved_at_80[0x4];
3754	u8 lro_timeout_period_usecs[0x10];
3755	u8 packet_merge_mask[0x4];
3756	u8 lro_max_ip_payload_size[0x8];
3757
3758	u8 reserved_at_a0[0x40];
3759
3760	u8 reserved_at_e0[0x8];
3761	u8 inline_rqn[0x18];
3762
3763	u8 rx_hash_symmetric[0x1];
3764	u8 reserved_at_101[0x1];
3765	u8 tunneled_offload_en[0x1];
3766	u8 reserved_at_103[0x5];
3767	u8 indirect_table[0x18];
3768
3769	u8 rx_hash_fn[0x4];
3770	u8 reserved_at_124[0x2];
3771	u8 self_lb_block[0x2];
3772	u8 transport_domain[0x18];
3773
3774	u8 rx_hash_toeplitz_key[10][0x20];
3775
3776	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3777
3778	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3779
3780	u8 reserved_at_2c0[0x4c0];
3781	};
3782
3783	enum {
3784	MLX5_SRQC_STATE_GOOD = 0x0,
3785	MLX5_SRQC_STATE_ERROR = 0x1,
3786	};
3787
3788	struct mlx5_ifc_srqc_bits {
3789	u8 state[0x4];
3790	u8 log_srq_size[0x4];
3791	u8 reserved_at_8[0x18];
3792
3793	u8 wq_signature[0x1];
3794	u8 cont_srq[0x1];
3795	u8 reserved_at_22[0x1];
3796	u8 rlky[0x1];
3797	u8 reserved_at_24[0x1];
3798	u8 log_rq_stride[0x3];
3799	u8 xrcd[0x18];
3800
3801	u8 page_offset[0x6];
3802	u8 reserved_at_46[0x2];
3803	u8 cqn[0x18];
3804
3805	u8 reserved_at_60[0x20];
3806
3807	u8 reserved_at_80[0x2];
3808	u8 log_page_size[0x6];
3809	u8 reserved_at_88[0x18];
3810
3811	u8 reserved_at_a0[0x20];
3812
3813	u8 reserved_at_c0[0x8];
3814	u8 pd[0x18];
3815
3816	u8 lwm[0x10];
3817	u8 wqe_cnt[0x10];
3818
3819	u8 reserved_at_100[0x40];
3820
3821	u8 dbr_addr[0x40];
3822
3823	u8 reserved_at_180[0x80];
3824	};
3825
3826	enum {
3827	MLX5_SQC_STATE_RST = 0x0,
3828	MLX5_SQC_STATE_RDY = 0x1,
3829	MLX5_SQC_STATE_ERR = 0x3,
3830	};
3831
3832	struct mlx5_ifc_sqc_bits {
3833	u8 rlky[0x1];
3834	u8 cd_master[0x1];
3835	u8 fre[0x1];
3836	u8 flush_in_error_en[0x1];
3837	u8 allow_multi_pkt_send_wqe[0x1];
3838	u8 min_wqe_inline_mode[0x3];
3839	u8 state[0x4];
3840	u8 reg_umr[0x1];
3841	u8 allow_swp[0x1];
3842	u8 hairpin[0x1];
3843	u8 reserved_at_f[0xb];
3844	u8 ts_format[0x2];
3845	u8 reserved_at_1c[0x4];
3846
3847	u8 reserved_at_20[0x8];
3848	u8 user_index[0x18];
3849
3850	u8 reserved_at_40[0x8];
3851	u8 cqn[0x18];
3852
3853	u8 reserved_at_60[0x8];
3854	u8 hairpin_peer_rq[0x18];
3855
3856	u8 reserved_at_80[0x10];
3857	u8 hairpin_peer_vhca[0x10];
3858
3859	u8 reserved_at_a0[0x20];
3860
3861	u8 reserved_at_c0[0x8];
3862	u8 ts_cqe_to_dest_cqn[0x18];
3863
3864	u8 reserved_at_e0[0x10];
3865	u8 packet_pacing_rate_limit_index[0x10];
3866	u8 tis_lst_sz[0x10];
3867	u8 qos_queue_group_id[0x10];
3868
3869	u8 reserved_at_120[0x40];
3870
3871	u8 reserved_at_160[0x8];
3872	u8 tis_num_0[0x18];
3873
3874	struct mlx5_ifc_wq_bits wq;
3875	};
3876
3877	enum {
3878	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3879	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3880	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3881	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3882	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3883	};
3884
3885	enum {
3886	ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3887	ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3888	ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3889	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3890	};
3891
3892	struct mlx5_ifc_scheduling_context_bits {
3893	u8 element_type[0x8];
3894	u8 reserved_at_8[0x18];
3895
3896	u8 element_attributes[0x20];
3897
3898	u8 parent_element_id[0x20];
3899
3900	u8 reserved_at_60[0x40];
3901
3902	u8 bw_share[0x20];
3903
3904	u8 max_average_bw[0x20];
3905
3906	u8 reserved_at_e0[0x120];
3907	};
3908
3909	struct mlx5_ifc_rqtc_bits {
3910	u8 reserved_at_0[0xa0];
3911
3912	u8 reserved_at_a0[0x5];
3913	u8 list_q_type[0x3];
3914	u8 reserved_at_a8[0x8];
3915	u8 rqt_max_size[0x10];
3916
3917	u8 rq_vhca_id_format[0x1];
3918	u8 reserved_at_c1[0xf];
3919	u8 rqt_actual_size[0x10];
3920
3921	u8 reserved_at_e0[0x6a0];
3922
3923	union {
3924	DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
3925	DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
3926	};
3927	};
3928
3929	enum {
3930	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3931	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3932	};
3933
3934	enum {
3935	MLX5_RQC_STATE_RST = 0x0,
3936	MLX5_RQC_STATE_RDY = 0x1,
3937	MLX5_RQC_STATE_ERR = 0x3,
3938	};
3939
3940	enum {
3941	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3942	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3943	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3944	};
3945
3946	enum {
3947	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3948	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3949	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3950	};
3951
3952	struct mlx5_ifc_rqc_bits {
3953	u8 rlky[0x1];
3954	u8 delay_drop_en[0x1];
3955	u8 scatter_fcs[0x1];
3956	u8 vsd[0x1];
3957	u8 mem_rq_type[0x4];
3958	u8 state[0x4];
3959	u8 reserved_at_c[0x1];
3960	u8 flush_in_error_en[0x1];
3961	u8 hairpin[0x1];
3962	u8 reserved_at_f[0xb];
3963	u8 ts_format[0x2];
3964	u8 reserved_at_1c[0x4];
3965
3966	u8 reserved_at_20[0x8];
3967	u8 user_index[0x18];
3968
3969	u8 reserved_at_40[0x8];
3970	u8 cqn[0x18];
3971
3972	u8 counter_set_id[0x8];
3973	u8 reserved_at_68[0x18];
3974
3975	u8 reserved_at_80[0x8];
3976	u8 rmpn[0x18];
3977
3978	u8 reserved_at_a0[0x8];
3979	u8 hairpin_peer_sq[0x18];
3980
3981	u8 reserved_at_c0[0x10];
3982	u8 hairpin_peer_vhca[0x10];
3983
3984	u8 reserved_at_e0[0x46];
3985	u8 shampo_no_match_alignment_granularity[0x2];
3986	u8 reserved_at_128[0x6];
3987	u8 shampo_match_criteria_type[0x2];
3988	u8 reservation_timeout[0x10];
3989
3990	u8 reserved_at_140[0x40];
3991
3992	struct mlx5_ifc_wq_bits wq;
3993	};
3994
3995	enum {
3996	MLX5_RMPC_STATE_RDY = 0x1,
3997	MLX5_RMPC_STATE_ERR = 0x3,
3998	};
3999
4000	struct mlx5_ifc_rmpc_bits {
4001	u8 reserved_at_0[0x8];
4002	u8 state[0x4];
4003	u8 reserved_at_c[0x14];
4004
4005	u8 basic_cyclic_rcv_wqe[0x1];
4006	u8 reserved_at_21[0x1f];
4007
4008	u8 reserved_at_40[0x140];
4009
4010	struct mlx5_ifc_wq_bits wq;
4011	};
4012
4013	enum {
4014	VHCA_ID_TYPE_HW = 0,
4015	VHCA_ID_TYPE_SW = 1,
4016	};
4017
4018	struct mlx5_ifc_nic_vport_context_bits {
4019	u8 reserved_at_0[0x5];
4020	u8 min_wqe_inline_mode[0x3];
4021	u8 reserved_at_8[0x15];
4022	u8 disable_mc_local_lb[0x1];
4023	u8 disable_uc_local_lb[0x1];
4024	u8 roce_en[0x1];
4025
4026	u8 arm_change_event[0x1];
4027	u8 reserved_at_21[0x1a];
4028	u8 event_on_mtu[0x1];
4029	u8 event_on_promisc_change[0x1];
4030	u8 event_on_vlan_change[0x1];
4031	u8 event_on_mc_address_change[0x1];
4032	u8 event_on_uc_address_change[0x1];
4033
4034	u8 vhca_id_type[0x1];
4035	u8 reserved_at_41[0xb];
4036	u8 affiliation_criteria[0x4];
4037	u8 affiliated_vhca_id[0x10];
4038
4039	u8 reserved_at_60[0xa0];
4040
4041	u8 reserved_at_100[0x1];
4042	u8 sd_group[0x3];
4043	u8 reserved_at_104[0x1c];
4044
4045	u8 reserved_at_120[0x10];
4046	u8 mtu[0x10];
4047
4048	u8 system_image_guid[0x40];
4049	u8 port_guid[0x40];
4050	u8 node_guid[0x40];
4051
4052	u8 reserved_at_200[0x140];
4053	u8 qkey_violation_counter[0x10];
4054	u8 reserved_at_350[0x430];
4055
4056	u8 promisc_uc[0x1];
4057	u8 promisc_mc[0x1];
4058	u8 promisc_all[0x1];
4059	u8 reserved_at_783[0x2];
4060	u8 allowed_list_type[0x3];
4061	u8 reserved_at_788[0xc];
4062	u8 allowed_list_size[0xc];
4063
4064	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4065
4066	u8 reserved_at_7e0[0x20];
4067
4068	u8 current_uc_mac_address[][0x40];
4069	};
4070
4071	enum {
4072	MLX5_MKC_ACCESS_MODE_PA = 0x0,
4073	MLX5_MKC_ACCESS_MODE_MTT = 0x1,
4074	MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
4075	MLX5_MKC_ACCESS_MODE_KSM = 0x3,
4076	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4077	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4078	};
4079
4080	struct mlx5_ifc_mkc_bits {
4081	u8 reserved_at_0[0x1];
4082	u8 free[0x1];
4083	u8 reserved_at_2[0x1];
4084	u8 access_mode_4_2[0x3];
4085	u8 reserved_at_6[0x7];
4086	u8 relaxed_ordering_write[0x1];
4087	u8 reserved_at_e[0x1];
4088	u8 small_fence_on_rdma_read_response[0x1];
4089	u8 umr_en[0x1];
4090	u8 a[0x1];
4091	u8 rw[0x1];
4092	u8 rr[0x1];
4093	u8 lw[0x1];
4094	u8 lr[0x1];
4095	u8 access_mode_1_0[0x2];
4096	u8 reserved_at_18[0x2];
4097	u8 ma_translation_mode[0x2];
4098	u8 reserved_at_1c[0x4];
4099
4100	u8 qpn[0x18];
4101	u8 mkey_7_0[0x8];
4102
4103	u8 reserved_at_40[0x20];
4104
4105	u8 length64[0x1];
4106	u8 bsf_en[0x1];
4107	u8 sync_umr[0x1];
4108	u8 reserved_at_63[0x2];
4109	u8 expected_sigerr_count[0x1];
4110	u8 reserved_at_66[0x1];
4111	u8 en_rinval[0x1];
4112	u8 pd[0x18];
4113
4114	u8 start_addr[0x40];
4115
4116	u8 len[0x40];
4117
4118	u8 bsf_octword_size[0x20];
4119
4120	u8 reserved_at_120[0x80];
4121
4122	u8 translations_octword_size[0x20];
4123
4124	u8 reserved_at_1c0[0x19];
4125	u8 relaxed_ordering_read[0x1];
4126	u8 reserved_at_1d9[0x1];
4127	u8 log_page_size[0x5];
4128
4129	u8 reserved_at_1e0[0x20];
4130	};
4131
4132	struct mlx5_ifc_pkey_bits {
4133	u8 reserved_at_0[0x10];
4134	u8 pkey[0x10];
4135	};
4136
4137	struct mlx5_ifc_array128_auto_bits {
4138	u8 array128_auto[16][0x8];
4139	};
4140
4141	struct mlx5_ifc_hca_vport_context_bits {
4142	u8 field_select[0x20];
4143
4144	u8 reserved_at_20[0xe0];
4145
4146	u8 sm_virt_aware[0x1];
4147	u8 has_smi[0x1];
4148	u8 has_raw[0x1];
4149	u8 grh_required[0x1];
4150	u8 reserved_at_104[0xc];
4151	u8 port_physical_state[0x4];
4152	u8 vport_state_policy[0x4];
4153	u8 port_state[0x4];
4154	u8 vport_state[0x4];
4155
4156	u8 reserved_at_120[0x20];
4157
4158	u8 system_image_guid[0x40];
4159
4160	u8 port_guid[0x40];
4161
4162	u8 node_guid[0x40];
4163
4164	u8 cap_mask1[0x20];
4165
4166	u8 cap_mask1_field_select[0x20];
4167
4168	u8 cap_mask2[0x20];
4169
4170	u8 cap_mask2_field_select[0x20];
4171
4172	u8 reserved_at_280[0x80];
4173
4174	u8 lid[0x10];
4175	u8 reserved_at_310[0x4];
4176	u8 init_type_reply[0x4];
4177	u8 lmc[0x3];
4178	u8 subnet_timeout[0x5];
4179
4180	u8 sm_lid[0x10];
4181	u8 sm_sl[0x4];
4182	u8 reserved_at_334[0xc];
4183
4184	u8 qkey_violation_counter[0x10];
4185	u8 pkey_violation_counter[0x10];
4186
4187	u8 reserved_at_360[0xca0];
4188	};
4189
4190	struct mlx5_ifc_esw_vport_context_bits {
4191	u8 fdb_to_vport_reg_c[0x1];
4192	u8 reserved_at_1[0x2];
4193	u8 vport_svlan_strip[0x1];
4194	u8 vport_cvlan_strip[0x1];
4195	u8 vport_svlan_insert[0x1];
4196	u8 vport_cvlan_insert[0x2];
4197	u8 fdb_to_vport_reg_c_id[0x8];
4198	u8 reserved_at_10[0x10];
4199
4200	u8 reserved_at_20[0x20];
4201
4202	u8 svlan_cfi[0x1];
4203	u8 svlan_pcp[0x3];
4204	u8 svlan_id[0xc];
4205	u8 cvlan_cfi[0x1];
4206	u8 cvlan_pcp[0x3];
4207	u8 cvlan_id[0xc];
4208
4209	u8 reserved_at_60[0x720];
4210
4211	u8 sw_steering_vport_icm_address_rx[0x40];
4212
4213	u8 sw_steering_vport_icm_address_tx[0x40];
4214	};
4215
4216	enum {
4217	MLX5_EQC_STATUS_OK = 0x0,
4218	MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4219	};
4220
4221	enum {
4222	MLX5_EQC_ST_ARMED = 0x9,
4223	MLX5_EQC_ST_FIRED = 0xa,
4224	};
4225
4226	struct mlx5_ifc_eqc_bits {
4227	u8 status[0x4];
4228	u8 reserved_at_4[0x9];
4229	u8 ec[0x1];
4230	u8 oi[0x1];
4231	u8 reserved_at_f[0x5];
4232	u8 st[0x4];
4233	u8 reserved_at_18[0x8];
4234
4235	u8 reserved_at_20[0x20];
4236
4237	u8 reserved_at_40[0x14];
4238	u8 page_offset[0x6];
4239	u8 reserved_at_5a[0x6];
4240
4241	u8 reserved_at_60[0x3];
4242	u8 log_eq_size[0x5];
4243	u8 uar_page[0x18];
4244
4245	u8 reserved_at_80[0x20];
4246
4247	u8 reserved_at_a0[0x14];
4248	u8 intr[0xc];
4249
4250	u8 reserved_at_c0[0x3];
4251	u8 log_page_size[0x5];
4252	u8 reserved_at_c8[0x18];
4253
4254	u8 reserved_at_e0[0x60];
4255
4256	u8 reserved_at_140[0x8];
4257	u8 consumer_counter[0x18];
4258
4259	u8 reserved_at_160[0x8];
4260	u8 producer_counter[0x18];
4261
4262	u8 reserved_at_180[0x80];
4263	};
4264
4265	enum {
4266	MLX5_DCTC_STATE_ACTIVE = 0x0,
4267	MLX5_DCTC_STATE_DRAINING = 0x1,
4268	MLX5_DCTC_STATE_DRAINED = 0x2,
4269	};
4270
4271	enum {
4272	MLX5_DCTC_CS_RES_DISABLE = 0x0,
4273	MLX5_DCTC_CS_RES_NA = 0x1,
4274	MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4275	};
4276
4277	enum {
4278	MLX5_DCTC_MTU_256_BYTES = 0x1,
4279	MLX5_DCTC_MTU_512_BYTES = 0x2,
4280	MLX5_DCTC_MTU_1K_BYTES = 0x3,
4281	MLX5_DCTC_MTU_2K_BYTES = 0x4,
4282	MLX5_DCTC_MTU_4K_BYTES = 0x5,
4283	};
4284
4285	struct mlx5_ifc_dctc_bits {
4286	u8 reserved_at_0[0x4];
4287	u8 state[0x4];
4288	u8 reserved_at_8[0x18];
4289
4290	u8 reserved_at_20[0x8];
4291	u8 user_index[0x18];
4292
4293	u8 reserved_at_40[0x8];
4294	u8 cqn[0x18];
4295
4296	u8 counter_set_id[0x8];
4297	u8 atomic_mode[0x4];
4298	u8 rre[0x1];
4299	u8 rwe[0x1];
4300	u8 rae[0x1];
4301	u8 atomic_like_write_en[0x1];
4302	u8 latency_sensitive[0x1];
4303	u8 rlky[0x1];
4304	u8 free_ar[0x1];
4305	u8 reserved_at_73[0xd];
4306
4307	u8 reserved_at_80[0x8];
4308	u8 cs_res[0x8];
4309	u8 reserved_at_90[0x3];
4310	u8 min_rnr_nak[0x5];
4311	u8 reserved_at_98[0x8];
4312
4313	u8 reserved_at_a0[0x8];
4314	u8 srqn_xrqn[0x18];
4315
4316	u8 reserved_at_c0[0x8];
4317	u8 pd[0x18];
4318
4319	u8 tclass[0x8];
4320	u8 reserved_at_e8[0x4];
4321	u8 flow_label[0x14];
4322
4323	u8 dc_access_key[0x40];
4324
4325	u8 reserved_at_140[0x5];
4326	u8 mtu[0x3];
4327	u8 port[0x8];
4328	u8 pkey_index[0x10];
4329
4330	u8 reserved_at_160[0x8];
4331	u8 my_addr_index[0x8];
4332	u8 reserved_at_170[0x8];
4333	u8 hop_limit[0x8];
4334
4335	u8 dc_access_key_violation_count[0x20];
4336
4337	u8 reserved_at_1a0[0x14];
4338	u8 dei_cfi[0x1];
4339	u8 eth_prio[0x3];
4340	u8 ecn[0x2];
4341	u8 dscp[0x6];
4342
4343	u8 reserved_at_1c0[0x20];
4344	u8 ece[0x20];
4345	};
4346
4347	enum {
4348	MLX5_CQC_STATUS_OK = 0x0,
4349	MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4350	MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4351	};
4352
4353	enum {
4354	MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4355	MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4356	};
4357
4358	enum {
4359	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4360	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4361	MLX5_CQC_ST_FIRED = 0xa,
4362	};
4363
4364	enum {
4365	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4366	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4367	MLX5_CQ_PERIOD_NUM_MODES
4368	};
4369
4370	struct mlx5_ifc_cqc_bits {
4371	u8 status[0x4];
4372	u8 reserved_at_4[0x2];
4373	u8 dbr_umem_valid[0x1];
4374	u8 apu_cq[0x1];
4375	u8 cqe_sz[0x3];
4376	u8 cc[0x1];
4377	u8 reserved_at_c[0x1];
4378	u8 scqe_break_moderation_en[0x1];
4379	u8 oi[0x1];
4380	u8 cq_period_mode[0x2];
4381	u8 cqe_comp_en[0x1];
4382	u8 mini_cqe_res_format[0x2];
4383	u8 st[0x4];
4384	u8 reserved_at_18[0x6];
4385	u8 cqe_compression_layout[0x2];
4386
4387	u8 reserved_at_20[0x20];
4388
4389	u8 reserved_at_40[0x14];
4390	u8 page_offset[0x6];
4391	u8 reserved_at_5a[0x6];
4392
4393	u8 reserved_at_60[0x3];
4394	u8 log_cq_size[0x5];
4395	u8 uar_page[0x18];
4396
4397	u8 reserved_at_80[0x4];
4398	u8 cq_period[0xc];
4399	u8 cq_max_count[0x10];
4400
4401	u8 c_eqn_or_apu_element[0x20];
4402
4403	u8 reserved_at_c0[0x3];
4404	u8 log_page_size[0x5];
4405	u8 reserved_at_c8[0x18];
4406
4407	u8 reserved_at_e0[0x20];
4408
4409	u8 reserved_at_100[0x8];
4410	u8 last_notified_index[0x18];
4411
4412	u8 reserved_at_120[0x8];
4413	u8 last_solicit_index[0x18];
4414
4415	u8 reserved_at_140[0x8];
4416	u8 consumer_counter[0x18];
4417
4418	u8 reserved_at_160[0x8];
4419	u8 producer_counter[0x18];
4420
4421	u8 reserved_at_180[0x40];
4422
4423	u8 dbr_addr[0x40];
4424	};
4425
4426	union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4427	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4428	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4429	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4430	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4431	u8 reserved_at_0[0x800];
4432	};
4433
4434	struct mlx5_ifc_query_adapter_param_block_bits {
4435	u8 reserved_at_0[0xc0];
4436
4437	u8 reserved_at_c0[0x8];
4438	u8 ieee_vendor_id[0x18];
4439
4440	u8 reserved_at_e0[0x10];
4441	u8 vsd_vendor_id[0x10];
4442
4443	u8 vsd[208][0x8];
4444
4445	u8 vsd_contd_psid[16][0x8];
4446	};
4447
4448	enum {
4449	MLX5_XRQC_STATE_GOOD = 0x0,
4450	MLX5_XRQC_STATE_ERROR = 0x1,
4451	};
4452
4453	enum {
4454	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4455	MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4456	};
4457
4458	enum {
4459	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4460	};
4461
4462	struct mlx5_ifc_tag_matching_topology_context_bits {
4463	u8 log_matching_list_sz[0x4];
4464	u8 reserved_at_4[0xc];
4465	u8 append_next_index[0x10];
4466
4467	u8 sw_phase_cnt[0x10];
4468	u8 hw_phase_cnt[0x10];
4469
4470	u8 reserved_at_40[0x40];
4471	};
4472
4473	struct mlx5_ifc_xrqc_bits {
4474	u8 state[0x4];
4475	u8 rlkey[0x1];
4476	u8 reserved_at_5[0xf];
4477	u8 topology[0x4];
4478	u8 reserved_at_18[0x4];
4479	u8 offload[0x4];
4480
4481	u8 reserved_at_20[0x8];
4482	u8 user_index[0x18];
4483
4484	u8 reserved_at_40[0x8];
4485	u8 cqn[0x18];
4486
4487	u8 reserved_at_60[0xa0];
4488
4489	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4490
4491	u8 reserved_at_180[0x280];
4492
4493	struct mlx5_ifc_wq_bits wq;
4494	};
4495
4496	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4497	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4498	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4499	u8 reserved_at_0[0x20];
4500	};
4501
4502	union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4503	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4504	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4505	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4506	u8 reserved_at_0[0x20];
4507	};
4508
4509	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4510	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4511	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4512	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4513	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4514	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4515	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4516	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4517	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4518	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4519	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4520	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4521	u8 reserved_at_0[0x7c0];
4522	};
4523
4524	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4525	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4526	u8 reserved_at_0[0x7c0];
4527	};
4528
4529	union mlx5_ifc_event_auto_bits {
4530	struct mlx5_ifc_comp_event_bits comp_event;
4531	struct mlx5_ifc_dct_events_bits dct_events;
4532	struct mlx5_ifc_qp_events_bits qp_events;
4533	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4534	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4535	struct mlx5_ifc_cq_error_bits cq_error;
4536	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4537	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4538	struct mlx5_ifc_gpio_event_bits gpio_event;
4539	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4540	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4541	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4542	u8 reserved_at_0[0xe0];
4543	};
4544
4545	struct mlx5_ifc_health_buffer_bits {
4546	u8 reserved_at_0[0x100];
4547
4548	u8 assert_existptr[0x20];
4549
4550	u8 assert_callra[0x20];
4551
4552	u8 reserved_at_140[0x20];
4553
4554	u8 time[0x20];
4555
4556	u8 fw_version[0x20];
4557
4558	u8 hw_id[0x20];
4559
4560	u8 rfr[0x1];
4561	u8 reserved_at_1c1[0x3];
4562	u8 valid[0x1];
4563	u8 severity[0x3];
4564	u8 reserved_at_1c8[0x18];
4565
4566	u8 irisc_index[0x8];
4567	u8 synd[0x8];
4568	u8 ext_synd[0x10];
4569	};
4570
4571	struct mlx5_ifc_register_loopback_control_bits {
4572	u8 no_lb[0x1];
4573	u8 reserved_at_1[0x7];
4574	u8 port[0x8];
4575	u8 reserved_at_10[0x10];
4576
4577	u8 reserved_at_20[0x60];
4578	};
4579
4580	struct mlx5_ifc_vport_tc_element_bits {
4581	u8 traffic_class[0x4];
4582	u8 reserved_at_4[0xc];
4583	u8 vport_number[0x10];
4584	};
4585
4586	struct mlx5_ifc_vport_element_bits {
4587	u8 reserved_at_0[0x10];
4588	u8 vport_number[0x10];
4589	};
4590
4591	enum {
4592	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4593	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4594	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4595	};
4596
4597	struct mlx5_ifc_tsar_element_bits {
4598	u8 reserved_at_0[0x8];
4599	u8 tsar_type[0x8];
4600	u8 reserved_at_10[0x10];
4601	};
4602
4603	enum {
4604	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4605	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4606	};
4607
4608	struct mlx5_ifc_teardown_hca_out_bits {
4609	u8 status[0x8];
4610	u8 reserved_at_8[0x18];
4611
4612	u8 syndrome[0x20];
4613
4614	u8 reserved_at_40[0x3f];
4615
4616	u8 state[0x1];
4617	};
4618
4619	enum {
4620	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4621	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4622	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4623	};
4624
4625	struct mlx5_ifc_teardown_hca_in_bits {
4626	u8 opcode[0x10];
4627	u8 reserved_at_10[0x10];
4628
4629	u8 reserved_at_20[0x10];
4630	u8 op_mod[0x10];
4631
4632	u8 reserved_at_40[0x10];
4633	u8 profile[0x10];
4634
4635	u8 reserved_at_60[0x20];
4636	};
4637
4638	struct mlx5_ifc_sqerr2rts_qp_out_bits {
4639	u8 status[0x8];
4640	u8 reserved_at_8[0x18];
4641
4642	u8 syndrome[0x20];
4643
4644	u8 reserved_at_40[0x40];
4645	};
4646
4647	struct mlx5_ifc_sqerr2rts_qp_in_bits {
4648	u8 opcode[0x10];
4649	u8 uid[0x10];
4650
4651	u8 reserved_at_20[0x10];
4652	u8 op_mod[0x10];
4653
4654	u8 reserved_at_40[0x8];
4655	u8 qpn[0x18];
4656
4657	u8 reserved_at_60[0x20];
4658
4659	u8 opt_param_mask[0x20];
4660
4661	u8 reserved_at_a0[0x20];
4662
4663	struct mlx5_ifc_qpc_bits qpc;
4664
4665	u8 reserved_at_800[0x80];
4666	};
4667
4668	struct mlx5_ifc_sqd2rts_qp_out_bits {
4669	u8 status[0x8];
4670	u8 reserved_at_8[0x18];
4671
4672	u8 syndrome[0x20];
4673
4674	u8 reserved_at_40[0x40];
4675	};
4676
4677	struct mlx5_ifc_sqd2rts_qp_in_bits {
4678	u8 opcode[0x10];
4679	u8 uid[0x10];
4680
4681	u8 reserved_at_20[0x10];
4682	u8 op_mod[0x10];
4683
4684	u8 reserved_at_40[0x8];
4685	u8 qpn[0x18];
4686
4687	u8 reserved_at_60[0x20];
4688
4689	u8 opt_param_mask[0x20];
4690
4691	u8 reserved_at_a0[0x20];
4692
4693	struct mlx5_ifc_qpc_bits qpc;
4694
4695	u8 reserved_at_800[0x80];
4696	};
4697
4698	struct mlx5_ifc_set_roce_address_out_bits {
4699	u8 status[0x8];
4700	u8 reserved_at_8[0x18];
4701
4702	u8 syndrome[0x20];
4703
4704	u8 reserved_at_40[0x40];
4705	};
4706
4707	struct mlx5_ifc_set_roce_address_in_bits {
4708	u8 opcode[0x10];
4709	u8 reserved_at_10[0x10];
4710
4711	u8 reserved_at_20[0x10];
4712	u8 op_mod[0x10];
4713
4714	u8 roce_address_index[0x10];
4715	u8 reserved_at_50[0xc];
4716	u8 vhca_port_num[0x4];
4717
4718	u8 reserved_at_60[0x20];
4719
4720	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4721	};
4722
4723	struct mlx5_ifc_set_mad_demux_out_bits {
4724	u8 status[0x8];
4725	u8 reserved_at_8[0x18];
4726
4727	u8 syndrome[0x20];
4728
4729	u8 reserved_at_40[0x40];
4730	};
4731
4732	enum {
4733	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4734	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4735	};
4736
4737	struct mlx5_ifc_set_mad_demux_in_bits {
4738	u8 opcode[0x10];
4739	u8 reserved_at_10[0x10];
4740
4741	u8 reserved_at_20[0x10];
4742	u8 op_mod[0x10];
4743
4744	u8 reserved_at_40[0x20];
4745
4746	u8 reserved_at_60[0x6];
4747	u8 demux_mode[0x2];
4748	u8 reserved_at_68[0x18];
4749	};
4750
4751	struct mlx5_ifc_set_l2_table_entry_out_bits {
4752	u8 status[0x8];
4753	u8 reserved_at_8[0x18];
4754
4755	u8 syndrome[0x20];
4756
4757	u8 reserved_at_40[0x40];
4758	};
4759
4760	struct mlx5_ifc_set_l2_table_entry_in_bits {
4761	u8 opcode[0x10];
4762	u8 reserved_at_10[0x10];
4763
4764	u8 reserved_at_20[0x10];
4765	u8 op_mod[0x10];
4766
4767	u8 reserved_at_40[0x60];
4768
4769	u8 reserved_at_a0[0x8];
4770	u8 table_index[0x18];
4771
4772	u8 reserved_at_c0[0x20];
4773
4774	u8 reserved_at_e0[0x10];
4775	u8 silent_mode_valid[0x1];
4776	u8 silent_mode[0x1];
4777	u8 reserved_at_f2[0x1];
4778	u8 vlan_valid[0x1];
4779	u8 vlan[0xc];
4780
4781	struct mlx5_ifc_mac_address_layout_bits mac_address;
4782
4783	u8 reserved_at_140[0xc0];
4784	};
4785
4786	struct mlx5_ifc_set_issi_out_bits {
4787	u8 status[0x8];
4788	u8 reserved_at_8[0x18];
4789
4790	u8 syndrome[0x20];
4791
4792	u8 reserved_at_40[0x40];
4793	};
4794
4795	struct mlx5_ifc_set_issi_in_bits {
4796	u8 opcode[0x10];
4797	u8 reserved_at_10[0x10];
4798
4799	u8 reserved_at_20[0x10];
4800	u8 op_mod[0x10];
4801
4802	u8 reserved_at_40[0x10];
4803	u8 current_issi[0x10];
4804
4805	u8 reserved_at_60[0x20];
4806	};
4807
4808	struct mlx5_ifc_set_hca_cap_out_bits {
4809	u8 status[0x8];
4810	u8 reserved_at_8[0x18];
4811
4812	u8 syndrome[0x20];
4813
4814	u8 reserved_at_40[0x40];
4815	};
4816
4817	struct mlx5_ifc_set_hca_cap_in_bits {
4818	u8 opcode[0x10];
4819	u8 reserved_at_10[0x10];
4820
4821	u8 reserved_at_20[0x10];
4822	u8 op_mod[0x10];
4823
4824	u8 other_function[0x1];
4825	u8 ec_vf_function[0x1];
4826	u8 reserved_at_42[0xe];
4827	u8 function_id[0x10];
4828
4829	u8 reserved_at_60[0x20];
4830
4831	union mlx5_ifc_hca_cap_union_bits capability;
4832	};
4833
4834	enum {
4835	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4836	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4837	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4838	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4839	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4840	};
4841
4842	struct mlx5_ifc_set_fte_out_bits {
4843	u8 status[0x8];
4844	u8 reserved_at_8[0x18];
4845
4846	u8 syndrome[0x20];
4847
4848	u8 reserved_at_40[0x40];
4849	};
4850
4851	struct mlx5_ifc_set_fte_in_bits {
4852	u8 opcode[0x10];
4853	u8 reserved_at_10[0x10];
4854
4855	u8 reserved_at_20[0x10];
4856	u8 op_mod[0x10];
4857
4858	u8 other_vport[0x1];
4859	u8 reserved_at_41[0xf];
4860	u8 vport_number[0x10];
4861
4862	u8 reserved_at_60[0x20];
4863
4864	u8 table_type[0x8];
4865	u8 reserved_at_88[0x18];
4866
4867	u8 reserved_at_a0[0x8];
4868	u8 table_id[0x18];
4869
4870	u8 ignore_flow_level[0x1];
4871	u8 reserved_at_c1[0x17];
4872	u8 modify_enable_mask[0x8];
4873
4874	u8 reserved_at_e0[0x20];
4875
4876	u8 flow_index[0x20];
4877
4878	u8 reserved_at_120[0xe0];
4879
4880	struct mlx5_ifc_flow_context_bits flow_context;
4881	};
4882
4883	struct mlx5_ifc_rts2rts_qp_out_bits {
4884	u8 status[0x8];
4885	u8 reserved_at_8[0x18];
4886
4887	u8 syndrome[0x20];
4888
4889	u8 reserved_at_40[0x20];
4890	u8 ece[0x20];
4891	};
4892
4893	struct mlx5_ifc_rts2rts_qp_in_bits {
4894	u8 opcode[0x10];
4895	u8 uid[0x10];
4896
4897	u8 reserved_at_20[0x10];
4898	u8 op_mod[0x10];
4899
4900	u8 reserved_at_40[0x8];
4901	u8 qpn[0x18];
4902
4903	u8 reserved_at_60[0x20];
4904
4905	u8 opt_param_mask[0x20];
4906
4907	u8 ece[0x20];
4908
4909	struct mlx5_ifc_qpc_bits qpc;
4910
4911	u8 reserved_at_800[0x80];
4912	};
4913
4914	struct mlx5_ifc_rtr2rts_qp_out_bits {
4915	u8 status[0x8];
4916	u8 reserved_at_8[0x18];
4917
4918	u8 syndrome[0x20];
4919
4920	u8 reserved_at_40[0x20];
4921	u8 ece[0x20];
4922	};
4923
4924	struct mlx5_ifc_rtr2rts_qp_in_bits {
4925	u8 opcode[0x10];
4926	u8 uid[0x10];
4927
4928	u8 reserved_at_20[0x10];
4929	u8 op_mod[0x10];
4930
4931	u8 reserved_at_40[0x8];
4932	u8 qpn[0x18];
4933
4934	u8 reserved_at_60[0x20];
4935
4936	u8 opt_param_mask[0x20];
4937
4938	u8 ece[0x20];
4939
4940	struct mlx5_ifc_qpc_bits qpc;
4941
4942	u8 reserved_at_800[0x80];
4943	};
4944
4945	struct mlx5_ifc_rst2init_qp_out_bits {
4946	u8 status[0x8];
4947	u8 reserved_at_8[0x18];
4948
4949	u8 syndrome[0x20];
4950
4951	u8 reserved_at_40[0x20];
4952	u8 ece[0x20];
4953	};
4954
4955	struct mlx5_ifc_rst2init_qp_in_bits {
4956	u8 opcode[0x10];
4957	u8 uid[0x10];
4958
4959	u8 reserved_at_20[0x10];
4960	u8 op_mod[0x10];
4961
4962	u8 reserved_at_40[0x8];
4963	u8 qpn[0x18];
4964
4965	u8 reserved_at_60[0x20];
4966
4967	u8 opt_param_mask[0x20];
4968
4969	u8 ece[0x20];
4970
4971	struct mlx5_ifc_qpc_bits qpc;
4972
4973	u8 reserved_at_800[0x80];
4974	};
4975
4976	struct mlx5_ifc_query_xrq_out_bits {
4977	u8 status[0x8];
4978	u8 reserved_at_8[0x18];
4979
4980	u8 syndrome[0x20];
4981
4982	u8 reserved_at_40[0x40];
4983
4984	struct mlx5_ifc_xrqc_bits xrq_context;
4985	};
4986
4987	struct mlx5_ifc_query_xrq_in_bits {
4988	u8 opcode[0x10];
4989	u8 reserved_at_10[0x10];
4990
4991	u8 reserved_at_20[0x10];
4992	u8 op_mod[0x10];
4993
4994	u8 reserved_at_40[0x8];
4995	u8 xrqn[0x18];
4996
4997	u8 reserved_at_60[0x20];
4998	};
4999
5000	struct mlx5_ifc_query_xrc_srq_out_bits {
5001	u8 status[0x8];
5002	u8 reserved_at_8[0x18];
5003
5004	u8 syndrome[0x20];
5005
5006	u8 reserved_at_40[0x40];
5007
5008	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5009
5010	u8 reserved_at_280[0x600];
5011
5012	u8 pas[][0x40];
5013	};
5014
5015	struct mlx5_ifc_query_xrc_srq_in_bits {
5016	u8 opcode[0x10];
5017	u8 reserved_at_10[0x10];
5018
5019	u8 reserved_at_20[0x10];
5020	u8 op_mod[0x10];
5021
5022	u8 reserved_at_40[0x8];
5023	u8 xrc_srqn[0x18];
5024
5025	u8 reserved_at_60[0x20];
5026	};
5027
5028	enum {
5029	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
5030	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
5031	};
5032
5033	struct mlx5_ifc_query_vport_state_out_bits {
5034	u8 status[0x8];
5035	u8 reserved_at_8[0x18];
5036
5037	u8 syndrome[0x20];
5038
5039	u8 reserved_at_40[0x20];
5040
5041	u8 reserved_at_60[0x18];
5042	u8 admin_state[0x4];
5043	u8 state[0x4];
5044	};
5045
5046	enum {
5047	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
5048	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
5049	MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
5050	};
5051
5052	struct mlx5_ifc_arm_monitor_counter_in_bits {
5053	u8 opcode[0x10];
5054	u8 uid[0x10];
5055
5056	u8 reserved_at_20[0x10];
5057	u8 op_mod[0x10];
5058
5059	u8 reserved_at_40[0x20];
5060
5061	u8 reserved_at_60[0x20];
5062	};
5063
5064	struct mlx5_ifc_arm_monitor_counter_out_bits {
5065	u8 status[0x8];
5066	u8 reserved_at_8[0x18];
5067
5068	u8 syndrome[0x20];
5069
5070	u8 reserved_at_40[0x40];
5071	};
5072
5073	enum {
5074	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
5075	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5076	};
5077
5078	enum mlx5_monitor_counter_ppcnt {
5079	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
5080	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
5081	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
5082	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5083	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
5084	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
5085	};
5086
5087	enum {
5088	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
5089	};
5090
5091	struct mlx5_ifc_monitor_counter_output_bits {
5092	u8 reserved_at_0[0x4];
5093	u8 type[0x4];
5094	u8 reserved_at_8[0x8];
5095	u8 counter[0x10];
5096
5097	u8 counter_group_id[0x20];
5098	};
5099
5100	#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5101	#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
5102	#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5103	MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5104
5105	struct mlx5_ifc_set_monitor_counter_in_bits {
5106	u8 opcode[0x10];
5107	u8 uid[0x10];
5108
5109	u8 reserved_at_20[0x10];
5110	u8 op_mod[0x10];
5111
5112	u8 reserved_at_40[0x10];
5113	u8 num_of_counters[0x10];
5114
5115	u8 reserved_at_60[0x20];
5116
5117	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5118	};
5119
5120	struct mlx5_ifc_set_monitor_counter_out_bits {
5121	u8 status[0x8];
5122	u8 reserved_at_8[0x18];
5123
5124	u8 syndrome[0x20];
5125
5126	u8 reserved_at_40[0x40];
5127	};
5128
5129	struct mlx5_ifc_query_vport_state_in_bits {
5130	u8 opcode[0x10];
5131	u8 reserved_at_10[0x10];
5132
5133	u8 reserved_at_20[0x10];
5134	u8 op_mod[0x10];
5135
5136	u8 other_vport[0x1];
5137	u8 reserved_at_41[0xf];
5138	u8 vport_number[0x10];
5139
5140	u8 reserved_at_60[0x20];
5141	};
5142
5143	struct mlx5_ifc_query_vnic_env_out_bits {
5144	u8 status[0x8];
5145	u8 reserved_at_8[0x18];
5146
5147	u8 syndrome[0x20];
5148
5149	u8 reserved_at_40[0x40];
5150
5151	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5152	};
5153
5154	enum {
5155	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
5156	};
5157
5158	struct mlx5_ifc_query_vnic_env_in_bits {
5159	u8 opcode[0x10];
5160	u8 reserved_at_10[0x10];
5161
5162	u8 reserved_at_20[0x10];
5163	u8 op_mod[0x10];
5164
5165	u8 other_vport[0x1];
5166	u8 reserved_at_41[0xf];
5167	u8 vport_number[0x10];
5168
5169	u8 reserved_at_60[0x20];
5170	};
5171
5172	struct mlx5_ifc_query_vport_counter_out_bits {
5173	u8 status[0x8];
5174	u8 reserved_at_8[0x18];
5175
5176	u8 syndrome[0x20];
5177
5178	u8 reserved_at_40[0x40];
5179
5180	struct mlx5_ifc_traffic_counter_bits received_errors;
5181
5182	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5183
5184	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5185
5186	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5187
5188	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5189
5190	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5191
5192	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5193
5194	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5195
5196	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5197
5198	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5199
5200	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5201
5202	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5203
5204	struct mlx5_ifc_traffic_counter_bits local_loopback;
5205
5206	u8 reserved_at_700[0x980];
5207	};
5208
5209	enum {
5210	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5211	};
5212
5213	struct mlx5_ifc_query_vport_counter_in_bits {
5214	u8 opcode[0x10];
5215	u8 reserved_at_10[0x10];
5216
5217	u8 reserved_at_20[0x10];
5218	u8 op_mod[0x10];
5219
5220	u8 other_vport[0x1];
5221	u8 reserved_at_41[0xb];
5222	u8 port_num[0x4];
5223	u8 vport_number[0x10];
5224
5225	u8 reserved_at_60[0x60];
5226
5227	u8 clear[0x1];
5228	u8 reserved_at_c1[0x1f];
5229
5230	u8 reserved_at_e0[0x20];
5231	};
5232
5233	struct mlx5_ifc_query_tis_out_bits {
5234	u8 status[0x8];
5235	u8 reserved_at_8[0x18];
5236
5237	u8 syndrome[0x20];
5238
5239	u8 reserved_at_40[0x40];
5240
5241	struct mlx5_ifc_tisc_bits tis_context;
5242	};
5243
5244	struct mlx5_ifc_query_tis_in_bits {
5245	u8 opcode[0x10];
5246	u8 reserved_at_10[0x10];
5247
5248	u8 reserved_at_20[0x10];
5249	u8 op_mod[0x10];
5250
5251	u8 reserved_at_40[0x8];
5252	u8 tisn[0x18];
5253
5254	u8 reserved_at_60[0x20];
5255	};
5256
5257	struct mlx5_ifc_query_tir_out_bits {
5258	u8 status[0x8];
5259	u8 reserved_at_8[0x18];
5260
5261	u8 syndrome[0x20];
5262
5263	u8 reserved_at_40[0xc0];
5264
5265	struct mlx5_ifc_tirc_bits tir_context;
5266	};
5267
5268	struct mlx5_ifc_query_tir_in_bits {
5269	u8 opcode[0x10];
5270	u8 reserved_at_10[0x10];
5271
5272	u8 reserved_at_20[0x10];
5273	u8 op_mod[0x10];
5274
5275	u8 reserved_at_40[0x8];
5276	u8 tirn[0x18];
5277
5278	u8 reserved_at_60[0x20];
5279	};
5280
5281	struct mlx5_ifc_query_srq_out_bits {
5282	u8 status[0x8];
5283	u8 reserved_at_8[0x18];
5284
5285	u8 syndrome[0x20];
5286
5287	u8 reserved_at_40[0x40];
5288
5289	struct mlx5_ifc_srqc_bits srq_context_entry;
5290
5291	u8 reserved_at_280[0x600];
5292
5293	u8 pas[][0x40];
5294	};
5295
5296	struct mlx5_ifc_query_srq_in_bits {
5297	u8 opcode[0x10];
5298	u8 reserved_at_10[0x10];
5299
5300	u8 reserved_at_20[0x10];
5301	u8 op_mod[0x10];
5302
5303	u8 reserved_at_40[0x8];
5304	u8 srqn[0x18];
5305
5306	u8 reserved_at_60[0x20];
5307	};
5308
5309	struct mlx5_ifc_query_sq_out_bits {
5310	u8 status[0x8];
5311	u8 reserved_at_8[0x18];
5312
5313	u8 syndrome[0x20];
5314
5315	u8 reserved_at_40[0xc0];
5316
5317	struct mlx5_ifc_sqc_bits sq_context;
5318	};
5319
5320	struct mlx5_ifc_query_sq_in_bits {
5321	u8 opcode[0x10];
5322	u8 reserved_at_10[0x10];
5323
5324	u8 reserved_at_20[0x10];
5325	u8 op_mod[0x10];
5326
5327	u8 reserved_at_40[0x8];
5328	u8 sqn[0x18];
5329
5330	u8 reserved_at_60[0x20];
5331	};
5332
5333	struct mlx5_ifc_query_special_contexts_out_bits {
5334	u8 status[0x8];
5335	u8 reserved_at_8[0x18];
5336
5337	u8 syndrome[0x20];
5338
5339	u8 dump_fill_mkey[0x20];
5340
5341	u8 resd_lkey[0x20];
5342
5343	u8 null_mkey[0x20];
5344
5345	u8 terminate_scatter_list_mkey[0x20];
5346
5347	u8 repeated_mkey[0x20];
5348
5349	u8 reserved_at_a0[0x20];
5350	};
5351
5352	struct mlx5_ifc_query_special_contexts_in_bits {
5353	u8 opcode[0x10];
5354	u8 reserved_at_10[0x10];
5355
5356	u8 reserved_at_20[0x10];
5357	u8 op_mod[0x10];
5358
5359	u8 reserved_at_40[0x40];
5360	};
5361
5362	struct mlx5_ifc_query_scheduling_element_out_bits {
5363	u8 opcode[0x10];
5364	u8 reserved_at_10[0x10];
5365
5366	u8 reserved_at_20[0x10];
5367	u8 op_mod[0x10];
5368
5369	u8 reserved_at_40[0xc0];
5370
5371	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5372
5373	u8 reserved_at_300[0x100];
5374	};
5375
5376	enum {
5377	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5378	SCHEDULING_HIERARCHY_NIC = 0x3,
5379	};
5380
5381	struct mlx5_ifc_query_scheduling_element_in_bits {
5382	u8 opcode[0x10];
5383	u8 reserved_at_10[0x10];
5384
5385	u8 reserved_at_20[0x10];
5386	u8 op_mod[0x10];
5387
5388	u8 scheduling_hierarchy[0x8];
5389	u8 reserved_at_48[0x18];
5390
5391	u8 scheduling_element_id[0x20];
5392
5393	u8 reserved_at_80[0x180];
5394	};
5395
5396	struct mlx5_ifc_query_rqt_out_bits {
5397	u8 status[0x8];
5398	u8 reserved_at_8[0x18];
5399
5400	u8 syndrome[0x20];
5401
5402	u8 reserved_at_40[0xc0];
5403
5404	struct mlx5_ifc_rqtc_bits rqt_context;
5405	};
5406
5407	struct mlx5_ifc_query_rqt_in_bits {
5408	u8 opcode[0x10];
5409	u8 reserved_at_10[0x10];
5410
5411	u8 reserved_at_20[0x10];
5412	u8 op_mod[0x10];
5413
5414	u8 reserved_at_40[0x8];
5415	u8 rqtn[0x18];
5416
5417	u8 reserved_at_60[0x20];
5418	};
5419
5420	struct mlx5_ifc_query_rq_out_bits {
5421	u8 status[0x8];
5422	u8 reserved_at_8[0x18];
5423
5424	u8 syndrome[0x20];
5425
5426	u8 reserved_at_40[0xc0];
5427
5428	struct mlx5_ifc_rqc_bits rq_context;
5429	};
5430
5431	struct mlx5_ifc_query_rq_in_bits {
5432	u8 opcode[0x10];
5433	u8 reserved_at_10[0x10];
5434
5435	u8 reserved_at_20[0x10];
5436	u8 op_mod[0x10];
5437
5438	u8 reserved_at_40[0x8];
5439	u8 rqn[0x18];
5440
5441	u8 reserved_at_60[0x20];
5442	};
5443
5444	struct mlx5_ifc_query_roce_address_out_bits {
5445	u8 status[0x8];
5446	u8 reserved_at_8[0x18];
5447
5448	u8 syndrome[0x20];
5449
5450	u8 reserved_at_40[0x40];
5451
5452	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5453	};
5454
5455	struct mlx5_ifc_query_roce_address_in_bits {
5456	u8 opcode[0x10];
5457	u8 reserved_at_10[0x10];
5458
5459	u8 reserved_at_20[0x10];
5460	u8 op_mod[0x10];
5461
5462	u8 roce_address_index[0x10];
5463	u8 reserved_at_50[0xc];
5464	u8 vhca_port_num[0x4];
5465
5466	u8 reserved_at_60[0x20];
5467	};
5468
5469	struct mlx5_ifc_query_rmp_out_bits {
5470	u8 status[0x8];
5471	u8 reserved_at_8[0x18];
5472
5473	u8 syndrome[0x20];
5474
5475	u8 reserved_at_40[0xc0];
5476
5477	struct mlx5_ifc_rmpc_bits rmp_context;
5478	};
5479
5480	struct mlx5_ifc_query_rmp_in_bits {
5481	u8 opcode[0x10];
5482	u8 reserved_at_10[0x10];
5483
5484	u8 reserved_at_20[0x10];
5485	u8 op_mod[0x10];
5486
5487	u8 reserved_at_40[0x8];
5488	u8 rmpn[0x18];
5489
5490	u8 reserved_at_60[0x20];
5491	};
5492
5493	struct mlx5_ifc_cqe_error_syndrome_bits {
5494	u8 hw_error_syndrome[0x8];
5495	u8 hw_syndrome_type[0x4];
5496	u8 reserved_at_c[0x4];
5497	u8 vendor_error_syndrome[0x8];
5498	u8 syndrome[0x8];
5499	};
5500
5501	struct mlx5_ifc_qp_context_extension_bits {
5502	u8 reserved_at_0[0x60];
5503
5504	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5505
5506	u8 reserved_at_80[0x580];
5507	};
5508
5509	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5510	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5511
5512	u8 pas[0][0x40];
5513	};
5514
5515	struct mlx5_ifc_qp_pas_list_in_bits {
5516	struct mlx5_ifc_cmd_pas_bits pas[0];
5517	};
5518
5519	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5520	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5521	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5522	};
5523
5524	struct mlx5_ifc_query_qp_out_bits {
5525	u8 status[0x8];
5526	u8 reserved_at_8[0x18];
5527
5528	u8 syndrome[0x20];
5529
5530	u8 reserved_at_40[0x40];
5531
5532	u8 opt_param_mask[0x20];
5533
5534	u8 ece[0x20];
5535
5536	struct mlx5_ifc_qpc_bits qpc;
5537
5538	u8 reserved_at_800[0x80];
5539
5540	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5541	};
5542
5543	struct mlx5_ifc_query_qp_in_bits {
5544	u8 opcode[0x10];
5545	u8 reserved_at_10[0x10];
5546
5547	u8 reserved_at_20[0x10];
5548	u8 op_mod[0x10];
5549
5550	u8 qpc_ext[0x1];
5551	u8 reserved_at_41[0x7];
5552	u8 qpn[0x18];
5553
5554	u8 reserved_at_60[0x20];
5555	};
5556
5557	struct mlx5_ifc_query_q_counter_out_bits {
5558	u8 status[0x8];
5559	u8 reserved_at_8[0x18];
5560
5561	u8 syndrome[0x20];
5562
5563	u8 reserved_at_40[0x40];
5564
5565	u8 rx_write_requests[0x20];
5566
5567	u8 reserved_at_a0[0x20];
5568
5569	u8 rx_read_requests[0x20];
5570
5571	u8 reserved_at_e0[0x20];
5572
5573	u8 rx_atomic_requests[0x20];
5574
5575	u8 reserved_at_120[0x20];
5576
5577	u8 rx_dct_connect[0x20];
5578
5579	u8 reserved_at_160[0x20];
5580
5581	u8 out_of_buffer[0x20];
5582
5583	u8 reserved_at_1a0[0x20];
5584
5585	u8 out_of_sequence[0x20];
5586
5587	u8 reserved_at_1e0[0x20];
5588
5589	u8 duplicate_request[0x20];
5590
5591	u8 reserved_at_220[0x20];
5592
5593	u8 rnr_nak_retry_err[0x20];
5594
5595	u8 reserved_at_260[0x20];
5596
5597	u8 packet_seq_err[0x20];
5598
5599	u8 reserved_at_2a0[0x20];
5600
5601	u8 implied_nak_seq_err[0x20];
5602
5603	u8 reserved_at_2e0[0x20];
5604
5605	u8 local_ack_timeout_err[0x20];
5606
5607	u8 reserved_at_320[0xa0];
5608
5609	u8 resp_local_length_error[0x20];
5610
5611	u8 req_local_length_error[0x20];
5612
5613	u8 resp_local_qp_error[0x20];
5614
5615	u8 local_operation_error[0x20];
5616
5617	u8 resp_local_protection[0x20];
5618
5619	u8 req_local_protection[0x20];
5620
5621	u8 resp_cqe_error[0x20];
5622
5623	u8 req_cqe_error[0x20];
5624
5625	u8 req_mw_binding[0x20];
5626
5627	u8 req_bad_response[0x20];
5628
5629	u8 req_remote_invalid_request[0x20];
5630
5631	u8 resp_remote_invalid_request[0x20];
5632
5633	u8 req_remote_access_errors[0x20];
5634
5635	u8 resp_remote_access_errors[0x20];
5636
5637	u8 req_remote_operation_errors[0x20];
5638
5639	u8 req_transport_retries_exceeded[0x20];
5640
5641	u8 cq_overflow[0x20];
5642
5643	u8 resp_cqe_flush_error[0x20];
5644
5645	u8 req_cqe_flush_error[0x20];
5646
5647	u8 reserved_at_620[0x20];
5648
5649	u8 roce_adp_retrans[0x20];
5650
5651	u8 roce_adp_retrans_to[0x20];
5652
5653	u8 roce_slow_restart[0x20];
5654
5655	u8 roce_slow_restart_cnps[0x20];
5656
5657	u8 roce_slow_restart_trans[0x20];
5658
5659	u8 reserved_at_6e0[0x120];
5660	};
5661
5662	struct mlx5_ifc_query_q_counter_in_bits {
5663	u8 opcode[0x10];
5664	u8 reserved_at_10[0x10];
5665
5666	u8 reserved_at_20[0x10];
5667	u8 op_mod[0x10];
5668
5669	u8 other_vport[0x1];
5670	u8 reserved_at_41[0xf];
5671	u8 vport_number[0x10];
5672
5673	u8 reserved_at_60[0x60];
5674
5675	u8 clear[0x1];
5676	u8 aggregate[0x1];
5677	u8 reserved_at_c2[0x1e];
5678
5679	u8 reserved_at_e0[0x18];
5680	u8 counter_set_id[0x8];
5681	};
5682
5683	struct mlx5_ifc_query_pages_out_bits {
5684	u8 status[0x8];
5685	u8 reserved_at_8[0x18];
5686
5687	u8 syndrome[0x20];
5688
5689	u8 embedded_cpu_function[0x1];
5690	u8 reserved_at_41[0xf];
5691	u8 function_id[0x10];
5692
5693	u8 num_pages[0x20];
5694	};
5695
5696	enum {
5697	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5698	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5699	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5700	};
5701
5702	struct mlx5_ifc_query_pages_in_bits {
5703	u8 opcode[0x10];
5704	u8 reserved_at_10[0x10];
5705
5706	u8 reserved_at_20[0x10];
5707	u8 op_mod[0x10];
5708
5709	u8 embedded_cpu_function[0x1];
5710	u8 reserved_at_41[0xf];
5711	u8 function_id[0x10];
5712
5713	u8 reserved_at_60[0x20];
5714	};
5715
5716	struct mlx5_ifc_query_nic_vport_context_out_bits {
5717	u8 status[0x8];
5718	u8 reserved_at_8[0x18];
5719
5720	u8 syndrome[0x20];
5721
5722	u8 reserved_at_40[0x40];
5723
5724	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5725	};
5726
5727	struct mlx5_ifc_query_nic_vport_context_in_bits {
5728	u8 opcode[0x10];
5729	u8 reserved_at_10[0x10];
5730
5731	u8 reserved_at_20[0x10];
5732	u8 op_mod[0x10];
5733
5734	u8 other_vport[0x1];
5735	u8 reserved_at_41[0xf];
5736	u8 vport_number[0x10];
5737
5738	u8 reserved_at_60[0x5];
5739	u8 allowed_list_type[0x3];
5740	u8 reserved_at_68[0x18];
5741	};
5742
5743	struct mlx5_ifc_query_mkey_out_bits {
5744	u8 status[0x8];
5745	u8 reserved_at_8[0x18];
5746
5747	u8 syndrome[0x20];
5748
5749	u8 reserved_at_40[0x40];
5750
5751	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5752
5753	u8 reserved_at_280[0x600];
5754
5755	u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5756
5757	u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5758	};
5759
5760	struct mlx5_ifc_query_mkey_in_bits {
5761	u8 opcode[0x10];
5762	u8 reserved_at_10[0x10];
5763
5764	u8 reserved_at_20[0x10];
5765	u8 op_mod[0x10];
5766
5767	u8 reserved_at_40[0x8];
5768	u8 mkey_index[0x18];
5769
5770	u8 pg_access[0x1];
5771	u8 reserved_at_61[0x1f];
5772	};
5773
5774	struct mlx5_ifc_query_mad_demux_out_bits {
5775	u8 status[0x8];
5776	u8 reserved_at_8[0x18];
5777
5778	u8 syndrome[0x20];
5779
5780	u8 reserved_at_40[0x40];
5781
5782	u8 mad_dumux_parameters_block[0x20];
5783	};
5784
5785	struct mlx5_ifc_query_mad_demux_in_bits {
5786	u8 opcode[0x10];
5787	u8 reserved_at_10[0x10];
5788
5789	u8 reserved_at_20[0x10];
5790	u8 op_mod[0x10];
5791
5792	u8 reserved_at_40[0x40];
5793	};
5794
5795	struct mlx5_ifc_query_l2_table_entry_out_bits {
5796	u8 status[0x8];
5797	u8 reserved_at_8[0x18];
5798
5799	u8 syndrome[0x20];
5800
5801	u8 reserved_at_40[0xa0];
5802
5803	u8 reserved_at_e0[0x13];
5804	u8 vlan_valid[0x1];
5805	u8 vlan[0xc];
5806
5807	struct mlx5_ifc_mac_address_layout_bits mac_address;
5808
5809	u8 reserved_at_140[0xc0];
5810	};
5811
5812	struct mlx5_ifc_query_l2_table_entry_in_bits {
5813	u8 opcode[0x10];
5814	u8 reserved_at_10[0x10];
5815
5816	u8 reserved_at_20[0x10];
5817	u8 op_mod[0x10];
5818
5819	u8 reserved_at_40[0x60];
5820
5821	u8 reserved_at_a0[0x8];
5822	u8 table_index[0x18];
5823
5824	u8 reserved_at_c0[0x140];
5825	};
5826
5827	struct mlx5_ifc_query_issi_out_bits {
5828	u8 status[0x8];
5829	u8 reserved_at_8[0x18];
5830
5831	u8 syndrome[0x20];
5832
5833	u8 reserved_at_40[0x10];
5834	u8 current_issi[0x10];
5835
5836	u8 reserved_at_60[0xa0];
5837
5838	u8 reserved_at_100[76][0x8];
5839	u8 supported_issi_dw0[0x20];
5840	};
5841
5842	struct mlx5_ifc_query_issi_in_bits {
5843	u8 opcode[0x10];
5844	u8 reserved_at_10[0x10];
5845
5846	u8 reserved_at_20[0x10];
5847	u8 op_mod[0x10];
5848
5849	u8 reserved_at_40[0x40];
5850	};
5851
5852	struct mlx5_ifc_set_driver_version_out_bits {
5853	u8 status[0x8];
5854	u8 reserved_0[0x18];
5855
5856	u8 syndrome[0x20];
5857	u8 reserved_1[0x40];
5858	};
5859
5860	struct mlx5_ifc_set_driver_version_in_bits {
5861	u8 opcode[0x10];
5862	u8 reserved_0[0x10];
5863
5864	u8 reserved_1[0x10];
5865	u8 op_mod[0x10];
5866
5867	u8 reserved_2[0x40];
5868	u8 driver_version[64][0x8];
5869	};
5870
5871	struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5872	u8 status[0x8];
5873	u8 reserved_at_8[0x18];
5874
5875	u8 syndrome[0x20];
5876
5877	u8 reserved_at_40[0x40];
5878
5879	struct mlx5_ifc_pkey_bits pkey[];
5880	};
5881
5882	struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5883	u8 opcode[0x10];
5884	u8 reserved_at_10[0x10];
5885
5886	u8 reserved_at_20[0x10];
5887	u8 op_mod[0x10];
5888
5889	u8 other_vport[0x1];
5890	u8 reserved_at_41[0xb];
5891	u8 port_num[0x4];
5892	u8 vport_number[0x10];
5893
5894	u8 reserved_at_60[0x10];
5895	u8 pkey_index[0x10];
5896	};
5897
5898	enum {
5899	MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5900	MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5901	MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5902	};
5903
5904	struct mlx5_ifc_query_hca_vport_gid_out_bits {
5905	u8 status[0x8];
5906	u8 reserved_at_8[0x18];
5907
5908	u8 syndrome[0x20];
5909
5910	u8 reserved_at_40[0x20];
5911
5912	u8 gids_num[0x10];
5913	u8 reserved_at_70[0x10];
5914
5915	struct mlx5_ifc_array128_auto_bits gid[];
5916	};
5917
5918	struct mlx5_ifc_query_hca_vport_gid_in_bits {
5919	u8 opcode[0x10];
5920	u8 reserved_at_10[0x10];
5921
5922	u8 reserved_at_20[0x10];
5923	u8 op_mod[0x10];
5924
5925	u8 other_vport[0x1];
5926	u8 reserved_at_41[0xb];
5927	u8 port_num[0x4];
5928	u8 vport_number[0x10];
5929
5930	u8 reserved_at_60[0x10];
5931	u8 gid_index[0x10];
5932	};
5933
5934	struct mlx5_ifc_query_hca_vport_context_out_bits {
5935	u8 status[0x8];
5936	u8 reserved_at_8[0x18];
5937
5938	u8 syndrome[0x20];
5939
5940	u8 reserved_at_40[0x40];
5941
5942	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5943	};
5944
5945	struct mlx5_ifc_query_hca_vport_context_in_bits {
5946	u8 opcode[0x10];
5947	u8 reserved_at_10[0x10];
5948
5949	u8 reserved_at_20[0x10];
5950	u8 op_mod[0x10];
5951
5952	u8 other_vport[0x1];
5953	u8 reserved_at_41[0xb];
5954	u8 port_num[0x4];
5955	u8 vport_number[0x10];
5956
5957	u8 reserved_at_60[0x20];
5958	};
5959
5960	struct mlx5_ifc_query_hca_cap_out_bits {
5961	u8 status[0x8];
5962	u8 reserved_at_8[0x18];
5963
5964	u8 syndrome[0x20];
5965
5966	u8 reserved_at_40[0x40];
5967
5968	union mlx5_ifc_hca_cap_union_bits capability;
5969	};
5970
5971	struct mlx5_ifc_query_hca_cap_in_bits {
5972	u8 opcode[0x10];
5973	u8 reserved_at_10[0x10];
5974
5975	u8 reserved_at_20[0x10];
5976	u8 op_mod[0x10];
5977
5978	u8 other_function[0x1];
5979	u8 ec_vf_function[0x1];
5980	u8 reserved_at_42[0xe];
5981	u8 function_id[0x10];
5982
5983	u8 reserved_at_60[0x20];
5984	};
5985
5986	struct mlx5_ifc_other_hca_cap_bits {
5987	u8 roce[0x1];
5988	u8 reserved_at_1[0x27f];
5989	};
5990
5991	struct mlx5_ifc_query_other_hca_cap_out_bits {
5992	u8 status[0x8];
5993	u8 reserved_at_8[0x18];
5994
5995	u8 syndrome[0x20];
5996
5997	u8 reserved_at_40[0x40];
5998
5999	struct mlx5_ifc_other_hca_cap_bits other_capability;
6000	};
6001
6002	struct mlx5_ifc_query_other_hca_cap_in_bits {
6003	u8 opcode[0x10];
6004	u8 reserved_at_10[0x10];
6005
6006	u8 reserved_at_20[0x10];
6007	u8 op_mod[0x10];
6008
6009	u8 reserved_at_40[0x10];
6010	u8 function_id[0x10];
6011
6012	u8 reserved_at_60[0x20];
6013	};
6014
6015	struct mlx5_ifc_modify_other_hca_cap_out_bits {
6016	u8 status[0x8];
6017	u8 reserved_at_8[0x18];
6018
6019	u8 syndrome[0x20];
6020
6021	u8 reserved_at_40[0x40];
6022	};
6023
6024	struct mlx5_ifc_modify_other_hca_cap_in_bits {
6025	u8 opcode[0x10];
6026	u8 reserved_at_10[0x10];
6027
6028	u8 reserved_at_20[0x10];
6029	u8 op_mod[0x10];
6030
6031	u8 reserved_at_40[0x10];
6032	u8 function_id[0x10];
6033	u8 field_select[0x20];
6034
6035	struct mlx5_ifc_other_hca_cap_bits other_capability;
6036	};
6037
6038	struct mlx5_ifc_flow_table_context_bits {
6039	u8 reformat_en[0x1];
6040	u8 decap_en[0x1];
6041	u8 sw_owner[0x1];
6042	u8 termination_table[0x1];
6043	u8 table_miss_action[0x4];
6044	u8 level[0x8];
6045	u8 reserved_at_10[0x8];
6046	u8 log_size[0x8];
6047
6048	u8 reserved_at_20[0x8];
6049	u8 table_miss_id[0x18];
6050
6051	u8 reserved_at_40[0x8];
6052	u8 lag_master_next_table_id[0x18];
6053
6054	u8 reserved_at_60[0x60];
6055
6056	u8 sw_owner_icm_root_1[0x40];
6057
6058	u8 sw_owner_icm_root_0[0x40];
6059
6060	};
6061
6062	struct mlx5_ifc_query_flow_table_out_bits {
6063	u8 status[0x8];
6064	u8 reserved_at_8[0x18];
6065
6066	u8 syndrome[0x20];
6067
6068	u8 reserved_at_40[0x80];
6069
6070	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6071	};
6072
6073	struct mlx5_ifc_query_flow_table_in_bits {
6074	u8 opcode[0x10];
6075	u8 reserved_at_10[0x10];
6076
6077	u8 reserved_at_20[0x10];
6078	u8 op_mod[0x10];
6079
6080	u8 reserved_at_40[0x40];
6081
6082	u8 table_type[0x8];
6083	u8 reserved_at_88[0x18];
6084
6085	u8 reserved_at_a0[0x8];
6086	u8 table_id[0x18];
6087
6088	u8 reserved_at_c0[0x140];
6089	};
6090
6091	struct mlx5_ifc_query_fte_out_bits {
6092	u8 status[0x8];
6093	u8 reserved_at_8[0x18];
6094
6095	u8 syndrome[0x20];
6096
6097	u8 reserved_at_40[0x1c0];
6098
6099	struct mlx5_ifc_flow_context_bits flow_context;
6100	};
6101
6102	struct mlx5_ifc_query_fte_in_bits {
6103	u8 opcode[0x10];
6104	u8 reserved_at_10[0x10];
6105
6106	u8 reserved_at_20[0x10];
6107	u8 op_mod[0x10];
6108
6109	u8 reserved_at_40[0x40];
6110
6111	u8 table_type[0x8];
6112	u8 reserved_at_88[0x18];
6113
6114	u8 reserved_at_a0[0x8];
6115	u8 table_id[0x18];
6116
6117	u8 reserved_at_c0[0x40];
6118
6119	u8 flow_index[0x20];
6120
6121	u8 reserved_at_120[0xe0];
6122	};
6123
6124	struct mlx5_ifc_match_definer_format_0_bits {
6125	u8 reserved_at_0[0x100];
6126
6127	u8 metadata_reg_c_0[0x20];
6128
6129	u8 metadata_reg_c_1[0x20];
6130
6131	u8 outer_dmac_47_16[0x20];
6132
6133	u8 outer_dmac_15_0[0x10];
6134	u8 outer_ethertype[0x10];
6135
6136	u8 reserved_at_180[0x1];
6137	u8 sx_sniffer[0x1];
6138	u8 functional_lb[0x1];
6139	u8 outer_ip_frag[0x1];
6140	u8 outer_qp_type[0x2];
6141	u8 outer_encap_type[0x2];
6142	u8 port_number[0x2];
6143	u8 outer_l3_type[0x2];
6144	u8 outer_l4_type[0x2];
6145	u8 outer_first_vlan_type[0x2];
6146	u8 outer_first_vlan_prio[0x3];
6147	u8 outer_first_vlan_cfi[0x1];
6148	u8 outer_first_vlan_vid[0xc];
6149
6150	u8 outer_l4_type_ext[0x4];
6151	u8 reserved_at_1a4[0x2];
6152	u8 outer_ipsec_layer[0x2];
6153	u8 outer_l2_type[0x2];
6154	u8 force_lb[0x1];
6155	u8 outer_l2_ok[0x1];
6156	u8 outer_l3_ok[0x1];
6157	u8 outer_l4_ok[0x1];
6158	u8 outer_second_vlan_type[0x2];
6159	u8 outer_second_vlan_prio[0x3];
6160	u8 outer_second_vlan_cfi[0x1];
6161	u8 outer_second_vlan_vid[0xc];
6162
6163	u8 outer_smac_47_16[0x20];
6164
6165	u8 outer_smac_15_0[0x10];
6166	u8 inner_ipv4_checksum_ok[0x1];
6167	u8 inner_l4_checksum_ok[0x1];
6168	u8 outer_ipv4_checksum_ok[0x1];
6169	u8 outer_l4_checksum_ok[0x1];
6170	u8 inner_l3_ok[0x1];
6171	u8 inner_l4_ok[0x1];
6172	u8 outer_l3_ok_duplicate[0x1];
6173	u8 outer_l4_ok_duplicate[0x1];
6174	u8 outer_tcp_cwr[0x1];
6175	u8 outer_tcp_ece[0x1];
6176	u8 outer_tcp_urg[0x1];
6177	u8 outer_tcp_ack[0x1];
6178	u8 outer_tcp_psh[0x1];
6179	u8 outer_tcp_rst[0x1];
6180	u8 outer_tcp_syn[0x1];
6181	u8 outer_tcp_fin[0x1];
6182	};
6183
6184	struct mlx5_ifc_match_definer_format_22_bits {
6185	u8 reserved_at_0[0x100];
6186
6187	u8 outer_ip_src_addr[0x20];
6188
6189	u8 outer_ip_dest_addr[0x20];
6190
6191	u8 outer_l4_sport[0x10];
6192	u8 outer_l4_dport[0x10];
6193
6194	u8 reserved_at_160[0x1];
6195	u8 sx_sniffer[0x1];
6196	u8 functional_lb[0x1];
6197	u8 outer_ip_frag[0x1];
6198	u8 outer_qp_type[0x2];
6199	u8 outer_encap_type[0x2];
6200	u8 port_number[0x2];
6201	u8 outer_l3_type[0x2];
6202	u8 outer_l4_type[0x2];
6203	u8 outer_first_vlan_type[0x2];
6204	u8 outer_first_vlan_prio[0x3];
6205	u8 outer_first_vlan_cfi[0x1];
6206	u8 outer_first_vlan_vid[0xc];
6207
6208	u8 metadata_reg_c_0[0x20];
6209
6210	u8 outer_dmac_47_16[0x20];
6211
6212	u8 outer_smac_47_16[0x20];
6213
6214	u8 outer_smac_15_0[0x10];
6215	u8 outer_dmac_15_0[0x10];
6216	};
6217
6218	struct mlx5_ifc_match_definer_format_23_bits {
6219	u8 reserved_at_0[0x100];
6220
6221	u8 inner_ip_src_addr[0x20];
6222
6223	u8 inner_ip_dest_addr[0x20];
6224
6225	u8 inner_l4_sport[0x10];
6226	u8 inner_l4_dport[0x10];
6227
6228	u8 reserved_at_160[0x1];
6229	u8 sx_sniffer[0x1];
6230	u8 functional_lb[0x1];
6231	u8 inner_ip_frag[0x1];
6232	u8 inner_qp_type[0x2];
6233	u8 inner_encap_type[0x2];
6234	u8 port_number[0x2];
6235	u8 inner_l3_type[0x2];
6236	u8 inner_l4_type[0x2];
6237	u8 inner_first_vlan_type[0x2];
6238	u8 inner_first_vlan_prio[0x3];
6239	u8 inner_first_vlan_cfi[0x1];
6240	u8 inner_first_vlan_vid[0xc];
6241
6242	u8 tunnel_header_0[0x20];
6243
6244	u8 inner_dmac_47_16[0x20];
6245
6246	u8 inner_smac_47_16[0x20];
6247
6248	u8 inner_smac_15_0[0x10];
6249	u8 inner_dmac_15_0[0x10];
6250	};
6251
6252	struct mlx5_ifc_match_definer_format_29_bits {
6253	u8 reserved_at_0[0xc0];
6254
6255	u8 outer_ip_dest_addr[0x80];
6256
6257	u8 outer_ip_src_addr[0x80];
6258
6259	u8 outer_l4_sport[0x10];
6260	u8 outer_l4_dport[0x10];
6261
6262	u8 reserved_at_1e0[0x20];
6263	};
6264
6265	struct mlx5_ifc_match_definer_format_30_bits {
6266	u8 reserved_at_0[0xa0];
6267
6268	u8 outer_ip_dest_addr[0x80];
6269
6270	u8 outer_ip_src_addr[0x80];
6271
6272	u8 outer_dmac_47_16[0x20];
6273
6274	u8 outer_smac_47_16[0x20];
6275
6276	u8 outer_smac_15_0[0x10];
6277	u8 outer_dmac_15_0[0x10];
6278	};
6279
6280	struct mlx5_ifc_match_definer_format_31_bits {
6281	u8 reserved_at_0[0xc0];
6282
6283	u8 inner_ip_dest_addr[0x80];
6284
6285	u8 inner_ip_src_addr[0x80];
6286
6287	u8 inner_l4_sport[0x10];
6288	u8 inner_l4_dport[0x10];
6289
6290	u8 reserved_at_1e0[0x20];
6291	};
6292
6293	struct mlx5_ifc_match_definer_format_32_bits {
6294	u8 reserved_at_0[0xa0];
6295
6296	u8 inner_ip_dest_addr[0x80];
6297
6298	u8 inner_ip_src_addr[0x80];
6299
6300	u8 inner_dmac_47_16[0x20];
6301
6302	u8 inner_smac_47_16[0x20];
6303
6304	u8 inner_smac_15_0[0x10];
6305	u8 inner_dmac_15_0[0x10];
6306	};
6307
6308	enum {
6309	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6310	};
6311
6312	#define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6313	#define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6314	#define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6315	#define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6316
6317	struct mlx5_ifc_match_definer_match_mask_bits {
6318	u8 reserved_at_1c0[5][0x20];
6319	u8 match_dw_8[0x20];
6320	u8 match_dw_7[0x20];
6321	u8 match_dw_6[0x20];
6322	u8 match_dw_5[0x20];
6323	u8 match_dw_4[0x20];
6324	u8 match_dw_3[0x20];
6325	u8 match_dw_2[0x20];
6326	u8 match_dw_1[0x20];
6327	u8 match_dw_0[0x20];
6328
6329	u8 match_byte_7[0x8];
6330	u8 match_byte_6[0x8];
6331	u8 match_byte_5[0x8];
6332	u8 match_byte_4[0x8];
6333
6334	u8 match_byte_3[0x8];
6335	u8 match_byte_2[0x8];
6336	u8 match_byte_1[0x8];
6337	u8 match_byte_0[0x8];
6338	};
6339
6340	struct mlx5_ifc_match_definer_bits {
6341	u8 modify_field_select[0x40];
6342
6343	u8 reserved_at_40[0x40];
6344
6345	u8 reserved_at_80[0x10];
6346	u8 format_id[0x10];
6347
6348	u8 reserved_at_a0[0x60];
6349
6350	u8 format_select_dw3[0x8];
6351	u8 format_select_dw2[0x8];
6352	u8 format_select_dw1[0x8];
6353	u8 format_select_dw0[0x8];
6354
6355	u8 format_select_dw7[0x8];
6356	u8 format_select_dw6[0x8];
6357	u8 format_select_dw5[0x8];
6358	u8 format_select_dw4[0x8];
6359
6360	u8 reserved_at_100[0x18];
6361	u8 format_select_dw8[0x8];
6362
6363	u8 reserved_at_120[0x20];
6364
6365	u8 format_select_byte3[0x8];
6366	u8 format_select_byte2[0x8];
6367	u8 format_select_byte1[0x8];
6368	u8 format_select_byte0[0x8];
6369
6370	u8 format_select_byte7[0x8];
6371	u8 format_select_byte6[0x8];
6372	u8 format_select_byte5[0x8];
6373	u8 format_select_byte4[0x8];
6374
6375	u8 reserved_at_180[0x40];
6376
6377	union {
6378	struct {
6379	u8 match_mask[16][0x20];
6380	};
6381	struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6382	};
6383	};
6384
6385	struct mlx5_ifc_general_obj_create_param_bits {
6386	u8 alias_object[0x1];
6387	u8 reserved_at_1[0x2];
6388	u8 log_obj_range[0x5];
6389	u8 reserved_at_8[0x18];
6390	};
6391
6392	struct mlx5_ifc_general_obj_query_param_bits {
6393	u8 alias_object[0x1];
6394	u8 obj_offset[0x1f];
6395	};
6396
6397	struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6398	u8 opcode[0x10];
6399	u8 uid[0x10];
6400
6401	u8 vhca_tunnel_id[0x10];
6402	u8 obj_type[0x10];
6403
6404	u8 obj_id[0x20];
6405
6406	union {
6407	struct mlx5_ifc_general_obj_create_param_bits create;
6408	struct mlx5_ifc_general_obj_query_param_bits query;
6409	} op_param;
6410	};
6411
6412	struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6413	u8 status[0x8];
6414	u8 reserved_at_8[0x18];
6415
6416	u8 syndrome[0x20];
6417
6418	u8 obj_id[0x20];
6419
6420	u8 reserved_at_60[0x20];
6421	};
6422
6423	struct mlx5_ifc_allow_other_vhca_access_in_bits {
6424	u8 opcode[0x10];
6425	u8 uid[0x10];
6426	u8 reserved_at_20[0x10];
6427	u8 op_mod[0x10];
6428	u8 reserved_at_40[0x50];
6429	u8 object_type_to_be_accessed[0x10];
6430	u8 object_id_to_be_accessed[0x20];
6431	u8 reserved_at_c0[0x40];
6432	union {
6433	u8 access_key_raw[0x100];
6434	u8 access_key[8][0x20];
6435	};
6436	};
6437
6438	struct mlx5_ifc_allow_other_vhca_access_out_bits {
6439	u8 status[0x8];
6440	u8 reserved_at_8[0x18];
6441	u8 syndrome[0x20];
6442	u8 reserved_at_40[0x40];
6443	};
6444
6445	struct mlx5_ifc_modify_header_arg_bits {
6446	u8 reserved_at_0[0x80];
6447
6448	u8 reserved_at_80[0x8];
6449	u8 access_pd[0x18];
6450	};
6451
6452	struct mlx5_ifc_create_modify_header_arg_in_bits {
6453	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6454	struct mlx5_ifc_modify_header_arg_bits arg;
6455	};
6456
6457	struct mlx5_ifc_create_match_definer_in_bits {
6458	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6459
6460	struct mlx5_ifc_match_definer_bits obj_context;
6461	};
6462
6463	struct mlx5_ifc_create_match_definer_out_bits {
6464	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6465	};
6466
6467	struct mlx5_ifc_alias_context_bits {
6468	u8 vhca_id_to_be_accessed[0x10];
6469	u8 reserved_at_10[0xd];
6470	u8 status[0x3];
6471	u8 object_id_to_be_accessed[0x20];
6472	u8 reserved_at_40[0x40];
6473	union {
6474	u8 access_key_raw[0x100];
6475	u8 access_key[8][0x20];
6476	};
6477	u8 metadata[0x80];
6478	};
6479
6480	struct mlx5_ifc_create_alias_obj_in_bits {
6481	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6482	struct mlx5_ifc_alias_context_bits alias_ctx;
6483	};
6484
6485	enum {
6486	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6487	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6488	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6489	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6490	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6491	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6492	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6493	};
6494
6495	struct mlx5_ifc_query_flow_group_out_bits {
6496	u8 status[0x8];
6497	u8 reserved_at_8[0x18];
6498
6499	u8 syndrome[0x20];
6500
6501	u8 reserved_at_40[0xa0];
6502
6503	u8 start_flow_index[0x20];
6504
6505	u8 reserved_at_100[0x20];
6506
6507	u8 end_flow_index[0x20];
6508
6509	u8 reserved_at_140[0xa0];
6510
6511	u8 reserved_at_1e0[0x18];
6512	u8 match_criteria_enable[0x8];
6513
6514	struct mlx5_ifc_fte_match_param_bits match_criteria;
6515
6516	u8 reserved_at_1200[0xe00];
6517	};
6518
6519	struct mlx5_ifc_query_flow_group_in_bits {
6520	u8 opcode[0x10];
6521	u8 reserved_at_10[0x10];
6522
6523	u8 reserved_at_20[0x10];
6524	u8 op_mod[0x10];
6525
6526	u8 reserved_at_40[0x40];
6527
6528	u8 table_type[0x8];
6529	u8 reserved_at_88[0x18];
6530
6531	u8 reserved_at_a0[0x8];
6532	u8 table_id[0x18];
6533
6534	u8 group_id[0x20];
6535
6536	u8 reserved_at_e0[0x120];
6537	};
6538
6539	struct mlx5_ifc_query_flow_counter_out_bits {
6540	u8 status[0x8];
6541	u8 reserved_at_8[0x18];
6542
6543	u8 syndrome[0x20];
6544
6545	u8 reserved_at_40[0x40];
6546
6547	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6548	};
6549
6550	struct mlx5_ifc_query_flow_counter_in_bits {
6551	u8 opcode[0x10];
6552	u8 reserved_at_10[0x10];
6553
6554	u8 reserved_at_20[0x10];
6555	u8 op_mod[0x10];
6556
6557	u8 reserved_at_40[0x80];
6558
6559	u8 clear[0x1];
6560	u8 reserved_at_c1[0xf];
6561	u8 num_of_counters[0x10];
6562
6563	u8 flow_counter_id[0x20];
6564	};
6565
6566	struct mlx5_ifc_query_esw_vport_context_out_bits {
6567	u8 status[0x8];
6568	u8 reserved_at_8[0x18];
6569
6570	u8 syndrome[0x20];
6571
6572	u8 reserved_at_40[0x40];
6573
6574	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6575	};
6576
6577	struct mlx5_ifc_query_esw_vport_context_in_bits {
6578	u8 opcode[0x10];
6579	u8 reserved_at_10[0x10];
6580
6581	u8 reserved_at_20[0x10];
6582	u8 op_mod[0x10];
6583
6584	u8 other_vport[0x1];
6585	u8 reserved_at_41[0xf];
6586	u8 vport_number[0x10];
6587
6588	u8 reserved_at_60[0x20];
6589	};
6590
6591	struct mlx5_ifc_modify_esw_vport_context_out_bits {
6592	u8 status[0x8];
6593	u8 reserved_at_8[0x18];
6594
6595	u8 syndrome[0x20];
6596
6597	u8 reserved_at_40[0x40];
6598	};
6599
6600	struct mlx5_ifc_esw_vport_context_fields_select_bits {
6601	u8 reserved_at_0[0x1b];
6602	u8 fdb_to_vport_reg_c_id[0x1];
6603	u8 vport_cvlan_insert[0x1];
6604	u8 vport_svlan_insert[0x1];
6605	u8 vport_cvlan_strip[0x1];
6606	u8 vport_svlan_strip[0x1];
6607	};
6608
6609	struct mlx5_ifc_modify_esw_vport_context_in_bits {
6610	u8 opcode[0x10];
6611	u8 reserved_at_10[0x10];
6612
6613	u8 reserved_at_20[0x10];
6614	u8 op_mod[0x10];
6615
6616	u8 other_vport[0x1];
6617	u8 reserved_at_41[0xf];
6618	u8 vport_number[0x10];
6619
6620	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6621
6622	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6623	};
6624
6625	struct mlx5_ifc_query_eq_out_bits {
6626	u8 status[0x8];
6627	u8 reserved_at_8[0x18];
6628
6629	u8 syndrome[0x20];
6630
6631	u8 reserved_at_40[0x40];
6632
6633	struct mlx5_ifc_eqc_bits eq_context_entry;
6634
6635	u8 reserved_at_280[0x40];
6636
6637	u8 event_bitmask[0x40];
6638
6639	u8 reserved_at_300[0x580];
6640
6641	u8 pas[][0x40];
6642	};
6643
6644	struct mlx5_ifc_query_eq_in_bits {
6645	u8 opcode[0x10];
6646	u8 reserved_at_10[0x10];
6647
6648	u8 reserved_at_20[0x10];
6649	u8 op_mod[0x10];
6650
6651	u8 reserved_at_40[0x18];
6652	u8 eq_number[0x8];
6653
6654	u8 reserved_at_60[0x20];
6655	};
6656
6657	struct mlx5_ifc_packet_reformat_context_in_bits {
6658	u8 reformat_type[0x8];
6659	u8 reserved_at_8[0x4];
6660	u8 reformat_param_0[0x4];
6661	u8 reserved_at_10[0x6];
6662	u8 reformat_data_size[0xa];
6663
6664	u8 reformat_param_1[0x8];
6665	u8 reserved_at_28[0x8];
6666	u8 reformat_data[2][0x8];
6667
6668	u8 more_reformat_data[][0x8];
6669	};
6670
6671	struct mlx5_ifc_query_packet_reformat_context_out_bits {
6672	u8 status[0x8];
6673	u8 reserved_at_8[0x18];
6674
6675	u8 syndrome[0x20];
6676
6677	u8 reserved_at_40[0xa0];
6678
6679	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6680	};
6681
6682	struct mlx5_ifc_query_packet_reformat_context_in_bits {
6683	u8 opcode[0x10];
6684	u8 reserved_at_10[0x10];
6685
6686	u8 reserved_at_20[0x10];
6687	u8 op_mod[0x10];
6688
6689	u8 packet_reformat_id[0x20];
6690
6691	u8 reserved_at_60[0xa0];
6692	};
6693
6694	struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6695	u8 status[0x8];
6696	u8 reserved_at_8[0x18];
6697
6698	u8 syndrome[0x20];
6699
6700	u8 packet_reformat_id[0x20];
6701
6702	u8 reserved_at_60[0x20];
6703	};
6704
6705	enum {
6706	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6707	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6708	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6709	};
6710
6711	enum mlx5_reformat_ctx_type {
6712	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6713	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6714	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6715	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6716	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6717	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6718	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6719	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6720	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6721	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6722	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6723	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6724	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6725	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6726	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6727	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6728	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6729	};
6730
6731	struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6732	u8 opcode[0x10];
6733	u8 reserved_at_10[0x10];
6734
6735	u8 reserved_at_20[0x10];
6736	u8 op_mod[0x10];
6737
6738	u8 reserved_at_40[0xa0];
6739
6740	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6741	};
6742
6743	struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6744	u8 status[0x8];
6745	u8 reserved_at_8[0x18];
6746
6747	u8 syndrome[0x20];
6748
6749	u8 reserved_at_40[0x40];
6750	};
6751
6752	struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6753	u8 opcode[0x10];
6754	u8 reserved_at_10[0x10];
6755
6756	u8 reserved_20[0x10];
6757	u8 op_mod[0x10];
6758
6759	u8 packet_reformat_id[0x20];
6760
6761	u8 reserved_60[0x20];
6762	};
6763
6764	struct mlx5_ifc_set_action_in_bits {
6765	u8 action_type[0x4];
6766	u8 field[0xc];
6767	u8 reserved_at_10[0x3];
6768	u8 offset[0x5];
6769	u8 reserved_at_18[0x3];
6770	u8 length[0x5];
6771
6772	u8 data[0x20];
6773	};
6774
6775	struct mlx5_ifc_add_action_in_bits {
6776	u8 action_type[0x4];
6777	u8 field[0xc];
6778	u8 reserved_at_10[0x10];
6779
6780	u8 data[0x20];
6781	};
6782
6783	struct mlx5_ifc_copy_action_in_bits {
6784	u8 action_type[0x4];
6785	u8 src_field[0xc];
6786	u8 reserved_at_10[0x3];
6787	u8 src_offset[0x5];
6788	u8 reserved_at_18[0x3];
6789	u8 length[0x5];
6790
6791	u8 reserved_at_20[0x4];
6792	u8 dst_field[0xc];
6793	u8 reserved_at_30[0x3];
6794	u8 dst_offset[0x5];
6795	u8 reserved_at_38[0x8];
6796	};
6797
6798	union mlx5_ifc_set_add_copy_action_in_auto_bits {
6799	struct mlx5_ifc_set_action_in_bits set_action_in;
6800	struct mlx5_ifc_add_action_in_bits add_action_in;
6801	struct mlx5_ifc_copy_action_in_bits copy_action_in;
6802	u8 reserved_at_0[0x40];
6803	};
6804
6805	enum {
6806	MLX5_ACTION_TYPE_SET = 0x1,
6807	MLX5_ACTION_TYPE_ADD = 0x2,
6808	MLX5_ACTION_TYPE_COPY = 0x3,
6809	};
6810
6811	enum {
6812	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6813	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6814	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6815	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6816	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6817	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6818	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6819	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6820	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6821	MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6822	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6823	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6824	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6825	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6826	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6827	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6828	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6829	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6830	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6831	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6832	MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6833	MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
6834	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
6835	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6836	MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6837	MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
6838	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
6839	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6840	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6841	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6842	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6843	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
6844	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6845	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
6846	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6847	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
6848	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
6849	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6850	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
6851	};
6852
6853	struct mlx5_ifc_alloc_modify_header_context_out_bits {
6854	u8 status[0x8];
6855	u8 reserved_at_8[0x18];
6856
6857	u8 syndrome[0x20];
6858
6859	u8 modify_header_id[0x20];
6860
6861	u8 reserved_at_60[0x20];
6862	};
6863
6864	struct mlx5_ifc_alloc_modify_header_context_in_bits {
6865	u8 opcode[0x10];
6866	u8 reserved_at_10[0x10];
6867
6868	u8 reserved_at_20[0x10];
6869	u8 op_mod[0x10];
6870
6871	u8 reserved_at_40[0x20];
6872
6873	u8 table_type[0x8];
6874	u8 reserved_at_68[0x10];
6875	u8 num_of_actions[0x8];
6876
6877	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6878	};
6879
6880	struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6881	u8 status[0x8];
6882	u8 reserved_at_8[0x18];
6883
6884	u8 syndrome[0x20];
6885
6886	u8 reserved_at_40[0x40];
6887	};
6888
6889	struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6890	u8 opcode[0x10];
6891	u8 reserved_at_10[0x10];
6892
6893	u8 reserved_at_20[0x10];
6894	u8 op_mod[0x10];
6895
6896	u8 modify_header_id[0x20];
6897
6898	u8 reserved_at_60[0x20];
6899	};
6900
6901	struct mlx5_ifc_query_modify_header_context_in_bits {
6902	u8 opcode[0x10];
6903	u8 uid[0x10];
6904
6905	u8 reserved_at_20[0x10];
6906	u8 op_mod[0x10];
6907
6908	u8 modify_header_id[0x20];
6909
6910	u8 reserved_at_60[0xa0];
6911	};
6912
6913	struct mlx5_ifc_query_dct_out_bits {
6914	u8 status[0x8];
6915	u8 reserved_at_8[0x18];
6916
6917	u8 syndrome[0x20];
6918
6919	u8 reserved_at_40[0x40];
6920
6921	struct mlx5_ifc_dctc_bits dct_context_entry;
6922
6923	u8 reserved_at_280[0x180];
6924	};
6925
6926	struct mlx5_ifc_query_dct_in_bits {
6927	u8 opcode[0x10];
6928	u8 reserved_at_10[0x10];
6929
6930	u8 reserved_at_20[0x10];
6931	u8 op_mod[0x10];
6932
6933	u8 reserved_at_40[0x8];
6934	u8 dctn[0x18];
6935
6936	u8 reserved_at_60[0x20];
6937	};
6938
6939	struct mlx5_ifc_query_cq_out_bits {
6940	u8 status[0x8];
6941	u8 reserved_at_8[0x18];
6942
6943	u8 syndrome[0x20];
6944
6945	u8 reserved_at_40[0x40];
6946
6947	struct mlx5_ifc_cqc_bits cq_context;
6948
6949	u8 reserved_at_280[0x600];
6950
6951	u8 pas[][0x40];
6952	};
6953
6954	struct mlx5_ifc_query_cq_in_bits {
6955	u8 opcode[0x10];
6956	u8 reserved_at_10[0x10];
6957
6958	u8 reserved_at_20[0x10];
6959	u8 op_mod[0x10];
6960
6961	u8 reserved_at_40[0x8];
6962	u8 cqn[0x18];
6963
6964	u8 reserved_at_60[0x20];
6965	};
6966
6967	struct mlx5_ifc_query_cong_status_out_bits {
6968	u8 status[0x8];
6969	u8 reserved_at_8[0x18];
6970
6971	u8 syndrome[0x20];
6972
6973	u8 reserved_at_40[0x20];
6974
6975	u8 enable[0x1];
6976	u8 tag_enable[0x1];
6977	u8 reserved_at_62[0x1e];
6978	};
6979
6980	struct mlx5_ifc_query_cong_status_in_bits {
6981	u8 opcode[0x10];
6982	u8 reserved_at_10[0x10];
6983
6984	u8 reserved_at_20[0x10];
6985	u8 op_mod[0x10];
6986
6987	u8 reserved_at_40[0x18];
6988	u8 priority[0x4];
6989	u8 cong_protocol[0x4];
6990
6991	u8 reserved_at_60[0x20];
6992	};
6993
6994	struct mlx5_ifc_query_cong_statistics_out_bits {
6995	u8 status[0x8];
6996	u8 reserved_at_8[0x18];
6997
6998	u8 syndrome[0x20];
6999
7000	u8 reserved_at_40[0x40];
7001
7002	u8 rp_cur_flows[0x20];
7003
7004	u8 sum_flows[0x20];
7005
7006	u8 rp_cnp_ignored_high[0x20];
7007
7008	u8 rp_cnp_ignored_low[0x20];
7009
7010	u8 rp_cnp_handled_high[0x20];
7011
7012	u8 rp_cnp_handled_low[0x20];
7013
7014	u8 reserved_at_140[0x100];
7015
7016	u8 time_stamp_high[0x20];
7017
7018	u8 time_stamp_low[0x20];
7019
7020	u8 accumulators_period[0x20];
7021
7022	u8 np_ecn_marked_roce_packets_high[0x20];
7023
7024	u8 np_ecn_marked_roce_packets_low[0x20];
7025
7026	u8 np_cnp_sent_high[0x20];
7027
7028	u8 np_cnp_sent_low[0x20];
7029
7030	u8 reserved_at_320[0x560];
7031	};
7032
7033	struct mlx5_ifc_query_cong_statistics_in_bits {
7034	u8 opcode[0x10];
7035	u8 reserved_at_10[0x10];
7036
7037	u8 reserved_at_20[0x10];
7038	u8 op_mod[0x10];
7039
7040	u8 clear[0x1];
7041	u8 reserved_at_41[0x1f];
7042
7043	u8 reserved_at_60[0x20];
7044	};
7045
7046	struct mlx5_ifc_query_cong_params_out_bits {
7047	u8 status[0x8];
7048	u8 reserved_at_8[0x18];
7049
7050	u8 syndrome[0x20];
7051
7052	u8 reserved_at_40[0x40];
7053
7054	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7055	};
7056
7057	struct mlx5_ifc_query_cong_params_in_bits {
7058	u8 opcode[0x10];
7059	u8 reserved_at_10[0x10];
7060
7061	u8 reserved_at_20[0x10];
7062	u8 op_mod[0x10];
7063
7064	u8 reserved_at_40[0x1c];
7065	u8 cong_protocol[0x4];
7066
7067	u8 reserved_at_60[0x20];
7068	};
7069
7070	struct mlx5_ifc_query_adapter_out_bits {
7071	u8 status[0x8];
7072	u8 reserved_at_8[0x18];
7073
7074	u8 syndrome[0x20];
7075
7076	u8 reserved_at_40[0x40];
7077
7078	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7079	};
7080
7081	struct mlx5_ifc_query_adapter_in_bits {
7082	u8 opcode[0x10];
7083	u8 reserved_at_10[0x10];
7084
7085	u8 reserved_at_20[0x10];
7086	u8 op_mod[0x10];
7087
7088	u8 reserved_at_40[0x40];
7089	};
7090
7091	struct mlx5_ifc_qp_2rst_out_bits {
7092	u8 status[0x8];
7093	u8 reserved_at_8[0x18];
7094
7095	u8 syndrome[0x20];
7096
7097	u8 reserved_at_40[0x40];
7098	};
7099
7100	struct mlx5_ifc_qp_2rst_in_bits {
7101	u8 opcode[0x10];
7102	u8 uid[0x10];
7103
7104	u8 reserved_at_20[0x10];
7105	u8 op_mod[0x10];
7106
7107	u8 reserved_at_40[0x8];
7108	u8 qpn[0x18];
7109
7110	u8 reserved_at_60[0x20];
7111	};
7112
7113	struct mlx5_ifc_qp_2err_out_bits {
7114	u8 status[0x8];
7115	u8 reserved_at_8[0x18];
7116
7117	u8 syndrome[0x20];
7118
7119	u8 reserved_at_40[0x40];
7120	};
7121
7122	struct mlx5_ifc_qp_2err_in_bits {
7123	u8 opcode[0x10];
7124	u8 uid[0x10];
7125
7126	u8 reserved_at_20[0x10];
7127	u8 op_mod[0x10];
7128
7129	u8 reserved_at_40[0x8];
7130	u8 qpn[0x18];
7131
7132	u8 reserved_at_60[0x20];
7133	};
7134
7135	struct mlx5_ifc_page_fault_resume_out_bits {
7136	u8 status[0x8];
7137	u8 reserved_at_8[0x18];
7138
7139	u8 syndrome[0x20];
7140
7141	u8 reserved_at_40[0x40];
7142	};
7143
7144	struct mlx5_ifc_page_fault_resume_in_bits {
7145	u8 opcode[0x10];
7146	u8 reserved_at_10[0x10];
7147
7148	u8 reserved_at_20[0x10];
7149	u8 op_mod[0x10];
7150
7151	u8 error[0x1];
7152	u8 reserved_at_41[0x4];
7153	u8 page_fault_type[0x3];
7154	u8 wq_number[0x18];
7155
7156	u8 reserved_at_60[0x8];
7157	u8 token[0x18];
7158	};
7159
7160	struct mlx5_ifc_nop_out_bits {
7161	u8 status[0x8];
7162	u8 reserved_at_8[0x18];
7163
7164	u8 syndrome[0x20];
7165
7166	u8 reserved_at_40[0x40];
7167	};
7168
7169	struct mlx5_ifc_nop_in_bits {
7170	u8 opcode[0x10];
7171	u8 reserved_at_10[0x10];
7172
7173	u8 reserved_at_20[0x10];
7174	u8 op_mod[0x10];
7175
7176	u8 reserved_at_40[0x40];
7177	};
7178
7179	struct mlx5_ifc_modify_vport_state_out_bits {
7180	u8 status[0x8];
7181	u8 reserved_at_8[0x18];
7182
7183	u8 syndrome[0x20];
7184
7185	u8 reserved_at_40[0x40];
7186	};
7187
7188	struct mlx5_ifc_modify_vport_state_in_bits {
7189	u8 opcode[0x10];
7190	u8 reserved_at_10[0x10];
7191
7192	u8 reserved_at_20[0x10];
7193	u8 op_mod[0x10];
7194
7195	u8 other_vport[0x1];
7196	u8 reserved_at_41[0xf];
7197	u8 vport_number[0x10];
7198
7199	u8 reserved_at_60[0x18];
7200	u8 admin_state[0x4];
7201	u8 reserved_at_7c[0x4];
7202	};
7203
7204	struct mlx5_ifc_modify_tis_out_bits {
7205	u8 status[0x8];
7206	u8 reserved_at_8[0x18];
7207
7208	u8 syndrome[0x20];
7209
7210	u8 reserved_at_40[0x40];
7211	};
7212
7213	struct mlx5_ifc_modify_tis_bitmask_bits {
7214	u8 reserved_at_0[0x20];
7215
7216	u8 reserved_at_20[0x1d];
7217	u8 lag_tx_port_affinity[0x1];
7218	u8 strict_lag_tx_port_affinity[0x1];
7219	u8 prio[0x1];
7220	};
7221
7222	struct mlx5_ifc_modify_tis_in_bits {
7223	u8 opcode[0x10];
7224	u8 uid[0x10];
7225
7226	u8 reserved_at_20[0x10];
7227	u8 op_mod[0x10];
7228
7229	u8 reserved_at_40[0x8];
7230	u8 tisn[0x18];
7231
7232	u8 reserved_at_60[0x20];
7233
7234	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7235
7236	u8 reserved_at_c0[0x40];
7237
7238	struct mlx5_ifc_tisc_bits ctx;
7239	};
7240
7241	struct mlx5_ifc_modify_tir_bitmask_bits {
7242	u8 reserved_at_0[0x20];
7243
7244	u8 reserved_at_20[0x1b];
7245	u8 self_lb_en[0x1];
7246	u8 reserved_at_3c[0x1];
7247	u8 hash[0x1];
7248	u8 reserved_at_3e[0x1];
7249	u8 packet_merge[0x1];
7250	};
7251
7252	struct mlx5_ifc_modify_tir_out_bits {
7253	u8 status[0x8];
7254	u8 reserved_at_8[0x18];
7255
7256	u8 syndrome[0x20];
7257
7258	u8 reserved_at_40[0x40];
7259	};
7260
7261	struct mlx5_ifc_modify_tir_in_bits {
7262	u8 opcode[0x10];
7263	u8 uid[0x10];
7264
7265	u8 reserved_at_20[0x10];
7266	u8 op_mod[0x10];
7267
7268	u8 reserved_at_40[0x8];
7269	u8 tirn[0x18];
7270
7271	u8 reserved_at_60[0x20];
7272
7273	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7274
7275	u8 reserved_at_c0[0x40];
7276
7277	struct mlx5_ifc_tirc_bits ctx;
7278	};
7279
7280	struct mlx5_ifc_modify_sq_out_bits {
7281	u8 status[0x8];
7282	u8 reserved_at_8[0x18];
7283
7284	u8 syndrome[0x20];
7285
7286	u8 reserved_at_40[0x40];
7287	};
7288
7289	struct mlx5_ifc_modify_sq_in_bits {
7290	u8 opcode[0x10];
7291	u8 uid[0x10];
7292
7293	u8 reserved_at_20[0x10];
7294	u8 op_mod[0x10];
7295
7296	u8 sq_state[0x4];
7297	u8 reserved_at_44[0x4];
7298	u8 sqn[0x18];
7299
7300	u8 reserved_at_60[0x20];
7301
7302	u8 modify_bitmask[0x40];
7303
7304	u8 reserved_at_c0[0x40];
7305
7306	struct mlx5_ifc_sqc_bits ctx;
7307	};
7308
7309	struct mlx5_ifc_modify_scheduling_element_out_bits {
7310	u8 status[0x8];
7311	u8 reserved_at_8[0x18];
7312
7313	u8 syndrome[0x20];
7314
7315	u8 reserved_at_40[0x1c0];
7316	};
7317
7318	enum {
7319	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7320	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7321	};
7322
7323	struct mlx5_ifc_modify_scheduling_element_in_bits {
7324	u8 opcode[0x10];
7325	u8 reserved_at_10[0x10];
7326
7327	u8 reserved_at_20[0x10];
7328	u8 op_mod[0x10];
7329
7330	u8 scheduling_hierarchy[0x8];
7331	u8 reserved_at_48[0x18];
7332
7333	u8 scheduling_element_id[0x20];
7334
7335	u8 reserved_at_80[0x20];
7336
7337	u8 modify_bitmask[0x20];
7338
7339	u8 reserved_at_c0[0x40];
7340
7341	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7342
7343	u8 reserved_at_300[0x100];
7344	};
7345
7346	struct mlx5_ifc_modify_rqt_out_bits {
7347	u8 status[0x8];
7348	u8 reserved_at_8[0x18];
7349
7350	u8 syndrome[0x20];
7351
7352	u8 reserved_at_40[0x40];
7353	};
7354
7355	struct mlx5_ifc_rqt_bitmask_bits {
7356	u8 reserved_at_0[0x20];
7357
7358	u8 reserved_at_20[0x1f];
7359	u8 rqn_list[0x1];
7360	};
7361
7362	struct mlx5_ifc_modify_rqt_in_bits {
7363	u8 opcode[0x10];
7364	u8 uid[0x10];
7365
7366	u8 reserved_at_20[0x10];
7367	u8 op_mod[0x10];
7368
7369	u8 reserved_at_40[0x8];
7370	u8 rqtn[0x18];
7371
7372	u8 reserved_at_60[0x20];
7373
7374	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7375
7376	u8 reserved_at_c0[0x40];
7377
7378	struct mlx5_ifc_rqtc_bits ctx;
7379	};
7380
7381	struct mlx5_ifc_modify_rq_out_bits {
7382	u8 status[0x8];
7383	u8 reserved_at_8[0x18];
7384
7385	u8 syndrome[0x20];
7386
7387	u8 reserved_at_40[0x40];
7388	};
7389
7390	enum {
7391	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7392	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7393	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7394	};
7395
7396	struct mlx5_ifc_modify_rq_in_bits {
7397	u8 opcode[0x10];
7398	u8 uid[0x10];
7399
7400	u8 reserved_at_20[0x10];
7401	u8 op_mod[0x10];
7402
7403	u8 rq_state[0x4];
7404	u8 reserved_at_44[0x4];
7405	u8 rqn[0x18];
7406
7407	u8 reserved_at_60[0x20];
7408
7409	u8 modify_bitmask[0x40];
7410
7411	u8 reserved_at_c0[0x40];
7412
7413	struct mlx5_ifc_rqc_bits ctx;
7414	};
7415
7416	struct mlx5_ifc_modify_rmp_out_bits {
7417	u8 status[0x8];
7418	u8 reserved_at_8[0x18];
7419
7420	u8 syndrome[0x20];
7421
7422	u8 reserved_at_40[0x40];
7423	};
7424
7425	struct mlx5_ifc_rmp_bitmask_bits {
7426	u8 reserved_at_0[0x20];
7427
7428	u8 reserved_at_20[0x1f];
7429	u8 lwm[0x1];
7430	};
7431
7432	struct mlx5_ifc_modify_rmp_in_bits {
7433	u8 opcode[0x10];
7434	u8 uid[0x10];
7435
7436	u8 reserved_at_20[0x10];
7437	u8 op_mod[0x10];
7438
7439	u8 rmp_state[0x4];
7440	u8 reserved_at_44[0x4];
7441	u8 rmpn[0x18];
7442
7443	u8 reserved_at_60[0x20];
7444
7445	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7446
7447	u8 reserved_at_c0[0x40];
7448
7449	struct mlx5_ifc_rmpc_bits ctx;
7450	};
7451
7452	struct mlx5_ifc_modify_nic_vport_context_out_bits {
7453	u8 status[0x8];
7454	u8 reserved_at_8[0x18];
7455
7456	u8 syndrome[0x20];
7457
7458	u8 reserved_at_40[0x40];
7459	};
7460
7461	struct mlx5_ifc_modify_nic_vport_field_select_bits {
7462	u8 reserved_at_0[0x12];
7463	u8 affiliation[0x1];
7464	u8 reserved_at_13[0x1];
7465	u8 disable_uc_local_lb[0x1];
7466	u8 disable_mc_local_lb[0x1];
7467	u8 node_guid[0x1];
7468	u8 port_guid[0x1];
7469	u8 min_inline[0x1];
7470	u8 mtu[0x1];
7471	u8 change_event[0x1];
7472	u8 promisc[0x1];
7473	u8 permanent_address[0x1];
7474	u8 addresses_list[0x1];
7475	u8 roce_en[0x1];
7476	u8 reserved_at_1f[0x1];
7477	};
7478
7479	struct mlx5_ifc_modify_nic_vport_context_in_bits {
7480	u8 opcode[0x10];
7481	u8 reserved_at_10[0x10];
7482
7483	u8 reserved_at_20[0x10];
7484	u8 op_mod[0x10];
7485
7486	u8 other_vport[0x1];
7487	u8 reserved_at_41[0xf];
7488	u8 vport_number[0x10];
7489
7490	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7491
7492	u8 reserved_at_80[0x780];
7493
7494	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7495	};
7496
7497	struct mlx5_ifc_modify_hca_vport_context_out_bits {
7498	u8 status[0x8];
7499	u8 reserved_at_8[0x18];
7500
7501	u8 syndrome[0x20];
7502
7503	u8 reserved_at_40[0x40];
7504	};
7505
7506	struct mlx5_ifc_modify_hca_vport_context_in_bits {
7507	u8 opcode[0x10];
7508	u8 reserved_at_10[0x10];
7509
7510	u8 reserved_at_20[0x10];
7511	u8 op_mod[0x10];
7512
7513	u8 other_vport[0x1];
7514	u8 reserved_at_41[0xb];
7515	u8 port_num[0x4];
7516	u8 vport_number[0x10];
7517
7518	u8 reserved_at_60[0x20];
7519
7520	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7521	};
7522
7523	struct mlx5_ifc_modify_cq_out_bits {
7524	u8 status[0x8];
7525	u8 reserved_at_8[0x18];
7526
7527	u8 syndrome[0x20];
7528
7529	u8 reserved_at_40[0x40];
7530	};
7531
7532	enum {
7533	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7534	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7535	};
7536
7537	struct mlx5_ifc_modify_cq_in_bits {
7538	u8 opcode[0x10];
7539	u8 uid[0x10];
7540
7541	u8 reserved_at_20[0x10];
7542	u8 op_mod[0x10];
7543
7544	u8 reserved_at_40[0x8];
7545	u8 cqn[0x18];
7546
7547	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7548
7549	struct mlx5_ifc_cqc_bits cq_context;
7550
7551	u8 reserved_at_280[0x60];
7552
7553	u8 cq_umem_valid[0x1];
7554	u8 reserved_at_2e1[0x1f];
7555
7556	u8 reserved_at_300[0x580];
7557
7558	u8 pas[][0x40];
7559	};
7560
7561	struct mlx5_ifc_modify_cong_status_out_bits {
7562	u8 status[0x8];
7563	u8 reserved_at_8[0x18];
7564
7565	u8 syndrome[0x20];
7566
7567	u8 reserved_at_40[0x40];
7568	};
7569
7570	struct mlx5_ifc_modify_cong_status_in_bits {
7571	u8 opcode[0x10];
7572	u8 reserved_at_10[0x10];
7573
7574	u8 reserved_at_20[0x10];
7575	u8 op_mod[0x10];
7576
7577	u8 reserved_at_40[0x18];
7578	u8 priority[0x4];
7579	u8 cong_protocol[0x4];
7580
7581	u8 enable[0x1];
7582	u8 tag_enable[0x1];
7583	u8 reserved_at_62[0x1e];
7584	};
7585
7586	struct mlx5_ifc_modify_cong_params_out_bits {
7587	u8 status[0x8];
7588	u8 reserved_at_8[0x18];
7589
7590	u8 syndrome[0x20];
7591
7592	u8 reserved_at_40[0x40];
7593	};
7594
7595	struct mlx5_ifc_modify_cong_params_in_bits {
7596	u8 opcode[0x10];
7597	u8 reserved_at_10[0x10];
7598
7599	u8 reserved_at_20[0x10];
7600	u8 op_mod[0x10];
7601
7602	u8 reserved_at_40[0x1c];
7603	u8 cong_protocol[0x4];
7604
7605	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7606
7607	u8 reserved_at_80[0x80];
7608
7609	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7610	};
7611
7612	struct mlx5_ifc_manage_pages_out_bits {
7613	u8 status[0x8];
7614	u8 reserved_at_8[0x18];
7615
7616	u8 syndrome[0x20];
7617
7618	u8 output_num_entries[0x20];
7619
7620	u8 reserved_at_60[0x20];
7621
7622	u8 pas[][0x40];
7623	};
7624
7625	enum {
7626	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7627	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7628	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7629	};
7630
7631	struct mlx5_ifc_manage_pages_in_bits {
7632	u8 opcode[0x10];
7633	u8 reserved_at_10[0x10];
7634
7635	u8 reserved_at_20[0x10];
7636	u8 op_mod[0x10];
7637
7638	u8 embedded_cpu_function[0x1];
7639	u8 reserved_at_41[0xf];
7640	u8 function_id[0x10];
7641
7642	u8 input_num_entries[0x20];
7643
7644	u8 pas[][0x40];
7645	};
7646
7647	struct mlx5_ifc_mad_ifc_out_bits {
7648	u8 status[0x8];
7649	u8 reserved_at_8[0x18];
7650
7651	u8 syndrome[0x20];
7652
7653	u8 reserved_at_40[0x40];
7654
7655	u8 response_mad_packet[256][0x8];
7656	};
7657
7658	struct mlx5_ifc_mad_ifc_in_bits {
7659	u8 opcode[0x10];
7660	u8 reserved_at_10[0x10];
7661
7662	u8 reserved_at_20[0x10];
7663	u8 op_mod[0x10];
7664
7665	u8 remote_lid[0x10];
7666	u8 reserved_at_50[0x8];
7667	u8 port[0x8];
7668
7669	u8 reserved_at_60[0x20];
7670
7671	u8 mad[256][0x8];
7672	};
7673
7674	struct mlx5_ifc_init_hca_out_bits {
7675	u8 status[0x8];
7676	u8 reserved_at_8[0x18];
7677
7678	u8 syndrome[0x20];
7679
7680	u8 reserved_at_40[0x40];
7681	};
7682
7683	struct mlx5_ifc_init_hca_in_bits {
7684	u8 opcode[0x10];
7685	u8 reserved_at_10[0x10];
7686
7687	u8 reserved_at_20[0x10];
7688	u8 op_mod[0x10];
7689
7690	u8 reserved_at_40[0x20];
7691
7692	u8 reserved_at_60[0x2];
7693	u8 sw_vhca_id[0xe];
7694	u8 reserved_at_70[0x10];
7695
7696	u8 sw_owner_id[4][0x20];
7697	};
7698
7699	struct mlx5_ifc_init2rtr_qp_out_bits {
7700	u8 status[0x8];
7701	u8 reserved_at_8[0x18];
7702
7703	u8 syndrome[0x20];
7704
7705	u8 reserved_at_40[0x20];
7706	u8 ece[0x20];
7707	};
7708
7709	struct mlx5_ifc_init2rtr_qp_in_bits {
7710	u8 opcode[0x10];
7711	u8 uid[0x10];
7712
7713	u8 reserved_at_20[0x10];
7714	u8 op_mod[0x10];
7715
7716	u8 reserved_at_40[0x8];
7717	u8 qpn[0x18];
7718
7719	u8 reserved_at_60[0x20];
7720
7721	u8 opt_param_mask[0x20];
7722
7723	u8 ece[0x20];
7724
7725	struct mlx5_ifc_qpc_bits qpc;
7726
7727	u8 reserved_at_800[0x80];
7728	};
7729
7730	struct mlx5_ifc_init2init_qp_out_bits {
7731	u8 status[0x8];
7732	u8 reserved_at_8[0x18];
7733
7734	u8 syndrome[0x20];
7735
7736	u8 reserved_at_40[0x20];
7737	u8 ece[0x20];
7738	};
7739
7740	struct mlx5_ifc_init2init_qp_in_bits {
7741	u8 opcode[0x10];
7742	u8 uid[0x10];
7743
7744	u8 reserved_at_20[0x10];
7745	u8 op_mod[0x10];
7746
7747	u8 reserved_at_40[0x8];
7748	u8 qpn[0x18];
7749
7750	u8 reserved_at_60[0x20];
7751
7752	u8 opt_param_mask[0x20];
7753
7754	u8 ece[0x20];
7755
7756	struct mlx5_ifc_qpc_bits qpc;
7757
7758	u8 reserved_at_800[0x80];
7759	};
7760
7761	struct mlx5_ifc_get_dropped_packet_log_out_bits {
7762	u8 status[0x8];
7763	u8 reserved_at_8[0x18];
7764
7765	u8 syndrome[0x20];
7766
7767	u8 reserved_at_40[0x40];
7768
7769	u8 packet_headers_log[128][0x8];
7770
7771	u8 packet_syndrome[64][0x8];
7772	};
7773
7774	struct mlx5_ifc_get_dropped_packet_log_in_bits {
7775	u8 opcode[0x10];
7776	u8 reserved_at_10[0x10];
7777
7778	u8 reserved_at_20[0x10];
7779	u8 op_mod[0x10];
7780
7781	u8 reserved_at_40[0x40];
7782	};
7783
7784	struct mlx5_ifc_gen_eqe_in_bits {
7785	u8 opcode[0x10];
7786	u8 reserved_at_10[0x10];
7787
7788	u8 reserved_at_20[0x10];
7789	u8 op_mod[0x10];
7790
7791	u8 reserved_at_40[0x18];
7792	u8 eq_number[0x8];
7793
7794	u8 reserved_at_60[0x20];
7795
7796	u8 eqe[64][0x8];
7797	};
7798
7799	struct mlx5_ifc_gen_eq_out_bits {
7800	u8 status[0x8];
7801	u8 reserved_at_8[0x18];
7802
7803	u8 syndrome[0x20];
7804
7805	u8 reserved_at_40[0x40];
7806	};
7807
7808	struct mlx5_ifc_enable_hca_out_bits {
7809	u8 status[0x8];
7810	u8 reserved_at_8[0x18];
7811
7812	u8 syndrome[0x20];
7813
7814	u8 reserved_at_40[0x20];
7815	};
7816
7817	struct mlx5_ifc_enable_hca_in_bits {
7818	u8 opcode[0x10];
7819	u8 reserved_at_10[0x10];
7820
7821	u8 reserved_at_20[0x10];
7822	u8 op_mod[0x10];
7823
7824	u8 embedded_cpu_function[0x1];
7825	u8 reserved_at_41[0xf];
7826	u8 function_id[0x10];
7827
7828	u8 reserved_at_60[0x20];
7829	};
7830
7831	struct mlx5_ifc_drain_dct_out_bits {
7832	u8 status[0x8];
7833	u8 reserved_at_8[0x18];
7834
7835	u8 syndrome[0x20];
7836
7837	u8 reserved_at_40[0x40];
7838	};
7839
7840	struct mlx5_ifc_drain_dct_in_bits {
7841	u8 opcode[0x10];
7842	u8 uid[0x10];
7843
7844	u8 reserved_at_20[0x10];
7845	u8 op_mod[0x10];
7846
7847	u8 reserved_at_40[0x8];
7848	u8 dctn[0x18];
7849
7850	u8 reserved_at_60[0x20];
7851	};
7852
7853	struct mlx5_ifc_disable_hca_out_bits {
7854	u8 status[0x8];
7855	u8 reserved_at_8[0x18];
7856
7857	u8 syndrome[0x20];
7858
7859	u8 reserved_at_40[0x20];
7860	};
7861
7862	struct mlx5_ifc_disable_hca_in_bits {
7863	u8 opcode[0x10];
7864	u8 reserved_at_10[0x10];
7865
7866	u8 reserved_at_20[0x10];
7867	u8 op_mod[0x10];
7868
7869	u8 embedded_cpu_function[0x1];
7870	u8 reserved_at_41[0xf];
7871	u8 function_id[0x10];
7872
7873	u8 reserved_at_60[0x20];
7874	};
7875
7876	struct mlx5_ifc_detach_from_mcg_out_bits {
7877	u8 status[0x8];
7878	u8 reserved_at_8[0x18];
7879
7880	u8 syndrome[0x20];
7881
7882	u8 reserved_at_40[0x40];
7883	};
7884
7885	struct mlx5_ifc_detach_from_mcg_in_bits {
7886	u8 opcode[0x10];
7887	u8 uid[0x10];
7888
7889	u8 reserved_at_20[0x10];
7890	u8 op_mod[0x10];
7891
7892	u8 reserved_at_40[0x8];
7893	u8 qpn[0x18];
7894
7895	u8 reserved_at_60[0x20];
7896
7897	u8 multicast_gid[16][0x8];
7898	};
7899
7900	struct mlx5_ifc_destroy_xrq_out_bits {
7901	u8 status[0x8];
7902	u8 reserved_at_8[0x18];
7903
7904	u8 syndrome[0x20];
7905
7906	u8 reserved_at_40[0x40];
7907	};
7908
7909	struct mlx5_ifc_destroy_xrq_in_bits {
7910	u8 opcode[0x10];
7911	u8 uid[0x10];
7912
7913	u8 reserved_at_20[0x10];
7914	u8 op_mod[0x10];
7915
7916	u8 reserved_at_40[0x8];
7917	u8 xrqn[0x18];
7918
7919	u8 reserved_at_60[0x20];
7920	};
7921
7922	struct mlx5_ifc_destroy_xrc_srq_out_bits {
7923	u8 status[0x8];
7924	u8 reserved_at_8[0x18];
7925
7926	u8 syndrome[0x20];
7927
7928	u8 reserved_at_40[0x40];
7929	};
7930
7931	struct mlx5_ifc_destroy_xrc_srq_in_bits {
7932	u8 opcode[0x10];
7933	u8 uid[0x10];
7934
7935	u8 reserved_at_20[0x10];
7936	u8 op_mod[0x10];
7937
7938	u8 reserved_at_40[0x8];
7939	u8 xrc_srqn[0x18];
7940
7941	u8 reserved_at_60[0x20];
7942	};
7943
7944	struct mlx5_ifc_destroy_tis_out_bits {
7945	u8 status[0x8];
7946	u8 reserved_at_8[0x18];
7947
7948	u8 syndrome[0x20];
7949
7950	u8 reserved_at_40[0x40];
7951	};
7952
7953	struct mlx5_ifc_destroy_tis_in_bits {
7954	u8 opcode[0x10];
7955	u8 uid[0x10];
7956
7957	u8 reserved_at_20[0x10];
7958	u8 op_mod[0x10];
7959
7960	u8 reserved_at_40[0x8];
7961	u8 tisn[0x18];
7962
7963	u8 reserved_at_60[0x20];
7964	};
7965
7966	struct mlx5_ifc_destroy_tir_out_bits {
7967	u8 status[0x8];
7968	u8 reserved_at_8[0x18];
7969
7970	u8 syndrome[0x20];
7971
7972	u8 reserved_at_40[0x40];
7973	};
7974
7975	struct mlx5_ifc_destroy_tir_in_bits {
7976	u8 opcode[0x10];
7977	u8 uid[0x10];
7978
7979	u8 reserved_at_20[0x10];
7980	u8 op_mod[0x10];
7981
7982	u8 reserved_at_40[0x8];
7983	u8 tirn[0x18];
7984
7985	u8 reserved_at_60[0x20];
7986	};
7987
7988	struct mlx5_ifc_destroy_srq_out_bits {
7989	u8 status[0x8];
7990	u8 reserved_at_8[0x18];
7991
7992	u8 syndrome[0x20];
7993
7994	u8 reserved_at_40[0x40];
7995	};
7996
7997	struct mlx5_ifc_destroy_srq_in_bits {
7998	u8 opcode[0x10];
7999	u8 uid[0x10];
8000
8001	u8 reserved_at_20[0x10];
8002	u8 op_mod[0x10];
8003
8004	u8 reserved_at_40[0x8];
8005	u8 srqn[0x18];
8006
8007	u8 reserved_at_60[0x20];
8008	};
8009
8010	struct mlx5_ifc_destroy_sq_out_bits {
8011	u8 status[0x8];
8012	u8 reserved_at_8[0x18];
8013
8014	u8 syndrome[0x20];
8015
8016	u8 reserved_at_40[0x40];
8017	};
8018
8019	struct mlx5_ifc_destroy_sq_in_bits {
8020	u8 opcode[0x10];
8021	u8 uid[0x10];
8022
8023	u8 reserved_at_20[0x10];
8024	u8 op_mod[0x10];
8025
8026	u8 reserved_at_40[0x8];
8027	u8 sqn[0x18];
8028
8029	u8 reserved_at_60[0x20];
8030	};
8031
8032	struct mlx5_ifc_destroy_scheduling_element_out_bits {
8033	u8 status[0x8];
8034	u8 reserved_at_8[0x18];
8035
8036	u8 syndrome[0x20];
8037
8038	u8 reserved_at_40[0x1c0];
8039	};
8040
8041	struct mlx5_ifc_destroy_scheduling_element_in_bits {
8042	u8 opcode[0x10];
8043	u8 reserved_at_10[0x10];
8044
8045	u8 reserved_at_20[0x10];
8046	u8 op_mod[0x10];
8047
8048	u8 scheduling_hierarchy[0x8];
8049	u8 reserved_at_48[0x18];
8050
8051	u8 scheduling_element_id[0x20];
8052
8053	u8 reserved_at_80[0x180];
8054	};
8055
8056	struct mlx5_ifc_destroy_rqt_out_bits {
8057	u8 status[0x8];
8058	u8 reserved_at_8[0x18];
8059
8060	u8 syndrome[0x20];
8061
8062	u8 reserved_at_40[0x40];
8063	};
8064
8065	struct mlx5_ifc_destroy_rqt_in_bits {
8066	u8 opcode[0x10];
8067	u8 uid[0x10];
8068
8069	u8 reserved_at_20[0x10];
8070	u8 op_mod[0x10];
8071
8072	u8 reserved_at_40[0x8];
8073	u8 rqtn[0x18];
8074
8075	u8 reserved_at_60[0x20];
8076	};
8077
8078	struct mlx5_ifc_destroy_rq_out_bits {
8079	u8 status[0x8];
8080	u8 reserved_at_8[0x18];
8081
8082	u8 syndrome[0x20];
8083
8084	u8 reserved_at_40[0x40];
8085	};
8086
8087	struct mlx5_ifc_destroy_rq_in_bits {
8088	u8 opcode[0x10];
8089	u8 uid[0x10];
8090
8091	u8 reserved_at_20[0x10];
8092	u8 op_mod[0x10];
8093
8094	u8 reserved_at_40[0x8];
8095	u8 rqn[0x18];
8096
8097	u8 reserved_at_60[0x20];
8098	};
8099
8100	struct mlx5_ifc_set_delay_drop_params_in_bits {
8101	u8 opcode[0x10];
8102	u8 reserved_at_10[0x10];
8103
8104	u8 reserved_at_20[0x10];
8105	u8 op_mod[0x10];
8106
8107	u8 reserved_at_40[0x20];
8108
8109	u8 reserved_at_60[0x10];
8110	u8 delay_drop_timeout[0x10];
8111	};
8112
8113	struct mlx5_ifc_set_delay_drop_params_out_bits {
8114	u8 status[0x8];
8115	u8 reserved_at_8[0x18];
8116
8117	u8 syndrome[0x20];
8118
8119	u8 reserved_at_40[0x40];
8120	};
8121
8122	struct mlx5_ifc_destroy_rmp_out_bits {
8123	u8 status[0x8];
8124	u8 reserved_at_8[0x18];
8125
8126	u8 syndrome[0x20];
8127
8128	u8 reserved_at_40[0x40];
8129	};
8130
8131	struct mlx5_ifc_destroy_rmp_in_bits {
8132	u8 opcode[0x10];
8133	u8 uid[0x10];
8134
8135	u8 reserved_at_20[0x10];
8136	u8 op_mod[0x10];
8137
8138	u8 reserved_at_40[0x8];
8139	u8 rmpn[0x18];
8140
8141	u8 reserved_at_60[0x20];
8142	};
8143
8144	struct mlx5_ifc_destroy_qp_out_bits {
8145	u8 status[0x8];
8146	u8 reserved_at_8[0x18];
8147
8148	u8 syndrome[0x20];
8149
8150	u8 reserved_at_40[0x40];
8151	};
8152
8153	struct mlx5_ifc_destroy_qp_in_bits {
8154	u8 opcode[0x10];
8155	u8 uid[0x10];
8156
8157	u8 reserved_at_20[0x10];
8158	u8 op_mod[0x10];
8159
8160	u8 reserved_at_40[0x8];
8161	u8 qpn[0x18];
8162
8163	u8 reserved_at_60[0x20];
8164	};
8165
8166	struct mlx5_ifc_destroy_psv_out_bits {
8167	u8 status[0x8];
8168	u8 reserved_at_8[0x18];
8169
8170	u8 syndrome[0x20];
8171
8172	u8 reserved_at_40[0x40];
8173	};
8174
8175	struct mlx5_ifc_destroy_psv_in_bits {
8176	u8 opcode[0x10];
8177	u8 reserved_at_10[0x10];
8178
8179	u8 reserved_at_20[0x10];
8180	u8 op_mod[0x10];
8181
8182	u8 reserved_at_40[0x8];
8183	u8 psvn[0x18];
8184
8185	u8 reserved_at_60[0x20];
8186	};
8187
8188	struct mlx5_ifc_destroy_mkey_out_bits {
8189	u8 status[0x8];
8190	u8 reserved_at_8[0x18];
8191
8192	u8 syndrome[0x20];
8193
8194	u8 reserved_at_40[0x40];
8195	};
8196
8197	struct mlx5_ifc_destroy_mkey_in_bits {
8198	u8 opcode[0x10];
8199	u8 uid[0x10];
8200
8201	u8 reserved_at_20[0x10];
8202	u8 op_mod[0x10];
8203
8204	u8 reserved_at_40[0x8];
8205	u8 mkey_index[0x18];
8206
8207	u8 reserved_at_60[0x20];
8208	};
8209
8210	struct mlx5_ifc_destroy_flow_table_out_bits {
8211	u8 status[0x8];
8212	u8 reserved_at_8[0x18];
8213
8214	u8 syndrome[0x20];
8215
8216	u8 reserved_at_40[0x40];
8217	};
8218
8219	struct mlx5_ifc_destroy_flow_table_in_bits {
8220	u8 opcode[0x10];
8221	u8 reserved_at_10[0x10];
8222
8223	u8 reserved_at_20[0x10];
8224	u8 op_mod[0x10];
8225
8226	u8 other_vport[0x1];
8227	u8 reserved_at_41[0xf];
8228	u8 vport_number[0x10];
8229
8230	u8 reserved_at_60[0x20];
8231
8232	u8 table_type[0x8];
8233	u8 reserved_at_88[0x18];
8234
8235	u8 reserved_at_a0[0x8];
8236	u8 table_id[0x18];
8237
8238	u8 reserved_at_c0[0x140];
8239	};
8240
8241	struct mlx5_ifc_destroy_flow_group_out_bits {
8242	u8 status[0x8];
8243	u8 reserved_at_8[0x18];
8244
8245	u8 syndrome[0x20];
8246
8247	u8 reserved_at_40[0x40];
8248	};
8249
8250	struct mlx5_ifc_destroy_flow_group_in_bits {
8251	u8 opcode[0x10];
8252	u8 reserved_at_10[0x10];
8253
8254	u8 reserved_at_20[0x10];
8255	u8 op_mod[0x10];
8256
8257	u8 other_vport[0x1];
8258	u8 reserved_at_41[0xf];
8259	u8 vport_number[0x10];
8260
8261	u8 reserved_at_60[0x20];
8262
8263	u8 table_type[0x8];
8264	u8 reserved_at_88[0x18];
8265
8266	u8 reserved_at_a0[0x8];
8267	u8 table_id[0x18];
8268
8269	u8 group_id[0x20];
8270
8271	u8 reserved_at_e0[0x120];
8272	};
8273
8274	struct mlx5_ifc_destroy_eq_out_bits {
8275	u8 status[0x8];
8276	u8 reserved_at_8[0x18];
8277
8278	u8 syndrome[0x20];
8279
8280	u8 reserved_at_40[0x40];
8281	};
8282
8283	struct mlx5_ifc_destroy_eq_in_bits {
8284	u8 opcode[0x10];
8285	u8 reserved_at_10[0x10];
8286
8287	u8 reserved_at_20[0x10];
8288	u8 op_mod[0x10];
8289
8290	u8 reserved_at_40[0x18];
8291	u8 eq_number[0x8];
8292
8293	u8 reserved_at_60[0x20];
8294	};
8295
8296	struct mlx5_ifc_destroy_dct_out_bits {
8297	u8 status[0x8];
8298	u8 reserved_at_8[0x18];
8299
8300	u8 syndrome[0x20];
8301
8302	u8 reserved_at_40[0x40];
8303	};
8304
8305	struct mlx5_ifc_destroy_dct_in_bits {
8306	u8 opcode[0x10];
8307	u8 uid[0x10];
8308
8309	u8 reserved_at_20[0x10];
8310	u8 op_mod[0x10];
8311
8312	u8 reserved_at_40[0x8];
8313	u8 dctn[0x18];
8314
8315	u8 reserved_at_60[0x20];
8316	};
8317
8318	struct mlx5_ifc_destroy_cq_out_bits {
8319	u8 status[0x8];
8320	u8 reserved_at_8[0x18];
8321
8322	u8 syndrome[0x20];
8323
8324	u8 reserved_at_40[0x40];
8325	};
8326
8327	struct mlx5_ifc_destroy_cq_in_bits {
8328	u8 opcode[0x10];
8329	u8 uid[0x10];
8330
8331	u8 reserved_at_20[0x10];
8332	u8 op_mod[0x10];
8333
8334	u8 reserved_at_40[0x8];
8335	u8 cqn[0x18];
8336
8337	u8 reserved_at_60[0x20];
8338	};
8339
8340	struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8341	u8 status[0x8];
8342	u8 reserved_at_8[0x18];
8343
8344	u8 syndrome[0x20];
8345
8346	u8 reserved_at_40[0x40];
8347	};
8348
8349	struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8350	u8 opcode[0x10];
8351	u8 reserved_at_10[0x10];
8352
8353	u8 reserved_at_20[0x10];
8354	u8 op_mod[0x10];
8355
8356	u8 reserved_at_40[0x20];
8357
8358	u8 reserved_at_60[0x10];
8359	u8 vxlan_udp_port[0x10];
8360	};
8361
8362	struct mlx5_ifc_delete_l2_table_entry_out_bits {
8363	u8 status[0x8];
8364	u8 reserved_at_8[0x18];
8365
8366	u8 syndrome[0x20];
8367
8368	u8 reserved_at_40[0x40];
8369	};
8370
8371	struct mlx5_ifc_delete_l2_table_entry_in_bits {
8372	u8 opcode[0x10];
8373	u8 reserved_at_10[0x10];
8374
8375	u8 reserved_at_20[0x10];
8376	u8 op_mod[0x10];
8377
8378	u8 reserved_at_40[0x60];
8379
8380	u8 reserved_at_a0[0x8];
8381	u8 table_index[0x18];
8382
8383	u8 reserved_at_c0[0x140];
8384	};
8385
8386	struct mlx5_ifc_delete_fte_out_bits {
8387	u8 status[0x8];
8388	u8 reserved_at_8[0x18];
8389
8390	u8 syndrome[0x20];
8391
8392	u8 reserved_at_40[0x40];
8393	};
8394
8395	struct mlx5_ifc_delete_fte_in_bits {
8396	u8 opcode[0x10];
8397	u8 reserved_at_10[0x10];
8398
8399	u8 reserved_at_20[0x10];
8400	u8 op_mod[0x10];
8401
8402	u8 other_vport[0x1];
8403	u8 reserved_at_41[0xf];
8404	u8 vport_number[0x10];
8405
8406	u8 reserved_at_60[0x20];
8407
8408	u8 table_type[0x8];
8409	u8 reserved_at_88[0x18];
8410
8411	u8 reserved_at_a0[0x8];
8412	u8 table_id[0x18];
8413
8414	u8 reserved_at_c0[0x40];
8415
8416	u8 flow_index[0x20];
8417
8418	u8 reserved_at_120[0xe0];
8419	};
8420
8421	struct mlx5_ifc_dealloc_xrcd_out_bits {
8422	u8 status[0x8];
8423	u8 reserved_at_8[0x18];
8424
8425	u8 syndrome[0x20];
8426
8427	u8 reserved_at_40[0x40];
8428	};
8429
8430	struct mlx5_ifc_dealloc_xrcd_in_bits {
8431	u8 opcode[0x10];
8432	u8 uid[0x10];
8433
8434	u8 reserved_at_20[0x10];
8435	u8 op_mod[0x10];
8436
8437	u8 reserved_at_40[0x8];
8438	u8 xrcd[0x18];
8439
8440	u8 reserved_at_60[0x20];
8441	};
8442
8443	struct mlx5_ifc_dealloc_uar_out_bits {
8444	u8 status[0x8];
8445	u8 reserved_at_8[0x18];
8446
8447	u8 syndrome[0x20];
8448
8449	u8 reserved_at_40[0x40];
8450	};
8451
8452	struct mlx5_ifc_dealloc_uar_in_bits {
8453	u8 opcode[0x10];
8454	u8 uid[0x10];
8455
8456	u8 reserved_at_20[0x10];
8457	u8 op_mod[0x10];
8458
8459	u8 reserved_at_40[0x8];
8460	u8 uar[0x18];
8461
8462	u8 reserved_at_60[0x20];
8463	};
8464
8465	struct mlx5_ifc_dealloc_transport_domain_out_bits {
8466	u8 status[0x8];
8467	u8 reserved_at_8[0x18];
8468
8469	u8 syndrome[0x20];
8470
8471	u8 reserved_at_40[0x40];
8472	};
8473
8474	struct mlx5_ifc_dealloc_transport_domain_in_bits {
8475	u8 opcode[0x10];
8476	u8 uid[0x10];
8477
8478	u8 reserved_at_20[0x10];
8479	u8 op_mod[0x10];
8480
8481	u8 reserved_at_40[0x8];
8482	u8 transport_domain[0x18];
8483
8484	u8 reserved_at_60[0x20];
8485	};
8486
8487	struct mlx5_ifc_dealloc_q_counter_out_bits {
8488	u8 status[0x8];
8489	u8 reserved_at_8[0x18];
8490
8491	u8 syndrome[0x20];
8492
8493	u8 reserved_at_40[0x40];
8494	};
8495
8496	struct mlx5_ifc_dealloc_q_counter_in_bits {
8497	u8 opcode[0x10];
8498	u8 reserved_at_10[0x10];
8499
8500	u8 reserved_at_20[0x10];
8501	u8 op_mod[0x10];
8502
8503	u8 reserved_at_40[0x18];
8504	u8 counter_set_id[0x8];
8505
8506	u8 reserved_at_60[0x20];
8507	};
8508
8509	struct mlx5_ifc_dealloc_pd_out_bits {
8510	u8 status[0x8];
8511	u8 reserved_at_8[0x18];
8512
8513	u8 syndrome[0x20];
8514
8515	u8 reserved_at_40[0x40];
8516	};
8517
8518	struct mlx5_ifc_dealloc_pd_in_bits {
8519	u8 opcode[0x10];
8520	u8 uid[0x10];
8521
8522	u8 reserved_at_20[0x10];
8523	u8 op_mod[0x10];
8524
8525	u8 reserved_at_40[0x8];
8526	u8 pd[0x18];
8527
8528	u8 reserved_at_60[0x20];
8529	};
8530
8531	struct mlx5_ifc_dealloc_flow_counter_out_bits {
8532	u8 status[0x8];
8533	u8 reserved_at_8[0x18];
8534
8535	u8 syndrome[0x20];
8536
8537	u8 reserved_at_40[0x40];
8538	};
8539
8540	struct mlx5_ifc_dealloc_flow_counter_in_bits {
8541	u8 opcode[0x10];
8542	u8 reserved_at_10[0x10];
8543
8544	u8 reserved_at_20[0x10];
8545	u8 op_mod[0x10];
8546
8547	u8 flow_counter_id[0x20];
8548
8549	u8 reserved_at_60[0x20];
8550	};
8551
8552	struct mlx5_ifc_create_xrq_out_bits {
8553	u8 status[0x8];
8554	u8 reserved_at_8[0x18];
8555
8556	u8 syndrome[0x20];
8557
8558	u8 reserved_at_40[0x8];
8559	u8 xrqn[0x18];
8560
8561	u8 reserved_at_60[0x20];
8562	};
8563
8564	struct mlx5_ifc_create_xrq_in_bits {
8565	u8 opcode[0x10];
8566	u8 uid[0x10];
8567
8568	u8 reserved_at_20[0x10];
8569	u8 op_mod[0x10];
8570
8571	u8 reserved_at_40[0x40];
8572
8573	struct mlx5_ifc_xrqc_bits xrq_context;
8574	};
8575
8576	struct mlx5_ifc_create_xrc_srq_out_bits {
8577	u8 status[0x8];
8578	u8 reserved_at_8[0x18];
8579
8580	u8 syndrome[0x20];
8581
8582	u8 reserved_at_40[0x8];
8583	u8 xrc_srqn[0x18];
8584
8585	u8 reserved_at_60[0x20];
8586	};
8587
8588	struct mlx5_ifc_create_xrc_srq_in_bits {
8589	u8 opcode[0x10];
8590	u8 uid[0x10];
8591
8592	u8 reserved_at_20[0x10];
8593	u8 op_mod[0x10];
8594
8595	u8 reserved_at_40[0x40];
8596
8597	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8598
8599	u8 reserved_at_280[0x60];
8600
8601	u8 xrc_srq_umem_valid[0x1];
8602	u8 reserved_at_2e1[0x1f];
8603
8604	u8 reserved_at_300[0x580];
8605
8606	u8 pas[][0x40];
8607	};
8608
8609	struct mlx5_ifc_create_tis_out_bits {
8610	u8 status[0x8];
8611	u8 reserved_at_8[0x18];
8612
8613	u8 syndrome[0x20];
8614
8615	u8 reserved_at_40[0x8];
8616	u8 tisn[0x18];
8617
8618	u8 reserved_at_60[0x20];
8619	};
8620
8621	struct mlx5_ifc_create_tis_in_bits {
8622	u8 opcode[0x10];
8623	u8 uid[0x10];
8624
8625	u8 reserved_at_20[0x10];
8626	u8 op_mod[0x10];
8627
8628	u8 reserved_at_40[0xc0];
8629
8630	struct mlx5_ifc_tisc_bits ctx;
8631	};
8632
8633	struct mlx5_ifc_create_tir_out_bits {
8634	u8 status[0x8];
8635	u8 icm_address_63_40[0x18];
8636
8637	u8 syndrome[0x20];
8638
8639	u8 icm_address_39_32[0x8];
8640	u8 tirn[0x18];
8641
8642	u8 icm_address_31_0[0x20];
8643	};
8644
8645	struct mlx5_ifc_create_tir_in_bits {
8646	u8 opcode[0x10];
8647	u8 uid[0x10];
8648
8649	u8 reserved_at_20[0x10];
8650	u8 op_mod[0x10];
8651
8652	u8 reserved_at_40[0xc0];
8653
8654	struct mlx5_ifc_tirc_bits ctx;
8655	};
8656
8657	struct mlx5_ifc_create_srq_out_bits {
8658	u8 status[0x8];
8659	u8 reserved_at_8[0x18];
8660
8661	u8 syndrome[0x20];
8662
8663	u8 reserved_at_40[0x8];
8664	u8 srqn[0x18];
8665
8666	u8 reserved_at_60[0x20];
8667	};
8668
8669	struct mlx5_ifc_create_srq_in_bits {
8670	u8 opcode[0x10];
8671	u8 uid[0x10];
8672
8673	u8 reserved_at_20[0x10];
8674	u8 op_mod[0x10];
8675
8676	u8 reserved_at_40[0x40];
8677
8678	struct mlx5_ifc_srqc_bits srq_context_entry;
8679
8680	u8 reserved_at_280[0x600];
8681
8682	u8 pas[][0x40];
8683	};
8684
8685	struct mlx5_ifc_create_sq_out_bits {
8686	u8 status[0x8];
8687	u8 reserved_at_8[0x18];
8688
8689	u8 syndrome[0x20];
8690
8691	u8 reserved_at_40[0x8];
8692	u8 sqn[0x18];
8693
8694	u8 reserved_at_60[0x20];
8695	};
8696
8697	struct mlx5_ifc_create_sq_in_bits {
8698	u8 opcode[0x10];
8699	u8 uid[0x10];
8700
8701	u8 reserved_at_20[0x10];
8702	u8 op_mod[0x10];
8703
8704	u8 reserved_at_40[0xc0];
8705
8706	struct mlx5_ifc_sqc_bits ctx;
8707	};
8708
8709	struct mlx5_ifc_create_scheduling_element_out_bits {
8710	u8 status[0x8];
8711	u8 reserved_at_8[0x18];
8712
8713	u8 syndrome[0x20];
8714
8715	u8 reserved_at_40[0x40];
8716
8717	u8 scheduling_element_id[0x20];
8718
8719	u8 reserved_at_a0[0x160];
8720	};
8721
8722	struct mlx5_ifc_create_scheduling_element_in_bits {
8723	u8 opcode[0x10];
8724	u8 reserved_at_10[0x10];
8725
8726	u8 reserved_at_20[0x10];
8727	u8 op_mod[0x10];
8728
8729	u8 scheduling_hierarchy[0x8];
8730	u8 reserved_at_48[0x18];
8731
8732	u8 reserved_at_60[0xa0];
8733
8734	struct mlx5_ifc_scheduling_context_bits scheduling_context;
8735
8736	u8 reserved_at_300[0x100];
8737	};
8738
8739	struct mlx5_ifc_create_rqt_out_bits {
8740	u8 status[0x8];
8741	u8 reserved_at_8[0x18];
8742
8743	u8 syndrome[0x20];
8744
8745	u8 reserved_at_40[0x8];
8746	u8 rqtn[0x18];
8747
8748	u8 reserved_at_60[0x20];
8749	};
8750
8751	struct mlx5_ifc_create_rqt_in_bits {
8752	u8 opcode[0x10];
8753	u8 uid[0x10];
8754
8755	u8 reserved_at_20[0x10];
8756	u8 op_mod[0x10];
8757
8758	u8 reserved_at_40[0xc0];
8759
8760	struct mlx5_ifc_rqtc_bits rqt_context;
8761	};
8762
8763	struct mlx5_ifc_create_rq_out_bits {
8764	u8 status[0x8];
8765	u8 reserved_at_8[0x18];
8766
8767	u8 syndrome[0x20];
8768
8769	u8 reserved_at_40[0x8];
8770	u8 rqn[0x18];
8771
8772	u8 reserved_at_60[0x20];
8773	};
8774
8775	struct mlx5_ifc_create_rq_in_bits {
8776	u8 opcode[0x10];
8777	u8 uid[0x10];
8778
8779	u8 reserved_at_20[0x10];
8780	u8 op_mod[0x10];
8781
8782	u8 reserved_at_40[0xc0];
8783
8784	struct mlx5_ifc_rqc_bits ctx;
8785	};
8786
8787	struct mlx5_ifc_create_rmp_out_bits {
8788	u8 status[0x8];
8789	u8 reserved_at_8[0x18];
8790
8791	u8 syndrome[0x20];
8792
8793	u8 reserved_at_40[0x8];
8794	u8 rmpn[0x18];
8795
8796	u8 reserved_at_60[0x20];
8797	};
8798
8799	struct mlx5_ifc_create_rmp_in_bits {
8800	u8 opcode[0x10];
8801	u8 uid[0x10];
8802
8803	u8 reserved_at_20[0x10];
8804	u8 op_mod[0x10];
8805
8806	u8 reserved_at_40[0xc0];
8807
8808	struct mlx5_ifc_rmpc_bits ctx;
8809	};
8810
8811	struct mlx5_ifc_create_qp_out_bits {
8812	u8 status[0x8];
8813	u8 reserved_at_8[0x18];
8814
8815	u8 syndrome[0x20];
8816
8817	u8 reserved_at_40[0x8];
8818	u8 qpn[0x18];
8819
8820	u8 ece[0x20];
8821	};
8822
8823	struct mlx5_ifc_create_qp_in_bits {
8824	u8 opcode[0x10];
8825	u8 uid[0x10];
8826
8827	u8 reserved_at_20[0x10];
8828	u8 op_mod[0x10];
8829
8830	u8 qpc_ext[0x1];
8831	u8 reserved_at_41[0x7];
8832	u8 input_qpn[0x18];
8833
8834	u8 reserved_at_60[0x20];
8835	u8 opt_param_mask[0x20];
8836
8837	u8 ece[0x20];
8838
8839	struct mlx5_ifc_qpc_bits qpc;
8840
8841	u8 reserved_at_800[0x60];
8842
8843	u8 wq_umem_valid[0x1];
8844	u8 reserved_at_861[0x1f];
8845
8846	u8 pas[][0x40];
8847	};
8848
8849	struct mlx5_ifc_create_psv_out_bits {
8850	u8 status[0x8];
8851	u8 reserved_at_8[0x18];
8852
8853	u8 syndrome[0x20];
8854
8855	u8 reserved_at_40[0x40];
8856
8857	u8 reserved_at_80[0x8];
8858	u8 psv0_index[0x18];
8859
8860	u8 reserved_at_a0[0x8];
8861	u8 psv1_index[0x18];
8862
8863	u8 reserved_at_c0[0x8];
8864	u8 psv2_index[0x18];
8865
8866	u8 reserved_at_e0[0x8];
8867	u8 psv3_index[0x18];
8868	};
8869
8870	struct mlx5_ifc_create_psv_in_bits {
8871	u8 opcode[0x10];
8872	u8 reserved_at_10[0x10];
8873
8874	u8 reserved_at_20[0x10];
8875	u8 op_mod[0x10];
8876
8877	u8 num_psv[0x4];
8878	u8 reserved_at_44[0x4];
8879	u8 pd[0x18];
8880
8881	u8 reserved_at_60[0x20];
8882	};
8883
8884	struct mlx5_ifc_create_mkey_out_bits {
8885	u8 status[0x8];
8886	u8 reserved_at_8[0x18];
8887
8888	u8 syndrome[0x20];
8889
8890	u8 reserved_at_40[0x8];
8891	u8 mkey_index[0x18];
8892
8893	u8 reserved_at_60[0x20];
8894	};
8895
8896	struct mlx5_ifc_create_mkey_in_bits {
8897	u8 opcode[0x10];
8898	u8 uid[0x10];
8899
8900	u8 reserved_at_20[0x10];
8901	u8 op_mod[0x10];
8902
8903	u8 reserved_at_40[0x20];
8904
8905	u8 pg_access[0x1];
8906	u8 mkey_umem_valid[0x1];
8907	u8 reserved_at_62[0x1e];
8908
8909	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8910
8911	u8 reserved_at_280[0x80];
8912
8913	u8 translations_octword_actual_size[0x20];
8914
8915	u8 reserved_at_320[0x560];
8916
8917	u8 klm_pas_mtt[][0x20];
8918	};
8919
8920	enum {
8921	MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8922	MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8923	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8924	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8925	MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8926	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8927	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8928	};
8929
8930	struct mlx5_ifc_create_flow_table_out_bits {
8931	u8 status[0x8];
8932	u8 icm_address_63_40[0x18];
8933
8934	u8 syndrome[0x20];
8935
8936	u8 icm_address_39_32[0x8];
8937	u8 table_id[0x18];
8938
8939	u8 icm_address_31_0[0x20];
8940	};
8941
8942	struct mlx5_ifc_create_flow_table_in_bits {
8943	u8 opcode[0x10];
8944	u8 uid[0x10];
8945
8946	u8 reserved_at_20[0x10];
8947	u8 op_mod[0x10];
8948
8949	u8 other_vport[0x1];
8950	u8 reserved_at_41[0xf];
8951	u8 vport_number[0x10];
8952
8953	u8 reserved_at_60[0x20];
8954
8955	u8 table_type[0x8];
8956	u8 reserved_at_88[0x18];
8957
8958	u8 reserved_at_a0[0x20];
8959
8960	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8961	};
8962
8963	struct mlx5_ifc_create_flow_group_out_bits {
8964	u8 status[0x8];
8965	u8 reserved_at_8[0x18];
8966
8967	u8 syndrome[0x20];
8968
8969	u8 reserved_at_40[0x8];
8970	u8 group_id[0x18];
8971
8972	u8 reserved_at_60[0x20];
8973	};
8974
8975	enum {
8976	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8977	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8978	};
8979
8980	enum {
8981	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8982	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8983	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8984	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8985	};
8986
8987	struct mlx5_ifc_create_flow_group_in_bits {
8988	u8 opcode[0x10];
8989	u8 reserved_at_10[0x10];
8990
8991	u8 reserved_at_20[0x10];
8992	u8 op_mod[0x10];
8993
8994	u8 other_vport[0x1];
8995	u8 reserved_at_41[0xf];
8996	u8 vport_number[0x10];
8997
8998	u8 reserved_at_60[0x20];
8999
9000	u8 table_type[0x8];
9001	u8 reserved_at_88[0x4];
9002	u8 group_type[0x4];
9003	u8 reserved_at_90[0x10];
9004
9005	u8 reserved_at_a0[0x8];
9006	u8 table_id[0x18];
9007
9008	u8 source_eswitch_owner_vhca_id_valid[0x1];
9009
9010	u8 reserved_at_c1[0x1f];
9011
9012	u8 start_flow_index[0x20];
9013
9014	u8 reserved_at_100[0x20];
9015
9016	u8 end_flow_index[0x20];
9017
9018	u8 reserved_at_140[0x10];
9019	u8 match_definer_id[0x10];
9020
9021	u8 reserved_at_160[0x80];
9022
9023	u8 reserved_at_1e0[0x18];
9024	u8 match_criteria_enable[0x8];
9025
9026	struct mlx5_ifc_fte_match_param_bits match_criteria;
9027
9028	u8 reserved_at_1200[0xe00];
9029	};
9030
9031	struct mlx5_ifc_create_eq_out_bits {
9032	u8 status[0x8];
9033	u8 reserved_at_8[0x18];
9034
9035	u8 syndrome[0x20];
9036
9037	u8 reserved_at_40[0x18];
9038	u8 eq_number[0x8];
9039
9040	u8 reserved_at_60[0x20];
9041	};
9042
9043	struct mlx5_ifc_create_eq_in_bits {
9044	u8 opcode[0x10];
9045	u8 uid[0x10];
9046
9047	u8 reserved_at_20[0x10];
9048	u8 op_mod[0x10];
9049
9050	u8 reserved_at_40[0x40];
9051
9052	struct mlx5_ifc_eqc_bits eq_context_entry;
9053
9054	u8 reserved_at_280[0x40];
9055
9056	u8 event_bitmask[4][0x40];
9057
9058	u8 reserved_at_3c0[0x4c0];
9059
9060	u8 pas[][0x40];
9061	};
9062
9063	struct mlx5_ifc_create_dct_out_bits {
9064	u8 status[0x8];
9065	u8 reserved_at_8[0x18];
9066
9067	u8 syndrome[0x20];
9068
9069	u8 reserved_at_40[0x8];
9070	u8 dctn[0x18];
9071
9072	u8 ece[0x20];
9073	};
9074
9075	struct mlx5_ifc_create_dct_in_bits {
9076	u8 opcode[0x10];
9077	u8 uid[0x10];
9078
9079	u8 reserved_at_20[0x10];
9080	u8 op_mod[0x10];
9081
9082	u8 reserved_at_40[0x40];
9083
9084	struct mlx5_ifc_dctc_bits dct_context_entry;
9085
9086	u8 reserved_at_280[0x180];
9087	};
9088
9089	struct mlx5_ifc_create_cq_out_bits {
9090	u8 status[0x8];
9091	u8 reserved_at_8[0x18];
9092
9093	u8 syndrome[0x20];
9094
9095	u8 reserved_at_40[0x8];
9096	u8 cqn[0x18];
9097
9098	u8 reserved_at_60[0x20];
9099	};
9100
9101	struct mlx5_ifc_create_cq_in_bits {
9102	u8 opcode[0x10];
9103	u8 uid[0x10];
9104
9105	u8 reserved_at_20[0x10];
9106	u8 op_mod[0x10];
9107
9108	u8 reserved_at_40[0x40];
9109
9110	struct mlx5_ifc_cqc_bits cq_context;
9111
9112	u8 reserved_at_280[0x60];
9113
9114	u8 cq_umem_valid[0x1];
9115	u8 reserved_at_2e1[0x59f];
9116
9117	u8 pas[][0x40];
9118	};
9119
9120	struct mlx5_ifc_config_int_moderation_out_bits {
9121	u8 status[0x8];
9122	u8 reserved_at_8[0x18];
9123
9124	u8 syndrome[0x20];
9125
9126	u8 reserved_at_40[0x4];
9127	u8 min_delay[0xc];
9128	u8 int_vector[0x10];
9129
9130	u8 reserved_at_60[0x20];
9131	};
9132
9133	enum {
9134	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
9135	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
9136	};
9137
9138	struct mlx5_ifc_config_int_moderation_in_bits {
9139	u8 opcode[0x10];
9140	u8 reserved_at_10[0x10];
9141
9142	u8 reserved_at_20[0x10];
9143	u8 op_mod[0x10];
9144
9145	u8 reserved_at_40[0x4];
9146	u8 min_delay[0xc];
9147	u8 int_vector[0x10];
9148
9149	u8 reserved_at_60[0x20];
9150	};
9151
9152	struct mlx5_ifc_attach_to_mcg_out_bits {
9153	u8 status[0x8];
9154	u8 reserved_at_8[0x18];
9155
9156	u8 syndrome[0x20];
9157
9158	u8 reserved_at_40[0x40];
9159	};
9160
9161	struct mlx5_ifc_attach_to_mcg_in_bits {
9162	u8 opcode[0x10];
9163	u8 uid[0x10];
9164
9165	u8 reserved_at_20[0x10];
9166	u8 op_mod[0x10];
9167
9168	u8 reserved_at_40[0x8];
9169	u8 qpn[0x18];
9170
9171	u8 reserved_at_60[0x20];
9172
9173	u8 multicast_gid[16][0x8];
9174	};
9175
9176	struct mlx5_ifc_arm_xrq_out_bits {
9177	u8 status[0x8];
9178	u8 reserved_at_8[0x18];
9179
9180	u8 syndrome[0x20];
9181
9182	u8 reserved_at_40[0x40];
9183	};
9184
9185	struct mlx5_ifc_arm_xrq_in_bits {
9186	u8 opcode[0x10];
9187	u8 reserved_at_10[0x10];
9188
9189	u8 reserved_at_20[0x10];
9190	u8 op_mod[0x10];
9191
9192	u8 reserved_at_40[0x8];
9193	u8 xrqn[0x18];
9194
9195	u8 reserved_at_60[0x10];
9196	u8 lwm[0x10];
9197	};
9198
9199	struct mlx5_ifc_arm_xrc_srq_out_bits {
9200	u8 status[0x8];
9201	u8 reserved_at_8[0x18];
9202
9203	u8 syndrome[0x20];
9204
9205	u8 reserved_at_40[0x40];
9206	};
9207
9208	enum {
9209	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
9210	};
9211
9212	struct mlx5_ifc_arm_xrc_srq_in_bits {
9213	u8 opcode[0x10];
9214	u8 uid[0x10];
9215
9216	u8 reserved_at_20[0x10];
9217	u8 op_mod[0x10];
9218
9219	u8 reserved_at_40[0x8];
9220	u8 xrc_srqn[0x18];
9221
9222	u8 reserved_at_60[0x10];
9223	u8 lwm[0x10];
9224	};
9225
9226	struct mlx5_ifc_arm_rq_out_bits {
9227	u8 status[0x8];
9228	u8 reserved_at_8[0x18];
9229
9230	u8 syndrome[0x20];
9231
9232	u8 reserved_at_40[0x40];
9233	};
9234
9235	enum {
9236	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9237	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9238	};
9239
9240	struct mlx5_ifc_arm_rq_in_bits {
9241	u8 opcode[0x10];
9242	u8 uid[0x10];
9243
9244	u8 reserved_at_20[0x10];
9245	u8 op_mod[0x10];
9246
9247	u8 reserved_at_40[0x8];
9248	u8 srq_number[0x18];
9249
9250	u8 reserved_at_60[0x10];
9251	u8 lwm[0x10];
9252	};
9253
9254	struct mlx5_ifc_arm_dct_out_bits {
9255	u8 status[0x8];
9256	u8 reserved_at_8[0x18];
9257
9258	u8 syndrome[0x20];
9259
9260	u8 reserved_at_40[0x40];
9261	};
9262
9263	struct mlx5_ifc_arm_dct_in_bits {
9264	u8 opcode[0x10];
9265	u8 reserved_at_10[0x10];
9266
9267	u8 reserved_at_20[0x10];
9268	u8 op_mod[0x10];
9269
9270	u8 reserved_at_40[0x8];
9271	u8 dct_number[0x18];
9272
9273	u8 reserved_at_60[0x20];
9274	};
9275
9276	struct mlx5_ifc_alloc_xrcd_out_bits {
9277	u8 status[0x8];
9278	u8 reserved_at_8[0x18];
9279
9280	u8 syndrome[0x20];
9281
9282	u8 reserved_at_40[0x8];
9283	u8 xrcd[0x18];
9284
9285	u8 reserved_at_60[0x20];
9286	};
9287
9288	struct mlx5_ifc_alloc_xrcd_in_bits {
9289	u8 opcode[0x10];
9290	u8 uid[0x10];
9291
9292	u8 reserved_at_20[0x10];
9293	u8 op_mod[0x10];
9294
9295	u8 reserved_at_40[0x40];
9296	};
9297
9298	struct mlx5_ifc_alloc_uar_out_bits {
9299	u8 status[0x8];
9300	u8 reserved_at_8[0x18];
9301
9302	u8 syndrome[0x20];
9303
9304	u8 reserved_at_40[0x8];
9305	u8 uar[0x18];
9306
9307	u8 reserved_at_60[0x20];
9308	};
9309
9310	struct mlx5_ifc_alloc_uar_in_bits {
9311	u8 opcode[0x10];
9312	u8 uid[0x10];
9313
9314	u8 reserved_at_20[0x10];
9315	u8 op_mod[0x10];
9316
9317	u8 reserved_at_40[0x40];
9318	};
9319
9320	struct mlx5_ifc_alloc_transport_domain_out_bits {
9321	u8 status[0x8];
9322	u8 reserved_at_8[0x18];
9323
9324	u8 syndrome[0x20];
9325
9326	u8 reserved_at_40[0x8];
9327	u8 transport_domain[0x18];
9328
9329	u8 reserved_at_60[0x20];
9330	};
9331
9332	struct mlx5_ifc_alloc_transport_domain_in_bits {
9333	u8 opcode[0x10];
9334	u8 uid[0x10];
9335
9336	u8 reserved_at_20[0x10];
9337	u8 op_mod[0x10];
9338
9339	u8 reserved_at_40[0x40];
9340	};
9341
9342	struct mlx5_ifc_alloc_q_counter_out_bits {
9343	u8 status[0x8];
9344	u8 reserved_at_8[0x18];
9345
9346	u8 syndrome[0x20];
9347
9348	u8 reserved_at_40[0x18];
9349	u8 counter_set_id[0x8];
9350
9351	u8 reserved_at_60[0x20];
9352	};
9353
9354	struct mlx5_ifc_alloc_q_counter_in_bits {
9355	u8 opcode[0x10];
9356	u8 uid[0x10];
9357
9358	u8 reserved_at_20[0x10];
9359	u8 op_mod[0x10];
9360
9361	u8 reserved_at_40[0x40];
9362	};
9363
9364	struct mlx5_ifc_alloc_pd_out_bits {
9365	u8 status[0x8];
9366	u8 reserved_at_8[0x18];
9367
9368	u8 syndrome[0x20];
9369
9370	u8 reserved_at_40[0x8];
9371	u8 pd[0x18];
9372
9373	u8 reserved_at_60[0x20];
9374	};
9375
9376	struct mlx5_ifc_alloc_pd_in_bits {
9377	u8 opcode[0x10];
9378	u8 uid[0x10];
9379
9380	u8 reserved_at_20[0x10];
9381	u8 op_mod[0x10];
9382
9383	u8 reserved_at_40[0x40];
9384	};
9385
9386	struct mlx5_ifc_alloc_flow_counter_out_bits {
9387	u8 status[0x8];
9388	u8 reserved_at_8[0x18];
9389
9390	u8 syndrome[0x20];
9391
9392	u8 flow_counter_id[0x20];
9393
9394	u8 reserved_at_60[0x20];
9395	};
9396
9397	struct mlx5_ifc_alloc_flow_counter_in_bits {
9398	u8 opcode[0x10];
9399	u8 reserved_at_10[0x10];
9400
9401	u8 reserved_at_20[0x10];
9402	u8 op_mod[0x10];
9403
9404	u8 reserved_at_40[0x33];
9405	u8 flow_counter_bulk_log_size[0x5];
9406	u8 flow_counter_bulk[0x8];
9407	};
9408
9409	struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9410	u8 status[0x8];
9411	u8 reserved_at_8[0x18];
9412
9413	u8 syndrome[0x20];
9414
9415	u8 reserved_at_40[0x40];
9416	};
9417
9418	struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9419	u8 opcode[0x10];
9420	u8 reserved_at_10[0x10];
9421
9422	u8 reserved_at_20[0x10];
9423	u8 op_mod[0x10];
9424
9425	u8 reserved_at_40[0x20];
9426
9427	u8 reserved_at_60[0x10];
9428	u8 vxlan_udp_port[0x10];
9429	};
9430
9431	struct mlx5_ifc_set_pp_rate_limit_out_bits {
9432	u8 status[0x8];
9433	u8 reserved_at_8[0x18];
9434
9435	u8 syndrome[0x20];
9436
9437	u8 reserved_at_40[0x40];
9438	};
9439
9440	struct mlx5_ifc_set_pp_rate_limit_context_bits {
9441	u8 rate_limit[0x20];
9442
9443	u8 burst_upper_bound[0x20];
9444
9445	u8 reserved_at_40[0x10];
9446	u8 typical_packet_size[0x10];
9447
9448	u8 reserved_at_60[0x120];
9449	};
9450
9451	struct mlx5_ifc_set_pp_rate_limit_in_bits {
9452	u8 opcode[0x10];
9453	u8 uid[0x10];
9454
9455	u8 reserved_at_20[0x10];
9456	u8 op_mod[0x10];
9457
9458	u8 reserved_at_40[0x10];
9459	u8 rate_limit_index[0x10];
9460
9461	u8 reserved_at_60[0x20];
9462
9463	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9464	};
9465
9466	struct mlx5_ifc_access_register_out_bits {
9467	u8 status[0x8];
9468	u8 reserved_at_8[0x18];
9469
9470	u8 syndrome[0x20];
9471
9472	u8 reserved_at_40[0x40];
9473
9474	u8 register_data[][0x20];
9475	};
9476
9477	enum {
9478	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9479	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9480	};
9481
9482	struct mlx5_ifc_access_register_in_bits {
9483	u8 opcode[0x10];
9484	u8 reserved_at_10[0x10];
9485
9486	u8 reserved_at_20[0x10];
9487	u8 op_mod[0x10];
9488
9489	u8 reserved_at_40[0x10];
9490	u8 register_id[0x10];
9491
9492	u8 argument[0x20];
9493
9494	u8 register_data[][0x20];
9495	};
9496
9497	struct mlx5_ifc_sltp_reg_bits {
9498	u8 status[0x4];
9499	u8 version[0x4];
9500	u8 local_port[0x8];
9501	u8 pnat[0x2];
9502	u8 reserved_at_12[0x2];
9503	u8 lane[0x4];
9504	u8 reserved_at_18[0x8];
9505
9506	u8 reserved_at_20[0x20];
9507
9508	u8 reserved_at_40[0x7];
9509	u8 polarity[0x1];
9510	u8 ob_tap0[0x8];
9511	u8 ob_tap1[0x8];
9512	u8 ob_tap2[0x8];
9513
9514	u8 reserved_at_60[0xc];
9515	u8 ob_preemp_mode[0x4];
9516	u8 ob_reg[0x8];
9517	u8 ob_bias[0x8];
9518
9519	u8 reserved_at_80[0x20];
9520	};
9521
9522	struct mlx5_ifc_slrg_reg_bits {
9523	u8 status[0x4];
9524	u8 version[0x4];
9525	u8 local_port[0x8];
9526	u8 pnat[0x2];
9527	u8 reserved_at_12[0x2];
9528	u8 lane[0x4];
9529	u8 reserved_at_18[0x8];
9530
9531	u8 time_to_link_up[0x10];
9532	u8 reserved_at_30[0xc];
9533	u8 grade_lane_speed[0x4];
9534
9535	u8 grade_version[0x8];
9536	u8 grade[0x18];
9537
9538	u8 reserved_at_60[0x4];
9539	u8 height_grade_type[0x4];
9540	u8 height_grade[0x18];
9541
9542	u8 height_dz[0x10];
9543	u8 height_dv[0x10];
9544
9545	u8 reserved_at_a0[0x10];
9546	u8 height_sigma[0x10];
9547
9548	u8 reserved_at_c0[0x20];
9549
9550	u8 reserved_at_e0[0x4];
9551	u8 phase_grade_type[0x4];
9552	u8 phase_grade[0x18];
9553
9554	u8 reserved_at_100[0x8];
9555	u8 phase_eo_pos[0x8];
9556	u8 reserved_at_110[0x8];
9557	u8 phase_eo_neg[0x8];
9558
9559	u8 ffe_set_tested[0x10];
9560	u8 test_errors_per_lane[0x10];
9561	};
9562
9563	struct mlx5_ifc_pvlc_reg_bits {
9564	u8 reserved_at_0[0x8];
9565	u8 local_port[0x8];
9566	u8 reserved_at_10[0x10];
9567
9568	u8 reserved_at_20[0x1c];
9569	u8 vl_hw_cap[0x4];
9570
9571	u8 reserved_at_40[0x1c];
9572	u8 vl_admin[0x4];
9573
9574	u8 reserved_at_60[0x1c];
9575	u8 vl_operational[0x4];
9576	};
9577
9578	struct mlx5_ifc_pude_reg_bits {
9579	u8 swid[0x8];
9580	u8 local_port[0x8];
9581	u8 reserved_at_10[0x4];
9582	u8 admin_status[0x4];
9583	u8 reserved_at_18[0x4];
9584	u8 oper_status[0x4];
9585
9586	u8 reserved_at_20[0x60];
9587	};
9588
9589	struct mlx5_ifc_ptys_reg_bits {
9590	u8 reserved_at_0[0x1];
9591	u8 an_disable_admin[0x1];
9592	u8 an_disable_cap[0x1];
9593	u8 reserved_at_3[0x5];
9594	u8 local_port[0x8];
9595	u8 reserved_at_10[0xd];
9596	u8 proto_mask[0x3];
9597
9598	u8 an_status[0x4];
9599	u8 reserved_at_24[0xc];
9600	u8 data_rate_oper[0x10];
9601
9602	u8 ext_eth_proto_capability[0x20];
9603
9604	u8 eth_proto_capability[0x20];
9605
9606	u8 ib_link_width_capability[0x10];
9607	u8 ib_proto_capability[0x10];
9608
9609	u8 ext_eth_proto_admin[0x20];
9610
9611	u8 eth_proto_admin[0x20];
9612
9613	u8 ib_link_width_admin[0x10];
9614	u8 ib_proto_admin[0x10];
9615
9616	u8 ext_eth_proto_oper[0x20];
9617
9618	u8 eth_proto_oper[0x20];
9619
9620	u8 ib_link_width_oper[0x10];
9621	u8 ib_proto_oper[0x10];
9622
9623	u8 reserved_at_160[0x1c];
9624	u8 connector_type[0x4];
9625
9626	u8 eth_proto_lp_advertise[0x20];
9627
9628	u8 reserved_at_1a0[0x60];
9629	};
9630
9631	struct mlx5_ifc_mlcr_reg_bits {
9632	u8 reserved_at_0[0x8];
9633	u8 local_port[0x8];
9634	u8 reserved_at_10[0x20];
9635
9636	u8 beacon_duration[0x10];
9637	u8 reserved_at_40[0x10];
9638
9639	u8 beacon_remain[0x10];
9640	};
9641
9642	struct mlx5_ifc_ptas_reg_bits {
9643	u8 reserved_at_0[0x20];
9644
9645	u8 algorithm_options[0x10];
9646	u8 reserved_at_30[0x4];
9647	u8 repetitions_mode[0x4];
9648	u8 num_of_repetitions[0x8];
9649
9650	u8 grade_version[0x8];
9651	u8 height_grade_type[0x4];
9652	u8 phase_grade_type[0x4];
9653	u8 height_grade_weight[0x8];
9654	u8 phase_grade_weight[0x8];
9655
9656	u8 gisim_measure_bits[0x10];
9657	u8 adaptive_tap_measure_bits[0x10];
9658
9659	u8 ber_bath_high_error_threshold[0x10];
9660	u8 ber_bath_mid_error_threshold[0x10];
9661
9662	u8 ber_bath_low_error_threshold[0x10];
9663	u8 one_ratio_high_threshold[0x10];
9664
9665	u8 one_ratio_high_mid_threshold[0x10];
9666	u8 one_ratio_low_mid_threshold[0x10];
9667
9668	u8 one_ratio_low_threshold[0x10];
9669	u8 ndeo_error_threshold[0x10];
9670
9671	u8 mixer_offset_step_size[0x10];
9672	u8 reserved_at_110[0x8];
9673	u8 mix90_phase_for_voltage_bath[0x8];
9674
9675	u8 mixer_offset_start[0x10];
9676	u8 mixer_offset_end[0x10];
9677
9678	u8 reserved_at_140[0x15];
9679	u8 ber_test_time[0xb];
9680	};
9681
9682	struct mlx5_ifc_pspa_reg_bits {
9683	u8 swid[0x8];
9684	u8 local_port[0x8];
9685	u8 sub_port[0x8];
9686	u8 reserved_at_18[0x8];
9687
9688	u8 reserved_at_20[0x20];
9689	};
9690
9691	struct mlx5_ifc_pqdr_reg_bits {
9692	u8 reserved_at_0[0x8];
9693	u8 local_port[0x8];
9694	u8 reserved_at_10[0x5];
9695	u8 prio[0x3];
9696	u8 reserved_at_18[0x6];
9697	u8 mode[0x2];
9698
9699	u8 reserved_at_20[0x20];
9700
9701	u8 reserved_at_40[0x10];
9702	u8 min_threshold[0x10];
9703
9704	u8 reserved_at_60[0x10];
9705	u8 max_threshold[0x10];
9706
9707	u8 reserved_at_80[0x10];
9708	u8 mark_probability_denominator[0x10];
9709
9710	u8 reserved_at_a0[0x60];
9711	};
9712
9713	struct mlx5_ifc_ppsc_reg_bits {
9714	u8 reserved_at_0[0x8];
9715	u8 local_port[0x8];
9716	u8 reserved_at_10[0x10];
9717
9718	u8 reserved_at_20[0x60];
9719
9720	u8 reserved_at_80[0x1c];
9721	u8 wrps_admin[0x4];
9722
9723	u8 reserved_at_a0[0x1c];
9724	u8 wrps_status[0x4];
9725
9726	u8 reserved_at_c0[0x8];
9727	u8 up_threshold[0x8];
9728	u8 reserved_at_d0[0x8];
9729	u8 down_threshold[0x8];
9730
9731	u8 reserved_at_e0[0x20];
9732
9733	u8 reserved_at_100[0x1c];
9734	u8 srps_admin[0x4];
9735
9736	u8 reserved_at_120[0x1c];
9737	u8 srps_status[0x4];
9738
9739	u8 reserved_at_140[0x40];
9740	};
9741
9742	struct mlx5_ifc_pplr_reg_bits {
9743	u8 reserved_at_0[0x8];
9744	u8 local_port[0x8];
9745	u8 reserved_at_10[0x10];
9746
9747	u8 reserved_at_20[0x8];
9748	u8 lb_cap[0x8];
9749	u8 reserved_at_30[0x8];
9750	u8 lb_en[0x8];
9751	};
9752
9753	struct mlx5_ifc_pplm_reg_bits {
9754	u8 reserved_at_0[0x8];
9755	u8 local_port[0x8];
9756	u8 reserved_at_10[0x10];
9757
9758	u8 reserved_at_20[0x20];
9759
9760	u8 port_profile_mode[0x8];
9761	u8 static_port_profile[0x8];
9762	u8 active_port_profile[0x8];
9763	u8 reserved_at_58[0x8];
9764
9765	u8 retransmission_active[0x8];
9766	u8 fec_mode_active[0x18];
9767
9768	u8 rs_fec_correction_bypass_cap[0x4];
9769	u8 reserved_at_84[0x8];
9770	u8 fec_override_cap_56g[0x4];
9771	u8 fec_override_cap_100g[0x4];
9772	u8 fec_override_cap_50g[0x4];
9773	u8 fec_override_cap_25g[0x4];
9774	u8 fec_override_cap_10g_40g[0x4];
9775
9776	u8 rs_fec_correction_bypass_admin[0x4];
9777	u8 reserved_at_a4[0x8];
9778	u8 fec_override_admin_56g[0x4];
9779	u8 fec_override_admin_100g[0x4];
9780	u8 fec_override_admin_50g[0x4];
9781	u8 fec_override_admin_25g[0x4];
9782	u8 fec_override_admin_10g_40g[0x4];
9783
9784	u8 fec_override_cap_400g_8x[0x10];
9785	u8 fec_override_cap_200g_4x[0x10];
9786
9787	u8 fec_override_cap_100g_2x[0x10];
9788	u8 fec_override_cap_50g_1x[0x10];
9789
9790	u8 fec_override_admin_400g_8x[0x10];
9791	u8 fec_override_admin_200g_4x[0x10];
9792
9793	u8 fec_override_admin_100g_2x[0x10];
9794	u8 fec_override_admin_50g_1x[0x10];
9795
9796	u8 reserved_at_140[0x140];
9797	};
9798
9799	struct mlx5_ifc_ppcnt_reg_bits {
9800	u8 swid[0x8];
9801	u8 local_port[0x8];
9802	u8 pnat[0x2];
9803	u8 reserved_at_12[0x8];
9804	u8 grp[0x6];
9805
9806	u8 clr[0x1];
9807	u8 reserved_at_21[0x1c];
9808	u8 prio_tc[0x3];
9809
9810	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9811	};
9812
9813	struct mlx5_ifc_mpein_reg_bits {
9814	u8 reserved_at_0[0x2];
9815	u8 depth[0x6];
9816	u8 pcie_index[0x8];
9817	u8 node[0x8];
9818	u8 reserved_at_18[0x8];
9819
9820	u8 capability_mask[0x20];
9821
9822	u8 reserved_at_40[0x8];
9823	u8 link_width_enabled[0x8];
9824	u8 link_speed_enabled[0x10];
9825
9826	u8 lane0_physical_position[0x8];
9827	u8 link_width_active[0x8];
9828	u8 link_speed_active[0x10];
9829
9830	u8 num_of_pfs[0x10];
9831	u8 num_of_vfs[0x10];
9832
9833	u8 bdf0[0x10];
9834	u8 reserved_at_b0[0x10];
9835
9836	u8 max_read_request_size[0x4];
9837	u8 max_payload_size[0x4];
9838	u8 reserved_at_c8[0x5];
9839	u8 pwr_status[0x3];
9840	u8 port_type[0x4];
9841	u8 reserved_at_d4[0xb];
9842	u8 lane_reversal[0x1];
9843
9844	u8 reserved_at_e0[0x14];
9845	u8 pci_power[0xc];
9846
9847	u8 reserved_at_100[0x20];
9848
9849	u8 device_status[0x10];
9850	u8 port_state[0x8];
9851	u8 reserved_at_138[0x8];
9852
9853	u8 reserved_at_140[0x10];
9854	u8 receiver_detect_result[0x10];
9855
9856	u8 reserved_at_160[0x20];
9857	};
9858
9859	struct mlx5_ifc_mpcnt_reg_bits {
9860	u8 reserved_at_0[0x8];
9861	u8 pcie_index[0x8];
9862	u8 reserved_at_10[0xa];
9863	u8 grp[0x6];
9864
9865	u8 clr[0x1];
9866	u8 reserved_at_21[0x1f];
9867
9868	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9869	};
9870
9871	struct mlx5_ifc_ppad_reg_bits {
9872	u8 reserved_at_0[0x3];
9873	u8 single_mac[0x1];
9874	u8 reserved_at_4[0x4];
9875	u8 local_port[0x8];
9876	u8 mac_47_32[0x10];
9877
9878	u8 mac_31_0[0x20];
9879
9880	u8 reserved_at_40[0x40];
9881	};
9882
9883	struct mlx5_ifc_pmtu_reg_bits {
9884	u8 reserved_at_0[0x8];
9885	u8 local_port[0x8];
9886	u8 reserved_at_10[0x10];
9887
9888	u8 max_mtu[0x10];
9889	u8 reserved_at_30[0x10];
9890
9891	u8 admin_mtu[0x10];
9892	u8 reserved_at_50[0x10];
9893
9894	u8 oper_mtu[0x10];
9895	u8 reserved_at_70[0x10];
9896	};
9897
9898	struct mlx5_ifc_pmpr_reg_bits {
9899	u8 reserved_at_0[0x8];
9900	u8 module[0x8];
9901	u8 reserved_at_10[0x10];
9902
9903	u8 reserved_at_20[0x18];
9904	u8 attenuation_5g[0x8];
9905
9906	u8 reserved_at_40[0x18];
9907	u8 attenuation_7g[0x8];
9908
9909	u8 reserved_at_60[0x18];
9910	u8 attenuation_12g[0x8];
9911	};
9912
9913	struct mlx5_ifc_pmpe_reg_bits {
9914	u8 reserved_at_0[0x8];
9915	u8 module[0x8];
9916	u8 reserved_at_10[0xc];
9917	u8 module_status[0x4];
9918
9919	u8 reserved_at_20[0x60];
9920	};
9921
9922	struct mlx5_ifc_pmpc_reg_bits {
9923	u8 module_state_updated[32][0x8];
9924	};
9925
9926	struct mlx5_ifc_pmlpn_reg_bits {
9927	u8 reserved_at_0[0x4];
9928	u8 mlpn_status[0x4];
9929	u8 local_port[0x8];
9930	u8 reserved_at_10[0x10];
9931
9932	u8 e[0x1];
9933	u8 reserved_at_21[0x1f];
9934	};
9935
9936	struct mlx5_ifc_pmlp_reg_bits {
9937	u8 rxtx[0x1];
9938	u8 reserved_at_1[0x7];
9939	u8 local_port[0x8];
9940	u8 reserved_at_10[0x8];
9941	u8 width[0x8];
9942
9943	u8 lane0_module_mapping[0x20];
9944
9945	u8 lane1_module_mapping[0x20];
9946
9947	u8 lane2_module_mapping[0x20];
9948
9949	u8 lane3_module_mapping[0x20];
9950
9951	u8 reserved_at_a0[0x160];
9952	};
9953
9954	struct mlx5_ifc_pmaos_reg_bits {
9955	u8 reserved_at_0[0x8];
9956	u8 module[0x8];
9957	u8 reserved_at_10[0x4];
9958	u8 admin_status[0x4];
9959	u8 reserved_at_18[0x4];
9960	u8 oper_status[0x4];
9961
9962	u8 ase[0x1];
9963	u8 ee[0x1];
9964	u8 reserved_at_22[0x1c];
9965	u8 e[0x2];
9966
9967	u8 reserved_at_40[0x40];
9968	};
9969
9970	struct mlx5_ifc_plpc_reg_bits {
9971	u8 reserved_at_0[0x4];
9972	u8 profile_id[0xc];
9973	u8 reserved_at_10[0x4];
9974	u8 proto_mask[0x4];
9975	u8 reserved_at_18[0x8];
9976
9977	u8 reserved_at_20[0x10];
9978	u8 lane_speed[0x10];
9979
9980	u8 reserved_at_40[0x17];
9981	u8 lpbf[0x1];
9982	u8 fec_mode_policy[0x8];
9983
9984	u8 retransmission_capability[0x8];
9985	u8 fec_mode_capability[0x18];
9986
9987	u8 retransmission_support_admin[0x8];
9988	u8 fec_mode_support_admin[0x18];
9989
9990	u8 retransmission_request_admin[0x8];
9991	u8 fec_mode_request_admin[0x18];
9992
9993	u8 reserved_at_c0[0x80];
9994	};
9995
9996	struct mlx5_ifc_plib_reg_bits {
9997	u8 reserved_at_0[0x8];
9998	u8 local_port[0x8];
9999	u8 reserved_at_10[0x8];
10000	u8 ib_port[0x8];
10001
10002	u8 reserved_at_20[0x60];
10003	};
10004
10005	struct mlx5_ifc_plbf_reg_bits {
10006	u8 reserved_at_0[0x8];
10007	u8 local_port[0x8];
10008	u8 reserved_at_10[0xd];
10009	u8 lbf_mode[0x3];
10010
10011	u8 reserved_at_20[0x20];
10012	};
10013
10014	struct mlx5_ifc_pipg_reg_bits {
10015	u8 reserved_at_0[0x8];
10016	u8 local_port[0x8];
10017	u8 reserved_at_10[0x10];
10018
10019	u8 dic[0x1];
10020	u8 reserved_at_21[0x19];
10021	u8 ipg[0x4];
10022	u8 reserved_at_3e[0x2];
10023	};
10024
10025	struct mlx5_ifc_pifr_reg_bits {
10026	u8 reserved_at_0[0x8];
10027	u8 local_port[0x8];
10028	u8 reserved_at_10[0x10];
10029
10030	u8 reserved_at_20[0xe0];
10031
10032	u8 port_filter[8][0x20];
10033
10034	u8 port_filter_update_en[8][0x20];
10035	};
10036
10037	struct mlx5_ifc_pfcc_reg_bits {
10038	u8 reserved_at_0[0x8];
10039	u8 local_port[0x8];
10040	u8 reserved_at_10[0xb];
10041	u8 ppan_mask_n[0x1];
10042	u8 minor_stall_mask[0x1];
10043	u8 critical_stall_mask[0x1];
10044	u8 reserved_at_1e[0x2];
10045
10046	u8 ppan[0x4];
10047	u8 reserved_at_24[0x4];
10048	u8 prio_mask_tx[0x8];
10049	u8 reserved_at_30[0x8];
10050	u8 prio_mask_rx[0x8];
10051
10052	u8 pptx[0x1];
10053	u8 aptx[0x1];
10054	u8 pptx_mask_n[0x1];
10055	u8 reserved_at_43[0x5];
10056	u8 pfctx[0x8];
10057	u8 reserved_at_50[0x10];
10058
10059	u8 pprx[0x1];
10060	u8 aprx[0x1];
10061	u8 pprx_mask_n[0x1];
10062	u8 reserved_at_63[0x5];
10063	u8 pfcrx[0x8];
10064	u8 reserved_at_70[0x10];
10065
10066	u8 device_stall_minor_watermark[0x10];
10067	u8 device_stall_critical_watermark[0x10];
10068
10069	u8 reserved_at_a0[0x60];
10070	};
10071
10072	struct mlx5_ifc_pelc_reg_bits {
10073	u8 op[0x4];
10074	u8 reserved_at_4[0x4];
10075	u8 local_port[0x8];
10076	u8 reserved_at_10[0x10];
10077
10078	u8 op_admin[0x8];
10079	u8 op_capability[0x8];
10080	u8 op_request[0x8];
10081	u8 op_active[0x8];
10082
10083	u8 admin[0x40];
10084
10085	u8 capability[0x40];
10086
10087	u8 request[0x40];
10088
10089	u8 active[0x40];
10090
10091	u8 reserved_at_140[0x80];
10092	};
10093
10094	struct mlx5_ifc_peir_reg_bits {
10095	u8 reserved_at_0[0x8];
10096	u8 local_port[0x8];
10097	u8 reserved_at_10[0x10];
10098
10099	u8 reserved_at_20[0xc];
10100	u8 error_count[0x4];
10101	u8 reserved_at_30[0x10];
10102
10103	u8 reserved_at_40[0xc];
10104	u8 lane[0x4];
10105	u8 reserved_at_50[0x8];
10106	u8 error_type[0x8];
10107	};
10108
10109	struct mlx5_ifc_mpegc_reg_bits {
10110	u8 reserved_at_0[0x30];
10111	u8 field_select[0x10];
10112
10113	u8 tx_overflow_sense[0x1];
10114	u8 mark_cqe[0x1];
10115	u8 mark_cnp[0x1];
10116	u8 reserved_at_43[0x1b];
10117	u8 tx_lossy_overflow_oper[0x2];
10118
10119	u8 reserved_at_60[0x100];
10120	};
10121
10122	struct mlx5_ifc_mpir_reg_bits {
10123	u8 sdm[0x1];
10124	u8 reserved_at_1[0x1b];
10125	u8 host_buses[0x4];
10126
10127	u8 reserved_at_20[0x20];
10128
10129	u8 local_port[0x8];
10130	u8 reserved_at_28[0x18];
10131
10132	u8 reserved_at_60[0x20];
10133	};
10134
10135	enum {
10136	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0,
10137	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1,
10138	};
10139
10140	enum {
10141	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
10142	MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
10143	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
10144	};
10145
10146	struct mlx5_ifc_mtutc_reg_bits {
10147	u8 reserved_at_0[0x5];
10148	u8 freq_adj_units[0x3];
10149	u8 reserved_at_8[0x3];
10150	u8 log_max_freq_adjustment[0x5];
10151
10152	u8 reserved_at_10[0xc];
10153	u8 operation[0x4];
10154
10155	u8 freq_adjustment[0x20];
10156
10157	u8 reserved_at_40[0x40];
10158
10159	u8 utc_sec[0x20];
10160
10161	u8 reserved_at_a0[0x2];
10162	u8 utc_nsec[0x1e];
10163
10164	u8 time_adjustment[0x20];
10165	};
10166
10167	struct mlx5_ifc_pcam_enhanced_features_bits {
10168	u8 reserved_at_0[0x68];
10169	u8 fec_50G_per_lane_in_pplm[0x1];
10170	u8 reserved_at_69[0x4];
10171	u8 rx_icrc_encapsulated_counter[0x1];
10172	u8 reserved_at_6e[0x4];
10173	u8 ptys_extended_ethernet[0x1];
10174	u8 reserved_at_73[0x3];
10175	u8 pfcc_mask[0x1];
10176	u8 reserved_at_77[0x3];
10177	u8 per_lane_error_counters[0x1];
10178	u8 rx_buffer_fullness_counters[0x1];
10179	u8 ptys_connector_type[0x1];
10180	u8 reserved_at_7d[0x1];
10181	u8 ppcnt_discard_group[0x1];
10182	u8 ppcnt_statistical_group[0x1];
10183	};
10184
10185	struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10186	u8 port_access_reg_cap_mask_127_to_96[0x20];
10187	u8 port_access_reg_cap_mask_95_to_64[0x20];
10188
10189	u8 port_access_reg_cap_mask_63_to_36[0x1c];
10190	u8 pplm[0x1];
10191	u8 port_access_reg_cap_mask_34_to_32[0x3];
10192
10193	u8 port_access_reg_cap_mask_31_to_13[0x13];
10194	u8 pbmc[0x1];
10195	u8 pptb[0x1];
10196	u8 port_access_reg_cap_mask_10_to_09[0x2];
10197	u8 ppcnt[0x1];
10198	u8 port_access_reg_cap_mask_07_to_00[0x8];
10199	};
10200
10201	struct mlx5_ifc_pcam_reg_bits {
10202	u8 reserved_at_0[0x8];
10203	u8 feature_group[0x8];
10204	u8 reserved_at_10[0x8];
10205	u8 access_reg_group[0x8];
10206
10207	u8 reserved_at_20[0x20];
10208
10209	union {
10210	struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10211	u8 reserved_at_0[0x80];
10212	} port_access_reg_cap_mask;
10213
10214	u8 reserved_at_c0[0x80];
10215
10216	union {
10217	struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10218	u8 reserved_at_0[0x80];
10219	} feature_cap_mask;
10220
10221	u8 reserved_at_1c0[0xc0];
10222	};
10223
10224	struct mlx5_ifc_mcam_enhanced_features_bits {
10225	u8 reserved_at_0[0x50];
10226	u8 mtutc_freq_adj_units[0x1];
10227	u8 mtutc_time_adjustment_extended_range[0x1];
10228	u8 reserved_at_52[0xb];
10229	u8 mcia_32dwords[0x1];
10230	u8 out_pulse_duration_ns[0x1];
10231	u8 npps_period[0x1];
10232	u8 reserved_at_60[0xa];
10233	u8 reset_state[0x1];
10234	u8 ptpcyc2realtime_modify[0x1];
10235	u8 reserved_at_6c[0x2];
10236	u8 pci_status_and_power[0x1];
10237	u8 reserved_at_6f[0x5];
10238	u8 mark_tx_action_cnp[0x1];
10239	u8 mark_tx_action_cqe[0x1];
10240	u8 dynamic_tx_overflow[0x1];
10241	u8 reserved_at_77[0x4];
10242	u8 pcie_outbound_stalled[0x1];
10243	u8 tx_overflow_buffer_pkt[0x1];
10244	u8 mtpps_enh_out_per_adj[0x1];
10245	u8 mtpps_fs[0x1];
10246	u8 pcie_performance_group[0x1];
10247	};
10248
10249	struct mlx5_ifc_mcam_access_reg_bits {
10250	u8 reserved_at_0[0x1c];
10251	u8 mcda[0x1];
10252	u8 mcc[0x1];
10253	u8 mcqi[0x1];
10254	u8 mcqs[0x1];
10255
10256	u8 regs_95_to_90[0x6];
10257	u8 mpir[0x1];
10258	u8 regs_88_to_87[0x2];
10259	u8 mpegc[0x1];
10260	u8 mtutc[0x1];
10261	u8 regs_84_to_68[0x11];
10262	u8 tracer_registers[0x4];
10263
10264	u8 regs_63_to_46[0x12];
10265	u8 mrtc[0x1];
10266	u8 regs_44_to_41[0x4];
10267	u8 mfrl[0x1];
10268	u8 regs_39_to_32[0x8];
10269
10270	u8 regs_31_to_10[0x16];
10271	u8 mtmp[0x1];
10272	u8 regs_8_to_0[0x9];
10273	};
10274
10275	struct mlx5_ifc_mcam_access_reg_bits1 {
10276	u8 regs_127_to_96[0x20];
10277
10278	u8 regs_95_to_64[0x20];
10279
10280	u8 regs_63_to_32[0x20];
10281
10282	u8 regs_31_to_0[0x20];
10283	};
10284
10285	struct mlx5_ifc_mcam_access_reg_bits2 {
10286	u8 regs_127_to_99[0x1d];
10287	u8 mirc[0x1];
10288	u8 regs_97_to_96[0x2];
10289
10290	u8 regs_95_to_87[0x09];
10291	u8 synce_registers[0x2];
10292	u8 regs_84_to_64[0x15];
10293
10294	u8 regs_63_to_32[0x20];
10295
10296	u8 regs_31_to_0[0x20];
10297	};
10298
10299	struct mlx5_ifc_mcam_reg_bits {
10300	u8 reserved_at_0[0x8];
10301	u8 feature_group[0x8];
10302	u8 reserved_at_10[0x8];
10303	u8 access_reg_group[0x8];
10304
10305	u8 reserved_at_20[0x20];
10306
10307	union {
10308	struct mlx5_ifc_mcam_access_reg_bits access_regs;
10309	struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10310	struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10311	u8 reserved_at_0[0x80];
10312	} mng_access_reg_cap_mask;
10313
10314	u8 reserved_at_c0[0x80];
10315
10316	union {
10317	struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10318	u8 reserved_at_0[0x80];
10319	} mng_feature_cap_mask;
10320
10321	u8 reserved_at_1c0[0x80];
10322	};
10323
10324	struct mlx5_ifc_qcam_access_reg_cap_mask {
10325	u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
10326	u8 qpdpm[0x1];
10327	u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
10328	u8 qdpm[0x1];
10329	u8 qpts[0x1];
10330	u8 qcap[0x1];
10331	u8 qcam_access_reg_cap_mask_0[0x1];
10332	};
10333
10334	struct mlx5_ifc_qcam_qos_feature_cap_mask {
10335	u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
10336	u8 qpts_trust_both[0x1];
10337	};
10338
10339	struct mlx5_ifc_qcam_reg_bits {
10340	u8 reserved_at_0[0x8];
10341	u8 feature_group[0x8];
10342	u8 reserved_at_10[0x8];
10343	u8 access_reg_group[0x8];
10344	u8 reserved_at_20[0x20];
10345
10346	union {
10347	struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10348	u8 reserved_at_0[0x80];
10349	} qos_access_reg_cap_mask;
10350
10351	u8 reserved_at_c0[0x80];
10352
10353	union {
10354	struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10355	u8 reserved_at_0[0x80];
10356	} qos_feature_cap_mask;
10357
10358	u8 reserved_at_1c0[0x80];
10359	};
10360
10361	struct mlx5_ifc_core_dump_reg_bits {
10362	u8 reserved_at_0[0x18];
10363	u8 core_dump_type[0x8];
10364
10365	u8 reserved_at_20[0x30];
10366	u8 vhca_id[0x10];
10367
10368	u8 reserved_at_60[0x8];
10369	u8 qpn[0x18];
10370	u8 reserved_at_80[0x180];
10371	};
10372
10373	struct mlx5_ifc_pcap_reg_bits {
10374	u8 reserved_at_0[0x8];
10375	u8 local_port[0x8];
10376	u8 reserved_at_10[0x10];
10377
10378	u8 port_capability_mask[4][0x20];
10379	};
10380
10381	struct mlx5_ifc_paos_reg_bits {
10382	u8 swid[0x8];
10383	u8 local_port[0x8];
10384	u8 reserved_at_10[0x4];
10385	u8 admin_status[0x4];
10386	u8 reserved_at_18[0x4];
10387	u8 oper_status[0x4];
10388
10389	u8 ase[0x1];
10390	u8 ee[0x1];
10391	u8 reserved_at_22[0x1c];
10392	u8 e[0x2];
10393
10394	u8 reserved_at_40[0x40];
10395	};
10396
10397	struct mlx5_ifc_pamp_reg_bits {
10398	u8 reserved_at_0[0x8];
10399	u8 opamp_group[0x8];
10400	u8 reserved_at_10[0xc];
10401	u8 opamp_group_type[0x4];
10402
10403	u8 start_index[0x10];
10404	u8 reserved_at_30[0x4];
10405	u8 num_of_indices[0xc];
10406
10407	u8 index_data[18][0x10];
10408	};
10409
10410	struct mlx5_ifc_pcmr_reg_bits {
10411	u8 reserved_at_0[0x8];
10412	u8 local_port[0x8];
10413	u8 reserved_at_10[0x10];
10414
10415	u8 entropy_force_cap[0x1];
10416	u8 entropy_calc_cap[0x1];
10417	u8 entropy_gre_calc_cap[0x1];
10418	u8 reserved_at_23[0xf];
10419	u8 rx_ts_over_crc_cap[0x1];
10420	u8 reserved_at_33[0xb];
10421	u8 fcs_cap[0x1];
10422	u8 reserved_at_3f[0x1];
10423
10424	u8 entropy_force[0x1];
10425	u8 entropy_calc[0x1];
10426	u8 entropy_gre_calc[0x1];
10427	u8 reserved_at_43[0xf];
10428	u8 rx_ts_over_crc[0x1];
10429	u8 reserved_at_53[0xb];
10430	u8 fcs_chk[0x1];
10431	u8 reserved_at_5f[0x1];
10432	};
10433
10434	struct mlx5_ifc_lane_2_module_mapping_bits {
10435	u8 reserved_at_0[0x4];
10436	u8 rx_lane[0x4];
10437	u8 reserved_at_8[0x4];
10438	u8 tx_lane[0x4];
10439	u8 reserved_at_10[0x8];
10440	u8 module[0x8];
10441	};
10442
10443	struct mlx5_ifc_bufferx_reg_bits {
10444	u8 reserved_at_0[0x6];
10445	u8 lossy[0x1];
10446	u8 epsb[0x1];
10447	u8 reserved_at_8[0x8];
10448	u8 size[0x10];
10449
10450	u8 xoff_threshold[0x10];
10451	u8 xon_threshold[0x10];
10452	};
10453
10454	struct mlx5_ifc_set_node_in_bits {
10455	u8 node_description[64][0x8];
10456	};
10457
10458	struct mlx5_ifc_register_power_settings_bits {
10459	u8 reserved_at_0[0x18];
10460	u8 power_settings_level[0x8];
10461
10462	u8 reserved_at_20[0x60];
10463	};
10464
10465	struct mlx5_ifc_register_host_endianness_bits {
10466	u8 he[0x1];
10467	u8 reserved_at_1[0x1f];
10468
10469	u8 reserved_at_20[0x60];
10470	};
10471
10472	struct mlx5_ifc_umr_pointer_desc_argument_bits {
10473	u8 reserved_at_0[0x20];
10474
10475	u8 mkey[0x20];
10476
10477	u8 addressh_63_32[0x20];
10478
10479	u8 addressl_31_0[0x20];
10480	};
10481
10482	struct mlx5_ifc_ud_adrs_vector_bits {
10483	u8 dc_key[0x40];
10484
10485	u8 ext[0x1];
10486	u8 reserved_at_41[0x7];
10487	u8 destination_qp_dct[0x18];
10488
10489	u8 static_rate[0x4];
10490	u8 sl_eth_prio[0x4];
10491	u8 fl[0x1];
10492	u8 mlid[0x7];
10493	u8 rlid_udp_sport[0x10];
10494
10495	u8 reserved_at_80[0x20];
10496
10497	u8 rmac_47_16[0x20];
10498
10499	u8 rmac_15_0[0x10];
10500	u8 tclass[0x8];
10501	u8 hop_limit[0x8];
10502
10503	u8 reserved_at_e0[0x1];
10504	u8 grh[0x1];
10505	u8 reserved_at_e2[0x2];
10506	u8 src_addr_index[0x8];
10507	u8 flow_label[0x14];
10508
10509	u8 rgid_rip[16][0x8];
10510	};
10511
10512	struct mlx5_ifc_pages_req_event_bits {
10513	u8 reserved_at_0[0x10];
10514	u8 function_id[0x10];
10515
10516	u8 num_pages[0x20];
10517
10518	u8 reserved_at_40[0xa0];
10519	};
10520
10521	struct mlx5_ifc_eqe_bits {
10522	u8 reserved_at_0[0x8];
10523	u8 event_type[0x8];
10524	u8 reserved_at_10[0x8];
10525	u8 event_sub_type[0x8];
10526
10527	u8 reserved_at_20[0xe0];
10528
10529	union mlx5_ifc_event_auto_bits event_data;
10530
10531	u8 reserved_at_1e0[0x10];
10532	u8 signature[0x8];
10533	u8 reserved_at_1f8[0x7];
10534	u8 owner[0x1];
10535	};
10536
10537	enum {
10538	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10539	};
10540
10541	struct mlx5_ifc_cmd_queue_entry_bits {
10542	u8 type[0x8];
10543	u8 reserved_at_8[0x18];
10544
10545	u8 input_length[0x20];
10546
10547	u8 input_mailbox_pointer_63_32[0x20];
10548
10549	u8 input_mailbox_pointer_31_9[0x17];
10550	u8 reserved_at_77[0x9];
10551
10552	u8 command_input_inline_data[16][0x8];
10553
10554	u8 command_output_inline_data[16][0x8];
10555
10556	u8 output_mailbox_pointer_63_32[0x20];
10557
10558	u8 output_mailbox_pointer_31_9[0x17];
10559	u8 reserved_at_1b7[0x9];
10560
10561	u8 output_length[0x20];
10562
10563	u8 token[0x8];
10564	u8 signature[0x8];
10565	u8 reserved_at_1f0[0x8];
10566	u8 status[0x7];
10567	u8 ownership[0x1];
10568	};
10569
10570	struct mlx5_ifc_cmd_out_bits {
10571	u8 status[0x8];
10572	u8 reserved_at_8[0x18];
10573
10574	u8 syndrome[0x20];
10575
10576	u8 command_output[0x20];
10577	};
10578
10579	struct mlx5_ifc_cmd_in_bits {
10580	u8 opcode[0x10];
10581	u8 reserved_at_10[0x10];
10582
10583	u8 reserved_at_20[0x10];
10584	u8 op_mod[0x10];
10585
10586	u8 command[][0x20];
10587	};
10588
10589	struct mlx5_ifc_cmd_if_box_bits {
10590	u8 mailbox_data[512][0x8];
10591
10592	u8 reserved_at_1000[0x180];
10593
10594	u8 next_pointer_63_32[0x20];
10595
10596	u8 next_pointer_31_10[0x16];
10597	u8 reserved_at_11b6[0xa];
10598
10599	u8 block_number[0x20];
10600
10601	u8 reserved_at_11e0[0x8];
10602	u8 token[0x8];
10603	u8 ctrl_signature[0x8];
10604	u8 signature[0x8];
10605	};
10606
10607	struct mlx5_ifc_mtt_bits {
10608	u8 ptag_63_32[0x20];
10609
10610	u8 ptag_31_8[0x18];
10611	u8 reserved_at_38[0x6];
10612	u8 wr_en[0x1];
10613	u8 rd_en[0x1];
10614	};
10615
10616	struct mlx5_ifc_query_wol_rol_out_bits {
10617	u8 status[0x8];
10618	u8 reserved_at_8[0x18];
10619
10620	u8 syndrome[0x20];
10621
10622	u8 reserved_at_40[0x10];
10623	u8 rol_mode[0x8];
10624	u8 wol_mode[0x8];
10625
10626	u8 reserved_at_60[0x20];
10627	};
10628
10629	struct mlx5_ifc_query_wol_rol_in_bits {
10630	u8 opcode[0x10];
10631	u8 reserved_at_10[0x10];
10632
10633	u8 reserved_at_20[0x10];
10634	u8 op_mod[0x10];
10635
10636	u8 reserved_at_40[0x40];
10637	};
10638
10639	struct mlx5_ifc_set_wol_rol_out_bits {
10640	u8 status[0x8];
10641	u8 reserved_at_8[0x18];
10642
10643	u8 syndrome[0x20];
10644
10645	u8 reserved_at_40[0x40];
10646	};
10647
10648	struct mlx5_ifc_set_wol_rol_in_bits {
10649	u8 opcode[0x10];
10650	u8 reserved_at_10[0x10];
10651
10652	u8 reserved_at_20[0x10];
10653	u8 op_mod[0x10];
10654
10655	u8 rol_mode_valid[0x1];
10656	u8 wol_mode_valid[0x1];
10657	u8 reserved_at_42[0xe];
10658	u8 rol_mode[0x8];
10659	u8 wol_mode[0x8];
10660
10661	u8 reserved_at_60[0x20];
10662	};
10663
10664	enum {
10665	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10666	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10667	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10668	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7,
10669	};
10670
10671	enum {
10672	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10673	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10674	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10675	};
10676
10677	enum {
10678	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10679	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10680	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10681	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10682	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10683	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10684	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10685	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10686	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10687	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10688	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10689	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12,
10690	};
10691
10692	struct mlx5_ifc_initial_seg_bits {
10693	u8 fw_rev_minor[0x10];
10694	u8 fw_rev_major[0x10];
10695
10696	u8 cmd_interface_rev[0x10];
10697	u8 fw_rev_subminor[0x10];
10698
10699	u8 reserved_at_40[0x40];
10700
10701	u8 cmdq_phy_addr_63_32[0x20];
10702
10703	u8 cmdq_phy_addr_31_12[0x14];
10704	u8 reserved_at_b4[0x2];
10705	u8 nic_interface[0x2];
10706	u8 log_cmdq_size[0x4];
10707	u8 log_cmdq_stride[0x4];
10708
10709	u8 command_doorbell_vector[0x20];
10710
10711	u8 reserved_at_e0[0xf00];
10712
10713	u8 initializing[0x1];
10714	u8 reserved_at_fe1[0x4];
10715	u8 nic_interface_supported[0x3];
10716	u8 embedded_cpu[0x1];
10717	u8 reserved_at_fe9[0x17];
10718
10719	struct mlx5_ifc_health_buffer_bits health_buffer;
10720
10721	u8 no_dram_nic_offset[0x20];
10722
10723	u8 reserved_at_1220[0x6e40];
10724
10725	u8 reserved_at_8060[0x1f];
10726	u8 clear_int[0x1];
10727
10728	u8 health_syndrome[0x8];
10729	u8 health_counter[0x18];
10730
10731	u8 reserved_at_80a0[0x17fc0];
10732	};
10733
10734	struct mlx5_ifc_mtpps_reg_bits {
10735	u8 reserved_at_0[0xc];
10736	u8 cap_number_of_pps_pins[0x4];
10737	u8 reserved_at_10[0x4];
10738	u8 cap_max_num_of_pps_in_pins[0x4];
10739	u8 reserved_at_18[0x4];
10740	u8 cap_max_num_of_pps_out_pins[0x4];
10741
10742	u8 reserved_at_20[0x13];
10743	u8 cap_log_min_npps_period[0x5];
10744	u8 reserved_at_38[0x3];
10745	u8 cap_log_min_out_pulse_duration_ns[0x5];
10746
10747	u8 reserved_at_40[0x4];
10748	u8 cap_pin_3_mode[0x4];
10749	u8 reserved_at_48[0x4];
10750	u8 cap_pin_2_mode[0x4];
10751	u8 reserved_at_50[0x4];
10752	u8 cap_pin_1_mode[0x4];
10753	u8 reserved_at_58[0x4];
10754	u8 cap_pin_0_mode[0x4];
10755
10756	u8 reserved_at_60[0x4];
10757	u8 cap_pin_7_mode[0x4];
10758	u8 reserved_at_68[0x4];
10759	u8 cap_pin_6_mode[0x4];
10760	u8 reserved_at_70[0x4];
10761	u8 cap_pin_5_mode[0x4];
10762	u8 reserved_at_78[0x4];
10763	u8 cap_pin_4_mode[0x4];
10764
10765	u8 field_select[0x20];
10766	u8 reserved_at_a0[0x20];
10767
10768	u8 npps_period[0x40];
10769
10770	u8 enable[0x1];
10771	u8 reserved_at_101[0xb];
10772	u8 pattern[0x4];
10773	u8 reserved_at_110[0x4];
10774	u8 pin_mode[0x4];
10775	u8 pin[0x8];
10776
10777	u8 reserved_at_120[0x2];
10778	u8 out_pulse_duration_ns[0x1e];
10779
10780	u8 time_stamp[0x40];
10781
10782	u8 out_pulse_duration[0x10];
10783	u8 out_periodic_adjustment[0x10];
10784	u8 enhanced_out_periodic_adjustment[0x20];
10785
10786	u8 reserved_at_1c0[0x20];
10787	};
10788
10789	struct mlx5_ifc_mtppse_reg_bits {
10790	u8 reserved_at_0[0x18];
10791	u8 pin[0x8];
10792	u8 event_arm[0x1];
10793	u8 reserved_at_21[0x1b];
10794	u8 event_generation_mode[0x4];
10795	u8 reserved_at_40[0x40];
10796	};
10797
10798	struct mlx5_ifc_mcqs_reg_bits {
10799	u8 last_index_flag[0x1];
10800	u8 reserved_at_1[0x7];
10801	u8 fw_device[0x8];
10802	u8 component_index[0x10];
10803
10804	u8 reserved_at_20[0x10];
10805	u8 identifier[0x10];
10806
10807	u8 reserved_at_40[0x17];
10808	u8 component_status[0x5];
10809	u8 component_update_state[0x4];
10810
10811	u8 last_update_state_changer_type[0x4];
10812	u8 last_update_state_changer_host_id[0x4];
10813	u8 reserved_at_68[0x18];
10814	};
10815
10816	struct mlx5_ifc_mcqi_cap_bits {
10817	u8 supported_info_bitmask[0x20];
10818
10819	u8 component_size[0x20];
10820
10821	u8 max_component_size[0x20];
10822
10823	u8 log_mcda_word_size[0x4];
10824	u8 reserved_at_64[0xc];
10825	u8 mcda_max_write_size[0x10];
10826
10827	u8 rd_en[0x1];
10828	u8 reserved_at_81[0x1];
10829	u8 match_chip_id[0x1];
10830	u8 match_psid[0x1];
10831	u8 check_user_timestamp[0x1];
10832	u8 match_base_guid_mac[0x1];
10833	u8 reserved_at_86[0x1a];
10834	};
10835
10836	struct mlx5_ifc_mcqi_version_bits {
10837	u8 reserved_at_0[0x2];
10838	u8 build_time_valid[0x1];
10839	u8 user_defined_time_valid[0x1];
10840	u8 reserved_at_4[0x14];
10841	u8 version_string_length[0x8];
10842
10843	u8 version[0x20];
10844
10845	u8 build_time[0x40];
10846
10847	u8 user_defined_time[0x40];
10848
10849	u8 build_tool_version[0x20];
10850
10851	u8 reserved_at_e0[0x20];
10852
10853	u8 version_string[92][0x8];
10854	};
10855
10856	struct mlx5_ifc_mcqi_activation_method_bits {
10857	u8 pending_server_ac_power_cycle[0x1];
10858	u8 pending_server_dc_power_cycle[0x1];
10859	u8 pending_server_reboot[0x1];
10860	u8 pending_fw_reset[0x1];
10861	u8 auto_activate[0x1];
10862	u8 all_hosts_sync[0x1];
10863	u8 device_hw_reset[0x1];
10864	u8 reserved_at_7[0x19];
10865	};
10866
10867	union mlx5_ifc_mcqi_reg_data_bits {
10868	struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10869	struct mlx5_ifc_mcqi_version_bits mcqi_version;
10870	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10871	};
10872
10873	struct mlx5_ifc_mcqi_reg_bits {
10874	u8 read_pending_component[0x1];
10875	u8 reserved_at_1[0xf];
10876	u8 component_index[0x10];
10877
10878	u8 reserved_at_20[0x20];
10879
10880	u8 reserved_at_40[0x1b];
10881	u8 info_type[0x5];
10882
10883	u8 info_size[0x20];
10884
10885	u8 offset[0x20];
10886
10887	u8 reserved_at_a0[0x10];
10888	u8 data_size[0x10];
10889
10890	union mlx5_ifc_mcqi_reg_data_bits data[];
10891	};
10892
10893	struct mlx5_ifc_mcc_reg_bits {
10894	u8 reserved_at_0[0x4];
10895	u8 time_elapsed_since_last_cmd[0xc];
10896	u8 reserved_at_10[0x8];
10897	u8 instruction[0x8];
10898
10899	u8 reserved_at_20[0x10];
10900	u8 component_index[0x10];
10901
10902	u8 reserved_at_40[0x8];
10903	u8 update_handle[0x18];
10904
10905	u8 handle_owner_type[0x4];
10906	u8 handle_owner_host_id[0x4];
10907	u8 reserved_at_68[0x1];
10908	u8 control_progress[0x7];
10909	u8 error_code[0x8];
10910	u8 reserved_at_78[0x4];
10911	u8 control_state[0x4];
10912
10913	u8 component_size[0x20];
10914
10915	u8 reserved_at_a0[0x60];
10916	};
10917
10918	struct mlx5_ifc_mcda_reg_bits {
10919	u8 reserved_at_0[0x8];
10920	u8 update_handle[0x18];
10921
10922	u8 offset[0x20];
10923
10924	u8 reserved_at_40[0x10];
10925	u8 size[0x10];
10926
10927	u8 reserved_at_60[0x20];
10928
10929	u8 data[][0x20];
10930	};
10931
10932	enum {
10933	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10934	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10935	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10936	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
10937	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10938	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
10939	};
10940
10941	enum {
10942	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10943	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10944	};
10945
10946	enum {
10947	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10948	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10949	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10950	};
10951
10952	struct mlx5_ifc_mfrl_reg_bits {
10953	u8 reserved_at_0[0x20];
10954
10955	u8 reserved_at_20[0x2];
10956	u8 pci_sync_for_fw_update_start[0x1];
10957	u8 pci_sync_for_fw_update_resp[0x2];
10958	u8 rst_type_sel[0x3];
10959	u8 reserved_at_28[0x4];
10960	u8 reset_state[0x4];
10961	u8 reset_type[0x8];
10962	u8 reset_level[0x8];
10963	};
10964
10965	struct mlx5_ifc_mirc_reg_bits {
10966	u8 reserved_at_0[0x18];
10967	u8 status_code[0x8];
10968
10969	u8 reserved_at_20[0x20];
10970	};
10971
10972	struct mlx5_ifc_pddr_monitor_opcode_bits {
10973	u8 reserved_at_0[0x10];
10974	u8 monitor_opcode[0x10];
10975	};
10976
10977	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10978	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10979	u8 reserved_at_0[0x20];
10980	};
10981
10982	enum {
10983	/* Monitor opcodes */
10984	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10985	};
10986
10987	struct mlx5_ifc_pddr_troubleshooting_page_bits {
10988	u8 reserved_at_0[0x10];
10989	u8 group_opcode[0x10];
10990
10991	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10992
10993	u8 reserved_at_40[0x20];
10994
10995	u8 status_message[59][0x20];
10996	};
10997
10998	union mlx5_ifc_pddr_reg_page_data_auto_bits {
10999	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11000	u8 reserved_at_0[0x7c0];
11001	};
11002
11003	enum {
11004	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
11005	};
11006
11007	struct mlx5_ifc_pddr_reg_bits {
11008	u8 reserved_at_0[0x8];
11009	u8 local_port[0x8];
11010	u8 pnat[0x2];
11011	u8 reserved_at_12[0xe];
11012
11013	u8 reserved_at_20[0x18];
11014	u8 page_select[0x8];
11015
11016	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11017	};
11018
11019	struct mlx5_ifc_mrtc_reg_bits {
11020	u8 time_synced[0x1];
11021	u8 reserved_at_1[0x1f];
11022
11023	u8 reserved_at_20[0x20];
11024
11025	u8 time_h[0x20];
11026
11027	u8 time_l[0x20];
11028	};
11029
11030	struct mlx5_ifc_mtcap_reg_bits {
11031	u8 reserved_at_0[0x19];
11032	u8 sensor_count[0x7];
11033
11034	u8 reserved_at_20[0x20];
11035
11036	u8 sensor_map[0x40];
11037	};
11038
11039	struct mlx5_ifc_mtmp_reg_bits {
11040	u8 reserved_at_0[0x14];
11041	u8 sensor_index[0xc];
11042
11043	u8 reserved_at_20[0x10];
11044	u8 temperature[0x10];
11045
11046	u8 mte[0x1];
11047	u8 mtr[0x1];
11048	u8 reserved_at_42[0xe];
11049	u8 max_temperature[0x10];
11050
11051	u8 tee[0x2];
11052	u8 reserved_at_62[0xe];
11053	u8 temp_threshold_hi[0x10];
11054
11055	u8 reserved_at_80[0x10];
11056	u8 temp_threshold_lo[0x10];
11057
11058	u8 reserved_at_a0[0x20];
11059
11060	u8 sensor_name_hi[0x20];
11061	u8 sensor_name_lo[0x20];
11062	};
11063
11064	union mlx5_ifc_ports_control_registers_document_bits {
11065	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11066	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11067	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11068	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11069	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11070	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11071	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11072	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11073	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11074	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11075	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11076	struct mlx5_ifc_paos_reg_bits paos_reg;
11077	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11078	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11079	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11080	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11081	struct mlx5_ifc_peir_reg_bits peir_reg;
11082	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11083	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11084	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11085	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11086	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11087	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11088	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11089	struct mlx5_ifc_plib_reg_bits plib_reg;
11090	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11091	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11092	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11093	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11094	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11095	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11096	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11097	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11098	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11099	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11100	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11101	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11102	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11103	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11104	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11105	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11106	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11107	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11108	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11109	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11110	struct mlx5_ifc_pude_reg_bits pude_reg;
11111	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11112	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11113	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11114	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11115	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11116	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11117	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11118	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11119	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11120	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11121	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11122	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11123	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11124	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11125	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11126	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11127	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11128	u8 reserved_at_0[0x60e0];
11129	};
11130
11131	union mlx5_ifc_debug_enhancements_document_bits {
11132	struct mlx5_ifc_health_buffer_bits health_buffer;
11133	u8 reserved_at_0[0x200];
11134	};
11135
11136	union mlx5_ifc_uplink_pci_interface_document_bits {
11137	struct mlx5_ifc_initial_seg_bits initial_seg;
11138	u8 reserved_at_0[0x20060];
11139	};
11140
11141	struct mlx5_ifc_set_flow_table_root_out_bits {
11142	u8 status[0x8];
11143	u8 reserved_at_8[0x18];
11144
11145	u8 syndrome[0x20];
11146
11147	u8 reserved_at_40[0x40];
11148	};
11149
11150	struct mlx5_ifc_set_flow_table_root_in_bits {
11151	u8 opcode[0x10];
11152	u8 reserved_at_10[0x10];
11153
11154	u8 reserved_at_20[0x10];
11155	u8 op_mod[0x10];
11156
11157	u8 other_vport[0x1];
11158	u8 reserved_at_41[0xf];
11159	u8 vport_number[0x10];
11160
11161	u8 reserved_at_60[0x20];
11162
11163	u8 table_type[0x8];
11164	u8 reserved_at_88[0x7];
11165	u8 table_of_other_vport[0x1];
11166	u8 table_vport_number[0x10];
11167
11168	u8 reserved_at_a0[0x8];
11169	u8 table_id[0x18];
11170
11171	u8 reserved_at_c0[0x8];
11172	u8 underlay_qpn[0x18];
11173	u8 table_eswitch_owner_vhca_id_valid[0x1];
11174	u8 reserved_at_e1[0xf];
11175	u8 table_eswitch_owner_vhca_id[0x10];
11176	u8 reserved_at_100[0x100];
11177	};
11178
11179	enum {
11180	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
11181	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11182	};
11183
11184	struct mlx5_ifc_modify_flow_table_out_bits {
11185	u8 status[0x8];
11186	u8 reserved_at_8[0x18];
11187
11188	u8 syndrome[0x20];
11189
11190	u8 reserved_at_40[0x40];
11191	};
11192
11193	struct mlx5_ifc_modify_flow_table_in_bits {
11194	u8 opcode[0x10];
11195	u8 reserved_at_10[0x10];
11196
11197	u8 reserved_at_20[0x10];
11198	u8 op_mod[0x10];
11199
11200	u8 other_vport[0x1];
11201	u8 reserved_at_41[0xf];
11202	u8 vport_number[0x10];
11203
11204	u8 reserved_at_60[0x10];
11205	u8 modify_field_select[0x10];
11206
11207	u8 table_type[0x8];
11208	u8 reserved_at_88[0x18];
11209
11210	u8 reserved_at_a0[0x8];
11211	u8 table_id[0x18];
11212
11213	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11214	};
11215
11216	struct mlx5_ifc_ets_tcn_config_reg_bits {
11217	u8 g[0x1];
11218	u8 b[0x1];
11219	u8 r[0x1];
11220	u8 reserved_at_3[0x9];
11221	u8 group[0x4];
11222	u8 reserved_at_10[0x9];
11223	u8 bw_allocation[0x7];
11224
11225	u8 reserved_at_20[0xc];
11226	u8 max_bw_units[0x4];
11227	u8 reserved_at_30[0x8];
11228	u8 max_bw_value[0x8];
11229	};
11230
11231	struct mlx5_ifc_ets_global_config_reg_bits {
11232	u8 reserved_at_0[0x2];
11233	u8 r[0x1];
11234	u8 reserved_at_3[0x1d];
11235
11236	u8 reserved_at_20[0xc];
11237	u8 max_bw_units[0x4];
11238	u8 reserved_at_30[0x8];
11239	u8 max_bw_value[0x8];
11240	};
11241
11242	struct mlx5_ifc_qetc_reg_bits {
11243	u8 reserved_at_0[0x8];
11244	u8 port_number[0x8];
11245	u8 reserved_at_10[0x30];
11246
11247	struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
11248	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11249	};
11250
11251	struct mlx5_ifc_qpdpm_dscp_reg_bits {
11252	u8 e[0x1];
11253	u8 reserved_at_01[0x0b];
11254	u8 prio[0x04];
11255	};
11256
11257	struct mlx5_ifc_qpdpm_reg_bits {
11258	u8 reserved_at_0[0x8];
11259	u8 local_port[0x8];
11260	u8 reserved_at_10[0x10];
11261	struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
11262	};
11263
11264	struct mlx5_ifc_qpts_reg_bits {
11265	u8 reserved_at_0[0x8];
11266	u8 local_port[0x8];
11267	u8 reserved_at_10[0x2d];
11268	u8 trust_state[0x3];
11269	};
11270
11271	struct mlx5_ifc_pptb_reg_bits {
11272	u8 reserved_at_0[0x2];
11273	u8 mm[0x2];
11274	u8 reserved_at_4[0x4];
11275	u8 local_port[0x8];
11276	u8 reserved_at_10[0x6];
11277	u8 cm[0x1];
11278	u8 um[0x1];
11279	u8 pm[0x8];
11280
11281	u8 prio_x_buff[0x20];
11282
11283	u8 pm_msb[0x8];
11284	u8 reserved_at_48[0x10];
11285	u8 ctrl_buff[0x4];
11286	u8 untagged_buff[0x4];
11287	};
11288
11289	struct mlx5_ifc_sbcam_reg_bits {
11290	u8 reserved_at_0[0x8];
11291	u8 feature_group[0x8];
11292	u8 reserved_at_10[0x8];
11293	u8 access_reg_group[0x8];
11294
11295	u8 reserved_at_20[0x20];
11296
11297	u8 sb_access_reg_cap_mask[4][0x20];
11298
11299	u8 reserved_at_c0[0x80];
11300
11301	u8 sb_feature_cap_mask[4][0x20];
11302
11303	u8 reserved_at_1c0[0x40];
11304
11305	u8 cap_total_buffer_size[0x20];
11306
11307	u8 cap_cell_size[0x10];
11308	u8 cap_max_pg_buffers[0x8];
11309	u8 cap_num_pool_supported[0x8];
11310
11311	u8 reserved_at_240[0x8];
11312	u8 cap_sbsr_stat_size[0x8];
11313	u8 cap_max_tclass_data[0x8];
11314	u8 cap_max_cpu_ingress_tclass_sb[0x8];
11315	};
11316
11317	struct mlx5_ifc_pbmc_reg_bits {
11318	u8 reserved_at_0[0x8];
11319	u8 local_port[0x8];
11320	u8 reserved_at_10[0x10];
11321
11322	u8 xoff_timer_value[0x10];
11323	u8 xoff_refresh[0x10];
11324
11325	u8 reserved_at_40[0x9];
11326	u8 fullness_threshold[0x7];
11327	u8 port_buffer_size[0x10];
11328
11329	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11330
11331	u8 reserved_at_2e0[0x80];
11332	};
11333
11334	struct mlx5_ifc_sbpr_reg_bits {
11335	u8 desc[0x1];
11336	u8 snap[0x1];
11337	u8 reserved_at_2[0x4];
11338	u8 dir[0x2];
11339	u8 reserved_at_8[0x14];
11340	u8 pool[0x4];
11341
11342	u8 infi_size[0x1];
11343	u8 reserved_at_21[0x7];
11344	u8 size[0x18];
11345
11346	u8 reserved_at_40[0x1c];
11347	u8 mode[0x4];
11348
11349	u8 reserved_at_60[0x8];
11350	u8 buff_occupancy[0x18];
11351
11352	u8 clr[0x1];
11353	u8 reserved_at_81[0x7];
11354	u8 max_buff_occupancy[0x18];
11355
11356	u8 reserved_at_a0[0x8];
11357	u8 ext_buff_occupancy[0x18];
11358	};
11359
11360	struct mlx5_ifc_sbcm_reg_bits {
11361	u8 desc[0x1];
11362	u8 snap[0x1];
11363	u8 reserved_at_2[0x6];
11364	u8 local_port[0x8];
11365	u8 pnat[0x2];
11366	u8 pg_buff[0x6];
11367	u8 reserved_at_18[0x6];
11368	u8 dir[0x2];
11369
11370	u8 reserved_at_20[0x1f];
11371	u8 exc[0x1];
11372
11373	u8 reserved_at_40[0x40];
11374
11375	u8 reserved_at_80[0x8];
11376	u8 buff_occupancy[0x18];
11377
11378	u8 clr[0x1];
11379	u8 reserved_at_a1[0x7];
11380	u8 max_buff_occupancy[0x18];
11381
11382	u8 reserved_at_c0[0x8];
11383	u8 min_buff[0x18];
11384
11385	u8 infi_max[0x1];
11386	u8 reserved_at_e1[0x7];
11387	u8 max_buff[0x18];
11388
11389	u8 reserved_at_100[0x20];
11390
11391	u8 reserved_at_120[0x1c];
11392	u8 pool[0x4];
11393	};
11394
11395	struct mlx5_ifc_qtct_reg_bits {
11396	u8 reserved_at_0[0x8];
11397	u8 port_number[0x8];
11398	u8 reserved_at_10[0xd];
11399	u8 prio[0x3];
11400
11401	u8 reserved_at_20[0x1d];
11402	u8 tclass[0x3];
11403	};
11404
11405	struct mlx5_ifc_mcia_reg_bits {
11406	u8 l[0x1];
11407	u8 reserved_at_1[0x7];
11408	u8 module[0x8];
11409	u8 reserved_at_10[0x8];
11410	u8 status[0x8];
11411
11412	u8 i2c_device_address[0x8];
11413	u8 page_number[0x8];
11414	u8 device_address[0x10];
11415
11416	u8 reserved_at_40[0x10];
11417	u8 size[0x10];
11418
11419	u8 reserved_at_60[0x20];
11420
11421	u8 dword_0[0x20];
11422	u8 dword_1[0x20];
11423	u8 dword_2[0x20];
11424	u8 dword_3[0x20];
11425	u8 dword_4[0x20];
11426	u8 dword_5[0x20];
11427	u8 dword_6[0x20];
11428	u8 dword_7[0x20];
11429	u8 dword_8[0x20];
11430	u8 dword_9[0x20];
11431	u8 dword_10[0x20];
11432	u8 dword_11[0x20];
11433	};
11434
11435	struct mlx5_ifc_dcbx_param_bits {
11436	u8 dcbx_cee_cap[0x1];
11437	u8 dcbx_ieee_cap[0x1];
11438	u8 dcbx_standby_cap[0x1];
11439	u8 reserved_at_3[0x5];
11440	u8 port_number[0x8];
11441	u8 reserved_at_10[0xa];
11442	u8 max_application_table_size[6];
11443	u8 reserved_at_20[0x15];
11444	u8 version_oper[0x3];
11445	u8 reserved_at_38[5];
11446	u8 version_admin[0x3];
11447	u8 willing_admin[0x1];
11448	u8 reserved_at_41[0x3];
11449	u8 pfc_cap_oper[0x4];
11450	u8 reserved_at_48[0x4];
11451	u8 pfc_cap_admin[0x4];
11452	u8 reserved_at_50[0x4];
11453	u8 num_of_tc_oper[0x4];
11454	u8 reserved_at_58[0x4];
11455	u8 num_of_tc_admin[0x4];
11456	u8 remote_willing[0x1];
11457	u8 reserved_at_61[3];
11458	u8 remote_pfc_cap[4];
11459	u8 reserved_at_68[0x14];
11460	u8 remote_num_of_tc[0x4];
11461	u8 reserved_at_80[0x18];
11462	u8 error[0x8];
11463	u8 reserved_at_a0[0x160];
11464	};
11465
11466	enum {
11467	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11468	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11469	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11470	};
11471
11472	struct mlx5_ifc_lagc_bits {
11473	u8 fdb_selection_mode[0x1];
11474	u8 reserved_at_1[0x14];
11475	u8 port_select_mode[0x3];
11476	u8 reserved_at_18[0x5];
11477	u8 lag_state[0x3];
11478
11479	u8 reserved_at_20[0xc];
11480	u8 active_port[0x4];
11481	u8 reserved_at_30[0x4];
11482	u8 tx_remap_affinity_2[0x4];
11483	u8 reserved_at_38[0x4];
11484	u8 tx_remap_affinity_1[0x4];
11485	};
11486
11487	struct mlx5_ifc_create_lag_out_bits {
11488	u8 status[0x8];
11489	u8 reserved_at_8[0x18];
11490
11491	u8 syndrome[0x20];
11492
11493	u8 reserved_at_40[0x40];
11494	};
11495
11496	struct mlx5_ifc_create_lag_in_bits {
11497	u8 opcode[0x10];
11498	u8 reserved_at_10[0x10];
11499
11500	u8 reserved_at_20[0x10];
11501	u8 op_mod[0x10];
11502
11503	struct mlx5_ifc_lagc_bits ctx;
11504	};
11505
11506	struct mlx5_ifc_modify_lag_out_bits {
11507	u8 status[0x8];
11508	u8 reserved_at_8[0x18];
11509
11510	u8 syndrome[0x20];
11511
11512	u8 reserved_at_40[0x40];
11513	};
11514
11515	struct mlx5_ifc_modify_lag_in_bits {
11516	u8 opcode[0x10];
11517	u8 reserved_at_10[0x10];
11518
11519	u8 reserved_at_20[0x10];
11520	u8 op_mod[0x10];
11521
11522	u8 reserved_at_40[0x20];
11523	u8 field_select[0x20];
11524
11525	struct mlx5_ifc_lagc_bits ctx;
11526	};
11527
11528	struct mlx5_ifc_query_lag_out_bits {
11529	u8 status[0x8];
11530	u8 reserved_at_8[0x18];
11531
11532	u8 syndrome[0x20];
11533
11534	struct mlx5_ifc_lagc_bits ctx;
11535	};
11536
11537	struct mlx5_ifc_query_lag_in_bits {
11538	u8 opcode[0x10];
11539	u8 reserved_at_10[0x10];
11540
11541	u8 reserved_at_20[0x10];
11542	u8 op_mod[0x10];
11543
11544	u8 reserved_at_40[0x40];
11545	};
11546
11547	struct mlx5_ifc_destroy_lag_out_bits {
11548	u8 status[0x8];
11549	u8 reserved_at_8[0x18];
11550
11551	u8 syndrome[0x20];
11552
11553	u8 reserved_at_40[0x40];
11554	};
11555
11556	struct mlx5_ifc_destroy_lag_in_bits {
11557	u8 opcode[0x10];
11558	u8 reserved_at_10[0x10];
11559
11560	u8 reserved_at_20[0x10];
11561	u8 op_mod[0x10];
11562
11563	u8 reserved_at_40[0x40];
11564	};
11565
11566	struct mlx5_ifc_create_vport_lag_out_bits {
11567	u8 status[0x8];
11568	u8 reserved_at_8[0x18];
11569
11570	u8 syndrome[0x20];
11571
11572	u8 reserved_at_40[0x40];
11573	};
11574
11575	struct mlx5_ifc_create_vport_lag_in_bits {
11576	u8 opcode[0x10];
11577	u8 reserved_at_10[0x10];
11578
11579	u8 reserved_at_20[0x10];
11580	u8 op_mod[0x10];
11581
11582	u8 reserved_at_40[0x40];
11583	};
11584
11585	struct mlx5_ifc_destroy_vport_lag_out_bits {
11586	u8 status[0x8];
11587	u8 reserved_at_8[0x18];
11588
11589	u8 syndrome[0x20];
11590
11591	u8 reserved_at_40[0x40];
11592	};
11593
11594	struct mlx5_ifc_destroy_vport_lag_in_bits {
11595	u8 opcode[0x10];
11596	u8 reserved_at_10[0x10];
11597
11598	u8 reserved_at_20[0x10];
11599	u8 op_mod[0x10];
11600
11601	u8 reserved_at_40[0x40];
11602	};
11603
11604	enum {
11605	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11606	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11607	};
11608
11609	struct mlx5_ifc_modify_memic_in_bits {
11610	u8 opcode[0x10];
11611	u8 uid[0x10];
11612
11613	u8 reserved_at_20[0x10];
11614	u8 op_mod[0x10];
11615
11616	u8 reserved_at_40[0x20];
11617
11618	u8 reserved_at_60[0x18];
11619	u8 memic_operation_type[0x8];
11620
11621	u8 memic_start_addr[0x40];
11622
11623	u8 reserved_at_c0[0x140];
11624	};
11625
11626	struct mlx5_ifc_modify_memic_out_bits {
11627	u8 status[0x8];
11628	u8 reserved_at_8[0x18];
11629
11630	u8 syndrome[0x20];
11631
11632	u8 reserved_at_40[0x40];
11633
11634	u8 memic_operation_addr[0x40];
11635
11636	u8 reserved_at_c0[0x140];
11637	};
11638
11639	struct mlx5_ifc_alloc_memic_in_bits {
11640	u8 opcode[0x10];
11641	u8 reserved_at_10[0x10];
11642
11643	u8 reserved_at_20[0x10];
11644	u8 op_mod[0x10];
11645
11646	u8 reserved_at_30[0x20];
11647
11648	u8 reserved_at_40[0x18];
11649	u8 log_memic_addr_alignment[0x8];
11650
11651	u8 range_start_addr[0x40];
11652
11653	u8 range_size[0x20];
11654
11655	u8 memic_size[0x20];
11656	};
11657
11658	struct mlx5_ifc_alloc_memic_out_bits {
11659	u8 status[0x8];
11660	u8 reserved_at_8[0x18];
11661
11662	u8 syndrome[0x20];
11663
11664	u8 memic_start_addr[0x40];
11665	};
11666
11667	struct mlx5_ifc_dealloc_memic_in_bits {
11668	u8 opcode[0x10];
11669	u8 reserved_at_10[0x10];
11670
11671	u8 reserved_at_20[0x10];
11672	u8 op_mod[0x10];
11673
11674	u8 reserved_at_40[0x40];
11675
11676	u8 memic_start_addr[0x40];
11677
11678	u8 memic_size[0x20];
11679
11680	u8 reserved_at_e0[0x20];
11681	};
11682
11683	struct mlx5_ifc_dealloc_memic_out_bits {
11684	u8 status[0x8];
11685	u8 reserved_at_8[0x18];
11686
11687	u8 syndrome[0x20];
11688
11689	u8 reserved_at_40[0x40];
11690	};
11691
11692	struct mlx5_ifc_umem_bits {
11693	u8 reserved_at_0[0x80];
11694
11695	u8 ats[0x1];
11696	u8 reserved_at_81[0x1a];
11697	u8 log_page_size[0x5];
11698
11699	u8 page_offset[0x20];
11700
11701	u8 num_of_mtt[0x40];
11702
11703	struct mlx5_ifc_mtt_bits mtt[];
11704	};
11705
11706	struct mlx5_ifc_uctx_bits {
11707	u8 cap[0x20];
11708
11709	u8 reserved_at_20[0x160];
11710	};
11711
11712	struct mlx5_ifc_sw_icm_bits {
11713	u8 modify_field_select[0x40];
11714
11715	u8 reserved_at_40[0x18];
11716	u8 log_sw_icm_size[0x8];
11717
11718	u8 reserved_at_60[0x20];
11719
11720	u8 sw_icm_start_addr[0x40];
11721
11722	u8 reserved_at_c0[0x140];
11723	};
11724
11725	struct mlx5_ifc_geneve_tlv_option_bits {
11726	u8 modify_field_select[0x40];
11727
11728	u8 reserved_at_40[0x18];
11729	u8 geneve_option_fte_index[0x8];
11730
11731	u8 option_class[0x10];
11732	u8 option_type[0x8];
11733	u8 reserved_at_78[0x3];
11734	u8 option_data_length[0x5];
11735
11736	u8 reserved_at_80[0x180];
11737	};
11738
11739	struct mlx5_ifc_create_umem_in_bits {
11740	u8 opcode[0x10];
11741	u8 uid[0x10];
11742
11743	u8 reserved_at_20[0x10];
11744	u8 op_mod[0x10];
11745
11746	u8 reserved_at_40[0x40];
11747
11748	struct mlx5_ifc_umem_bits umem;
11749	};
11750
11751	struct mlx5_ifc_create_umem_out_bits {
11752	u8 status[0x8];
11753	u8 reserved_at_8[0x18];
11754
11755	u8 syndrome[0x20];
11756
11757	u8 reserved_at_40[0x8];
11758	u8 umem_id[0x18];
11759
11760	u8 reserved_at_60[0x20];
11761	};
11762
11763	struct mlx5_ifc_destroy_umem_in_bits {
11764	u8 opcode[0x10];
11765	u8 uid[0x10];
11766
11767	u8 reserved_at_20[0x10];
11768	u8 op_mod[0x10];
11769
11770	u8 reserved_at_40[0x8];
11771	u8 umem_id[0x18];
11772
11773	u8 reserved_at_60[0x20];
11774	};
11775
11776	struct mlx5_ifc_destroy_umem_out_bits {
11777	u8 status[0x8];
11778	u8 reserved_at_8[0x18];
11779
11780	u8 syndrome[0x20];
11781
11782	u8 reserved_at_40[0x40];
11783	};
11784
11785	struct mlx5_ifc_create_uctx_in_bits {
11786	u8 opcode[0x10];
11787	u8 reserved_at_10[0x10];
11788
11789	u8 reserved_at_20[0x10];
11790	u8 op_mod[0x10];
11791
11792	u8 reserved_at_40[0x40];
11793
11794	struct mlx5_ifc_uctx_bits uctx;
11795	};
11796
11797	struct mlx5_ifc_create_uctx_out_bits {
11798	u8 status[0x8];
11799	u8 reserved_at_8[0x18];
11800
11801	u8 syndrome[0x20];
11802
11803	u8 reserved_at_40[0x10];
11804	u8 uid[0x10];
11805
11806	u8 reserved_at_60[0x20];
11807	};
11808
11809	struct mlx5_ifc_destroy_uctx_in_bits {
11810	u8 opcode[0x10];
11811	u8 reserved_at_10[0x10];
11812
11813	u8 reserved_at_20[0x10];
11814	u8 op_mod[0x10];
11815
11816	u8 reserved_at_40[0x10];
11817	u8 uid[0x10];
11818
11819	u8 reserved_at_60[0x20];
11820	};
11821
11822	struct mlx5_ifc_destroy_uctx_out_bits {
11823	u8 status[0x8];
11824	u8 reserved_at_8[0x18];
11825
11826	u8 syndrome[0x20];
11827
11828	u8 reserved_at_40[0x40];
11829	};
11830
11831	struct mlx5_ifc_create_sw_icm_in_bits {
11832	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11833	struct mlx5_ifc_sw_icm_bits sw_icm;
11834	};
11835
11836	struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11837	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11838	struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11839	};
11840
11841	struct mlx5_ifc_mtrc_string_db_param_bits {
11842	u8 string_db_base_address[0x20];
11843
11844	u8 reserved_at_20[0x8];
11845	u8 string_db_size[0x18];
11846	};
11847
11848	struct mlx5_ifc_mtrc_cap_bits {
11849	u8 trace_owner[0x1];
11850	u8 trace_to_memory[0x1];
11851	u8 reserved_at_2[0x4];
11852	u8 trc_ver[0x2];
11853	u8 reserved_at_8[0x14];
11854	u8 num_string_db[0x4];
11855
11856	u8 first_string_trace[0x8];
11857	u8 num_string_trace[0x8];
11858	u8 reserved_at_30[0x28];
11859
11860	u8 log_max_trace_buffer_size[0x8];
11861
11862	u8 reserved_at_60[0x20];
11863
11864	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11865
11866	u8 reserved_at_280[0x180];
11867	};
11868
11869	struct mlx5_ifc_mtrc_conf_bits {
11870	u8 reserved_at_0[0x1c];
11871	u8 trace_mode[0x4];
11872	u8 reserved_at_20[0x18];
11873	u8 log_trace_buffer_size[0x8];
11874	u8 trace_mkey[0x20];
11875	u8 reserved_at_60[0x3a0];
11876	};
11877
11878	struct mlx5_ifc_mtrc_stdb_bits {
11879	u8 string_db_index[0x4];
11880	u8 reserved_at_4[0x4];
11881	u8 read_size[0x18];
11882	u8 start_offset[0x20];
11883	u8 string_db_data[];
11884	};
11885
11886	struct mlx5_ifc_mtrc_ctrl_bits {
11887	u8 trace_status[0x2];
11888	u8 reserved_at_2[0x2];
11889	u8 arm_event[0x1];
11890	u8 reserved_at_5[0xb];
11891	u8 modify_field_select[0x10];
11892	u8 reserved_at_20[0x2b];
11893	u8 current_timestamp52_32[0x15];
11894	u8 current_timestamp31_0[0x20];
11895	u8 reserved_at_80[0x180];
11896	};
11897
11898	struct mlx5_ifc_host_params_context_bits {
11899	u8 host_number[0x8];
11900	u8 reserved_at_8[0x7];
11901	u8 host_pf_disabled[0x1];
11902	u8 host_num_of_vfs[0x10];
11903
11904	u8 host_total_vfs[0x10];
11905	u8 host_pci_bus[0x10];
11906
11907	u8 reserved_at_40[0x10];
11908	u8 host_pci_device[0x10];
11909
11910	u8 reserved_at_60[0x10];
11911	u8 host_pci_function[0x10];
11912
11913	u8 reserved_at_80[0x180];
11914	};
11915
11916	struct mlx5_ifc_query_esw_functions_in_bits {
11917	u8 opcode[0x10];
11918	u8 reserved_at_10[0x10];
11919
11920	u8 reserved_at_20[0x10];
11921	u8 op_mod[0x10];
11922
11923	u8 reserved_at_40[0x40];
11924	};
11925
11926	struct mlx5_ifc_query_esw_functions_out_bits {
11927	u8 status[0x8];
11928	u8 reserved_at_8[0x18];
11929
11930	u8 syndrome[0x20];
11931
11932	u8 reserved_at_40[0x40];
11933
11934	struct mlx5_ifc_host_params_context_bits host_params_context;
11935
11936	u8 reserved_at_280[0x180];
11937	u8 host_sf_enable[][0x40];
11938	};
11939
11940	struct mlx5_ifc_sf_partition_bits {
11941	u8 reserved_at_0[0x10];
11942	u8 log_num_sf[0x8];
11943	u8 log_sf_bar_size[0x8];
11944	};
11945
11946	struct mlx5_ifc_query_sf_partitions_out_bits {
11947	u8 status[0x8];
11948	u8 reserved_at_8[0x18];
11949
11950	u8 syndrome[0x20];
11951
11952	u8 reserved_at_40[0x18];
11953	u8 num_sf_partitions[0x8];
11954
11955	u8 reserved_at_60[0x20];
11956
11957	struct mlx5_ifc_sf_partition_bits sf_partition[];
11958	};
11959
11960	struct mlx5_ifc_query_sf_partitions_in_bits {
11961	u8 opcode[0x10];
11962	u8 reserved_at_10[0x10];
11963
11964	u8 reserved_at_20[0x10];
11965	u8 op_mod[0x10];
11966
11967	u8 reserved_at_40[0x40];
11968	};
11969
11970	struct mlx5_ifc_dealloc_sf_out_bits {
11971	u8 status[0x8];
11972	u8 reserved_at_8[0x18];
11973
11974	u8 syndrome[0x20];
11975
11976	u8 reserved_at_40[0x40];
11977	};
11978
11979	struct mlx5_ifc_dealloc_sf_in_bits {
11980	u8 opcode[0x10];
11981	u8 reserved_at_10[0x10];
11982
11983	u8 reserved_at_20[0x10];
11984	u8 op_mod[0x10];
11985
11986	u8 reserved_at_40[0x10];
11987	u8 function_id[0x10];
11988
11989	u8 reserved_at_60[0x20];
11990	};
11991
11992	struct mlx5_ifc_alloc_sf_out_bits {
11993	u8 status[0x8];
11994	u8 reserved_at_8[0x18];
11995
11996	u8 syndrome[0x20];
11997
11998	u8 reserved_at_40[0x40];
11999	};
12000
12001	struct mlx5_ifc_alloc_sf_in_bits {
12002	u8 opcode[0x10];
12003	u8 reserved_at_10[0x10];
12004
12005	u8 reserved_at_20[0x10];
12006	u8 op_mod[0x10];
12007
12008	u8 reserved_at_40[0x10];
12009	u8 function_id[0x10];
12010
12011	u8 reserved_at_60[0x20];
12012	};
12013
12014	struct mlx5_ifc_affiliated_event_header_bits {
12015	u8 reserved_at_0[0x10];
12016	u8 obj_type[0x10];
12017
12018	u8 obj_id[0x20];
12019	};
12020
12021	enum {
12022	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12023	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12024	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12025	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12026	};
12027
12028	enum {
12029	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12030	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12031	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12032	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12033	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12034	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12035	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12036	};
12037
12038	enum {
12039	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12040	};
12041
12042	enum {
12043	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12044	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12045	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12046	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12047	};
12048
12049	enum {
12050	MLX5_IPSEC_ASO_MODE = 0x0,
12051	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12052	MLX5_IPSEC_ASO_INC_SN = 0x2,
12053	};
12054
12055	enum {
12056	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12057	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12058	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12059	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12060	};
12061
12062	struct mlx5_ifc_ipsec_aso_bits {
12063	u8 valid[0x1];
12064	u8 reserved_at_201[0x1];
12065	u8 mode[0x2];
12066	u8 window_sz[0x2];
12067	u8 soft_lft_arm[0x1];
12068	u8 hard_lft_arm[0x1];
12069	u8 remove_flow_enable[0x1];
12070	u8 esn_event_arm[0x1];
12071	u8 reserved_at_20a[0x16];
12072
12073	u8 remove_flow_pkt_cnt[0x20];
12074
12075	u8 remove_flow_soft_lft[0x20];
12076
12077	u8 reserved_at_260[0x80];
12078
12079	u8 mode_parameter[0x20];
12080
12081	u8 replay_protection_window[0x100];
12082	};
12083
12084	struct mlx5_ifc_ipsec_obj_bits {
12085	u8 modify_field_select[0x40];
12086	u8 full_offload[0x1];
12087	u8 reserved_at_41[0x1];
12088	u8 esn_en[0x1];
12089	u8 esn_overlap[0x1];
12090	u8 reserved_at_44[0x2];
12091	u8 icv_length[0x2];
12092	u8 reserved_at_48[0x4];
12093	u8 aso_return_reg[0x4];
12094	u8 reserved_at_50[0x10];
12095
12096	u8 esn_msb[0x20];
12097
12098	u8 reserved_at_80[0x8];
12099	u8 dekn[0x18];
12100
12101	u8 salt[0x20];
12102
12103	u8 implicit_iv[0x40];
12104
12105	u8 reserved_at_100[0x8];
12106	u8 ipsec_aso_access_pd[0x18];
12107	u8 reserved_at_120[0xe0];
12108
12109	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12110	};
12111
12112	struct mlx5_ifc_create_ipsec_obj_in_bits {
12113	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12114	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12115	};
12116
12117	enum {
12118	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12119	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12120	};
12121
12122	struct mlx5_ifc_query_ipsec_obj_out_bits {
12123	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12124	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12125	};
12126
12127	struct mlx5_ifc_modify_ipsec_obj_in_bits {
12128	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12129	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12130	};
12131
12132	enum {
12133	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12134	};
12135
12136	enum {
12137	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12138	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12139	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12140	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12141	};
12142
12143	#define MLX5_MACSEC_ASO_INC_SN 0x2
12144	#define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12145
12146	struct mlx5_ifc_macsec_aso_bits {
12147	u8 valid[0x1];
12148	u8 reserved_at_1[0x1];
12149	u8 mode[0x2];
12150	u8 window_size[0x2];
12151	u8 soft_lifetime_arm[0x1];
12152	u8 hard_lifetime_arm[0x1];
12153	u8 remove_flow_enable[0x1];
12154	u8 epn_event_arm[0x1];
12155	u8 reserved_at_a[0x16];
12156
12157	u8 remove_flow_packet_count[0x20];
12158
12159	u8 remove_flow_soft_lifetime[0x20];
12160
12161	u8 reserved_at_60[0x80];
12162
12163	u8 mode_parameter[0x20];
12164
12165	u8 replay_protection_window[8][0x20];
12166	};
12167
12168	struct mlx5_ifc_macsec_offload_obj_bits {
12169	u8 modify_field_select[0x40];
12170
12171	u8 confidentiality_en[0x1];
12172	u8 reserved_at_41[0x1];
12173	u8 epn_en[0x1];
12174	u8 epn_overlap[0x1];
12175	u8 reserved_at_44[0x2];
12176	u8 confidentiality_offset[0x2];
12177	u8 reserved_at_48[0x4];
12178	u8 aso_return_reg[0x4];
12179	u8 reserved_at_50[0x10];
12180
12181	u8 epn_msb[0x20];
12182
12183	u8 reserved_at_80[0x8];
12184	u8 dekn[0x18];
12185
12186	u8 reserved_at_a0[0x20];
12187
12188	u8 sci[0x40];
12189
12190	u8 reserved_at_100[0x8];
12191	u8 macsec_aso_access_pd[0x18];
12192
12193	u8 reserved_at_120[0x60];
12194
12195	u8 salt[3][0x20];
12196
12197	u8 reserved_at_1e0[0x20];
12198
12199	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12200	};
12201
12202	struct mlx5_ifc_create_macsec_obj_in_bits {
12203	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12204	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12205	};
12206
12207	struct mlx5_ifc_modify_macsec_obj_in_bits {
12208	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12209	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12210	};
12211
12212	enum {
12213	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12214	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12215	};
12216
12217	struct mlx5_ifc_query_macsec_obj_out_bits {
12218	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12219	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12220	};
12221
12222	struct mlx5_ifc_wrapped_dek_bits {
12223	u8 gcm_iv[0x60];
12224
12225	u8 reserved_at_60[0x20];
12226
12227	u8 const0[0x1];
12228	u8 key_size[0x1];
12229	u8 reserved_at_82[0x2];
12230	u8 key2_invalid[0x1];
12231	u8 reserved_at_85[0x3];
12232	u8 pd[0x18];
12233
12234	u8 key_purpose[0x5];
12235	u8 reserved_at_a5[0x13];
12236	u8 kek_id[0x8];
12237
12238	u8 reserved_at_c0[0x40];
12239
12240	u8 key1[0x8][0x20];
12241
12242	u8 key2[0x8][0x20];
12243
12244	u8 reserved_at_300[0x40];
12245
12246	u8 const1[0x1];
12247	u8 reserved_at_341[0x1f];
12248
12249	u8 reserved_at_360[0x20];
12250
12251	u8 auth_tag[0x80];
12252	};
12253
12254	struct mlx5_ifc_encryption_key_obj_bits {
12255	u8 modify_field_select[0x40];
12256
12257	u8 state[0x8];
12258	u8 sw_wrapped[0x1];
12259	u8 reserved_at_49[0xb];
12260	u8 key_size[0x4];
12261	u8 reserved_at_58[0x4];
12262	u8 key_purpose[0x4];
12263
12264	u8 reserved_at_60[0x8];
12265	u8 pd[0x18];
12266
12267	u8 reserved_at_80[0x100];
12268
12269	u8 opaque[0x40];
12270
12271	u8 reserved_at_1c0[0x40];
12272
12273	u8 key[8][0x80];
12274
12275	u8 sw_wrapped_dek[8][0x80];
12276
12277	u8 reserved_at_a00[0x600];
12278	};
12279
12280	struct mlx5_ifc_create_encryption_key_in_bits {
12281	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12282	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12283	};
12284
12285	struct mlx5_ifc_modify_encryption_key_in_bits {
12286	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12287	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12288	};
12289
12290	enum {
12291	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
12292	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
12293	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
12294	MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
12295	};
12296
12297	struct mlx5_ifc_flow_meter_parameters_bits {
12298	u8 valid[0x1];
12299	u8 bucket_overflow[0x1];
12300	u8 start_color[0x2];
12301	u8 both_buckets_on_green[0x1];
12302	u8 reserved_at_5[0x1];
12303	u8 meter_mode[0x2];
12304	u8 reserved_at_8[0x18];
12305
12306	u8 reserved_at_20[0x20];
12307
12308	u8 reserved_at_40[0x3];
12309	u8 cbs_exponent[0x5];
12310	u8 cbs_mantissa[0x8];
12311	u8 reserved_at_50[0x3];
12312	u8 cir_exponent[0x5];
12313	u8 cir_mantissa[0x8];
12314
12315	u8 reserved_at_60[0x20];
12316
12317	u8 reserved_at_80[0x3];
12318	u8 ebs_exponent[0x5];
12319	u8 ebs_mantissa[0x8];
12320	u8 reserved_at_90[0x3];
12321	u8 eir_exponent[0x5];
12322	u8 eir_mantissa[0x8];
12323
12324	u8 reserved_at_a0[0x60];
12325	};
12326
12327	struct mlx5_ifc_flow_meter_aso_obj_bits {
12328	u8 modify_field_select[0x40];
12329
12330	u8 reserved_at_40[0x40];
12331
12332	u8 reserved_at_80[0x8];
12333	u8 meter_aso_access_pd[0x18];
12334
12335	u8 reserved_at_a0[0x160];
12336
12337	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12338	};
12339
12340	struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12341	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12342	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12343	};
12344
12345	struct mlx5_ifc_int_kek_obj_bits {
12346	u8 modify_field_select[0x40];
12347
12348	u8 state[0x8];
12349	u8 auto_gen[0x1];
12350	u8 reserved_at_49[0xb];
12351	u8 key_size[0x4];
12352	u8 reserved_at_58[0x8];
12353
12354	u8 reserved_at_60[0x8];
12355	u8 pd[0x18];
12356
12357	u8 reserved_at_80[0x180];
12358	u8 key[8][0x80];
12359
12360	u8 reserved_at_600[0x200];
12361	};
12362
12363	struct mlx5_ifc_create_int_kek_obj_in_bits {
12364	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12365	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12366	};
12367
12368	struct mlx5_ifc_create_int_kek_obj_out_bits {
12369	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12370	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12371	};
12372
12373	struct mlx5_ifc_sampler_obj_bits {
12374	u8 modify_field_select[0x40];
12375
12376	u8 table_type[0x8];
12377	u8 level[0x8];
12378	u8 reserved_at_50[0xf];
12379	u8 ignore_flow_level[0x1];
12380
12381	u8 sample_ratio[0x20];
12382
12383	u8 reserved_at_80[0x8];
12384	u8 sample_table_id[0x18];
12385
12386	u8 reserved_at_a0[0x8];
12387	u8 default_table_id[0x18];
12388
12389	u8 sw_steering_icm_address_rx[0x40];
12390	u8 sw_steering_icm_address_tx[0x40];
12391
12392	u8 reserved_at_140[0xa0];
12393	};
12394
12395	struct mlx5_ifc_create_sampler_obj_in_bits {
12396	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12397	struct mlx5_ifc_sampler_obj_bits sampler_object;
12398	};
12399
12400	struct mlx5_ifc_query_sampler_obj_out_bits {
12401	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12402	struct mlx5_ifc_sampler_obj_bits sampler_object;
12403	};
12404
12405	enum {
12406	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12407	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12408	};
12409
12410	enum {
12411	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12412	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12413	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12414	};
12415
12416	struct mlx5_ifc_tls_static_params_bits {
12417	u8 const_2[0x2];
12418	u8 tls_version[0x4];
12419	u8 const_1[0x2];
12420	u8 reserved_at_8[0x14];
12421	u8 encryption_standard[0x4];
12422
12423	u8 reserved_at_20[0x20];
12424
12425	u8 initial_record_number[0x40];
12426
12427	u8 resync_tcp_sn[0x20];
12428
12429	u8 gcm_iv[0x20];
12430
12431	u8 implicit_iv[0x40];
12432
12433	u8 reserved_at_100[0x8];
12434	u8 dek_index[0x18];
12435
12436	u8 reserved_at_120[0xe0];
12437	};
12438
12439	struct mlx5_ifc_tls_progress_params_bits {
12440	u8 next_record_tcp_sn[0x20];
12441
12442	u8 hw_resync_tcp_sn[0x20];
12443
12444	u8 record_tracker_state[0x2];
12445	u8 auth_state[0x2];
12446	u8 reserved_at_44[0x4];
12447	u8 hw_offset_record_number[0x18];
12448	};
12449
12450	enum {
12451	MLX5_MTT_PERM_READ = 1 << 0,
12452	MLX5_MTT_PERM_WRITE = 1 << 1,
12453	MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12454	};
12455
12456	enum {
12457	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
12458	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
12459	};
12460
12461	struct mlx5_ifc_suspend_vhca_in_bits {
12462	u8 opcode[0x10];
12463	u8 uid[0x10];
12464
12465	u8 reserved_at_20[0x10];
12466	u8 op_mod[0x10];
12467
12468	u8 reserved_at_40[0x10];
12469	u8 vhca_id[0x10];
12470
12471	u8 reserved_at_60[0x20];
12472	};
12473
12474	struct mlx5_ifc_suspend_vhca_out_bits {
12475	u8 status[0x8];
12476	u8 reserved_at_8[0x18];
12477
12478	u8 syndrome[0x20];
12479
12480	u8 reserved_at_40[0x40];
12481	};
12482
12483	enum {
12484	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
12485	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
12486	};
12487
12488	struct mlx5_ifc_resume_vhca_in_bits {
12489	u8 opcode[0x10];
12490	u8 uid[0x10];
12491
12492	u8 reserved_at_20[0x10];
12493	u8 op_mod[0x10];
12494
12495	u8 reserved_at_40[0x10];
12496	u8 vhca_id[0x10];
12497
12498	u8 reserved_at_60[0x20];
12499	};
12500
12501	struct mlx5_ifc_resume_vhca_out_bits {
12502	u8 status[0x8];
12503	u8 reserved_at_8[0x18];
12504
12505	u8 syndrome[0x20];
12506
12507	u8 reserved_at_40[0x40];
12508	};
12509
12510	struct mlx5_ifc_query_vhca_migration_state_in_bits {
12511	u8 opcode[0x10];
12512	u8 uid[0x10];
12513
12514	u8 reserved_at_20[0x10];
12515	u8 op_mod[0x10];
12516
12517	u8 incremental[0x1];
12518	u8 chunk[0x1];
12519	u8 reserved_at_42[0xe];
12520	u8 vhca_id[0x10];
12521
12522	u8 reserved_at_60[0x20];
12523	};
12524
12525	struct mlx5_ifc_query_vhca_migration_state_out_bits {
12526	u8 status[0x8];
12527	u8 reserved_at_8[0x18];
12528
12529	u8 syndrome[0x20];
12530
12531	u8 reserved_at_40[0x40];
12532
12533	u8 required_umem_size[0x20];
12534
12535	u8 reserved_at_a0[0x20];
12536
12537	u8 remaining_total_size[0x40];
12538
12539	u8 reserved_at_100[0x100];
12540	};
12541
12542	struct mlx5_ifc_save_vhca_state_in_bits {
12543	u8 opcode[0x10];
12544	u8 uid[0x10];
12545
12546	u8 reserved_at_20[0x10];
12547	u8 op_mod[0x10];
12548
12549	u8 incremental[0x1];
12550	u8 set_track[0x1];
12551	u8 reserved_at_42[0xe];
12552	u8 vhca_id[0x10];
12553
12554	u8 reserved_at_60[0x20];
12555
12556	u8 va[0x40];
12557
12558	u8 mkey[0x20];
12559
12560	u8 size[0x20];
12561	};
12562
12563	struct mlx5_ifc_save_vhca_state_out_bits {
12564	u8 status[0x8];
12565	u8 reserved_at_8[0x18];
12566
12567	u8 syndrome[0x20];
12568
12569	u8 actual_image_size[0x20];
12570
12571	u8 next_required_umem_size[0x20];
12572	};
12573
12574	struct mlx5_ifc_load_vhca_state_in_bits {
12575	u8 opcode[0x10];
12576	u8 uid[0x10];
12577
12578	u8 reserved_at_20[0x10];
12579	u8 op_mod[0x10];
12580
12581	u8 reserved_at_40[0x10];
12582	u8 vhca_id[0x10];
12583
12584	u8 reserved_at_60[0x20];
12585
12586	u8 va[0x40];
12587
12588	u8 mkey[0x20];
12589
12590	u8 size[0x20];
12591	};
12592
12593	struct mlx5_ifc_load_vhca_state_out_bits {
12594	u8 status[0x8];
12595	u8 reserved_at_8[0x18];
12596
12597	u8 syndrome[0x20];
12598
12599	u8 reserved_at_40[0x40];
12600	};
12601
12602	struct mlx5_ifc_adv_virtualization_cap_bits {
12603	u8 reserved_at_0[0x3];
12604	u8 pg_track_log_max_num[0x5];
12605	u8 pg_track_max_num_range[0x8];
12606	u8 pg_track_log_min_addr_space[0x8];
12607	u8 pg_track_log_max_addr_space[0x8];
12608
12609	u8 reserved_at_20[0x3];
12610	u8 pg_track_log_min_msg_size[0x5];
12611	u8 reserved_at_28[0x3];
12612	u8 pg_track_log_max_msg_size[0x5];
12613	u8 reserved_at_30[0x3];
12614	u8 pg_track_log_min_page_size[0x5];
12615	u8 reserved_at_38[0x3];
12616	u8 pg_track_log_max_page_size[0x5];
12617
12618	u8 reserved_at_40[0x7c0];
12619	};
12620
12621	struct mlx5_ifc_page_track_report_entry_bits {
12622	u8 dirty_address_high[0x20];
12623
12624	u8 dirty_address_low[0x20];
12625	};
12626
12627	enum {
12628	MLX5_PAGE_TRACK_STATE_TRACKING,
12629	MLX5_PAGE_TRACK_STATE_REPORTING,
12630	MLX5_PAGE_TRACK_STATE_ERROR,
12631	};
12632
12633	struct mlx5_ifc_page_track_range_bits {
12634	u8 start_address[0x40];
12635
12636	u8 length[0x40];
12637	};
12638
12639	struct mlx5_ifc_page_track_bits {
12640	u8 modify_field_select[0x40];
12641
12642	u8 reserved_at_40[0x10];
12643	u8 vhca_id[0x10];
12644
12645	u8 reserved_at_60[0x20];
12646
12647	u8 state[0x4];
12648	u8 track_type[0x4];
12649	u8 log_addr_space_size[0x8];
12650	u8 reserved_at_90[0x3];
12651	u8 log_page_size[0x5];
12652	u8 reserved_at_98[0x3];
12653	u8 log_msg_size[0x5];
12654
12655	u8 reserved_at_a0[0x8];
12656	u8 reporting_qpn[0x18];
12657
12658	u8 reserved_at_c0[0x18];
12659	u8 num_ranges[0x8];
12660
12661	u8 reserved_at_e0[0x20];
12662
12663	u8 range_start_address[0x40];
12664
12665	u8 length[0x40];
12666
12667	struct mlx5_ifc_page_track_range_bits track_range[0];
12668	};
12669
12670	struct mlx5_ifc_create_page_track_obj_in_bits {
12671	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12672	struct mlx5_ifc_page_track_bits obj_context;
12673	};
12674
12675	struct mlx5_ifc_modify_page_track_obj_in_bits {
12676	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12677	struct mlx5_ifc_page_track_bits obj_context;
12678	};
12679
12680	struct mlx5_ifc_query_page_track_obj_out_bits {
12681	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12682	struct mlx5_ifc_page_track_bits obj_context;
12683	};
12684
12685	struct mlx5_ifc_msecq_reg_bits {
12686	u8 reserved_at_0[0x20];
12687
12688	u8 reserved_at_20[0x12];
12689	u8 network_option[0x2];
12690	u8 local_ssm_code[0x4];
12691	u8 local_enhanced_ssm_code[0x8];
12692
12693	u8 local_clock_identity[0x40];
12694
12695	u8 reserved_at_80[0x180];
12696	};
12697
12698	enum {
12699	MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0),
12700	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1),
12701	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2),
12702	};
12703
12704	enum mlx5_msees_admin_status {
12705	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0,
12706	MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1,
12707	};
12708
12709	enum mlx5_msees_oper_status {
12710	MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0,
12711	MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1,
12712	MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2,
12713	MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3,
12714	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4,
12715	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5,
12716	};
12717
12718	enum mlx5_msees_failure_reason {
12719	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0,
12720	MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1,
12721	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2,
12722	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3,
12723	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4,
12724	};
12725
12726	struct mlx5_ifc_msees_reg_bits {
12727	u8 reserved_at_0[0x8];
12728	u8 local_port[0x8];
12729	u8 pnat[0x2];
12730	u8 lp_msb[0x2];
12731	u8 reserved_at_14[0xc];
12732
12733	u8 field_select[0x20];
12734
12735	u8 admin_status[0x4];
12736	u8 oper_status[0x4];
12737	u8 ho_acq[0x1];
12738	u8 reserved_at_49[0xc];
12739	u8 admin_freq_measure[0x1];
12740	u8 oper_freq_measure[0x1];
12741	u8 failure_reason[0x9];
12742
12743	u8 frequency_diff[0x20];
12744
12745	u8 reserved_at_80[0x180];
12746	};
12747
12748	#endif /* MLX5_IFC_H */
12749