1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (C) 2018 SiFive |
4 | * Copyright (C) 2018 Andes Technology Corporation |
5 | * Copyright (C) 2021 Western Digital Corporation or its affiliates. |
6 | * |
7 | */ |
8 | |
9 | #ifndef _RISCV_PMU_H |
10 | #define _RISCV_PMU_H |
11 | |
12 | #include <linux/perf_event.h> |
13 | #include <linux/ptrace.h> |
14 | #include <linux/interrupt.h> |
15 | |
16 | #ifdef CONFIG_RISCV_PMU |
17 | |
18 | /* |
19 | * The RISCV_MAX_COUNTERS parameter should be specified. |
20 | */ |
21 | |
22 | #define RISCV_MAX_COUNTERS 64 |
23 | #define RISCV_OP_UNSUPP (-EOPNOTSUPP) |
24 | #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" |
25 | #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" |
26 | |
27 | #define RISCV_PMU_STOP_FLAG_RESET 1 |
28 | |
29 | #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 |
30 | |
31 | struct cpu_hw_events { |
32 | /* currently enabled events */ |
33 | int n_events; |
34 | /* Counter overflow interrupt */ |
35 | int irq; |
36 | /* currently enabled events */ |
37 | struct perf_event *events[RISCV_MAX_COUNTERS]; |
38 | /* currently enabled hardware counters */ |
39 | DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS); |
40 | /* currently enabled firmware counters */ |
41 | DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS); |
42 | }; |
43 | |
44 | struct riscv_pmu { |
45 | struct pmu pmu; |
46 | char *name; |
47 | |
48 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
49 | |
50 | unsigned long cmask; |
51 | u64 (*ctr_read)(struct perf_event *event); |
52 | int (*ctr_get_idx)(struct perf_event *event); |
53 | int (*ctr_get_width)(int idx); |
54 | void (*ctr_clear_idx)(struct perf_event *event); |
55 | void (*ctr_start)(struct perf_event *event, u64 init_val); |
56 | void (*ctr_stop)(struct perf_event *event, unsigned long flag); |
57 | int (*event_map)(struct perf_event *event, u64 *config); |
58 | void (*event_init)(struct perf_event *event); |
59 | void (*event_mapped)(struct perf_event *event, struct mm_struct *mm); |
60 | void (*event_unmapped)(struct perf_event *event, struct mm_struct *mm); |
61 | uint8_t (*csr_index)(struct perf_event *event); |
62 | |
63 | struct cpu_hw_events __percpu *hw_events; |
64 | struct hlist_node node; |
65 | struct notifier_block riscv_pm_nb; |
66 | }; |
67 | |
68 | #define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu)) |
69 | |
70 | void riscv_pmu_start(struct perf_event *event, int flags); |
71 | void riscv_pmu_stop(struct perf_event *event, int flags); |
72 | unsigned long riscv_pmu_ctr_read_csr(unsigned long csr); |
73 | int riscv_pmu_event_set_period(struct perf_event *event); |
74 | uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event); |
75 | u64 riscv_pmu_event_update(struct perf_event *event); |
76 | #ifdef CONFIG_RISCV_PMU_LEGACY |
77 | void riscv_pmu_legacy_skip_init(void); |
78 | #else |
79 | static inline void riscv_pmu_legacy_skip_init(void) {}; |
80 | #endif |
81 | struct riscv_pmu *riscv_pmu_alloc(void); |
82 | #ifdef CONFIG_RISCV_PMU_SBI |
83 | int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); |
84 | #endif |
85 | |
86 | #endif /* CONFIG_RISCV_PMU */ |
87 | |
88 | #endif /* _RISCV_PMU_H */ |
89 | |