1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2021 MediaTek Inc. |
4 | */ |
5 | |
6 | #ifndef __LINUX_REGULATOR_MT6315_H |
7 | #define __LINUX_REGULATOR_MT6315_H |
8 | |
9 | #define MT6315_RP 3 |
10 | #define MT6315_PP 6 |
11 | #define MT6315_SP 7 |
12 | |
13 | enum { |
14 | MT6315_VBUCK1 = 0, |
15 | MT6315_VBUCK2, |
16 | MT6315_VBUCK3, |
17 | MT6315_VBUCK4, |
18 | MT6315_VBUCK_MAX, |
19 | }; |
20 | |
21 | /* Register */ |
22 | #define MT6315_TOP2_ELR7 0x139 |
23 | #define MT6315_TOP_TMA_KEY 0x39F |
24 | #define MT6315_TOP_TMA_KEY_H 0x3A0 |
25 | #define MT6315_BUCK_TOP_CON0 0x1440 |
26 | #define MT6315_BUCK_TOP_CON1 0x1443 |
27 | #define MT6315_BUCK_TOP_ELR0 0x1449 |
28 | #define MT6315_BUCK_TOP_ELR2 0x144B |
29 | #define MT6315_BUCK_TOP_ELR4 0x144D |
30 | #define MT6315_BUCK_TOP_ELR6 0x144F |
31 | #define MT6315_VBUCK1_DBG0 0x1499 |
32 | #define MT6315_VBUCK1_DBG4 0x149D |
33 | #define MT6315_VBUCK2_DBG0 0x1519 |
34 | #define MT6315_VBUCK2_DBG4 0x151D |
35 | #define MT6315_VBUCK3_DBG0 0x1599 |
36 | #define MT6315_VBUCK3_DBG4 0x159D |
37 | #define MT6315_VBUCK4_DBG0 0x1619 |
38 | #define MT6315_VBUCK4_DBG4 0x161D |
39 | #define MT6315_BUCK_TOP_4PHASE_ANA_CON42 0x16B1 |
40 | |
41 | #define PROTECTION_KEY_H 0x9C |
42 | #define PROTECTION_KEY 0xEA |
43 | |
44 | #endif /* __LINUX_REGULATOR_MT6315_H */ |
45 | |