1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __ASM_MACH_CPUTYPE_H |
3 | #define __ASM_MACH_CPUTYPE_H |
4 | |
5 | #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) |
6 | #include <asm/cputype.h> |
7 | #endif |
8 | |
9 | /* |
10 | * CPU Stepping CPU_ID CHIP_ID |
11 | * |
12 | * PXA168 S0 0x56158400 0x0000C910 |
13 | * PXA168 A0 0x56158400 0x00A0A168 |
14 | * PXA910 Y1 0x56158400 0x00F2C920 |
15 | * PXA910 A0 0x56158400 0x00F2C910 |
16 | * PXA910 A1 0x56158400 0x00A0C910 |
17 | * PXA920 Y0 0x56158400 0x00F2C920 |
18 | * PXA920 A0 0x56158400 0x00A0C920 |
19 | * PXA920 A1 0x56158400 0x00A1C920 |
20 | * MMP2 Z0 0x560f5811 0x00F00410 |
21 | * MMP2 Z1 0x560f5811 0x00E00410 |
22 | * MMP2 A0 0x560f5811 0x00A0A610 |
23 | * MMP3 A0 0x562f5842 0x00A02128 |
24 | * MMP3 B0 0x562f5842 0x00B02128 |
25 | */ |
26 | |
27 | extern unsigned int mmp_chip_id; |
28 | |
29 | #if defined(CONFIG_MACH_MMP2_DT) |
30 | static inline int cpu_is_mmp2(void) |
31 | { |
32 | return (((read_cpuid_id() >> 8) & 0xff) == 0x58) && |
33 | (((mmp_chip_id & 0xfff) == 0x410) || |
34 | ((mmp_chip_id & 0xfff) == 0x610)); |
35 | } |
36 | #else |
37 | #define cpu_is_mmp2() (0) |
38 | #endif |
39 | |
40 | #ifdef CONFIG_MACH_MMP3_DT |
41 | static inline int cpu_is_mmp3(void) |
42 | { |
43 | return (((read_cpuid_id() >> 8) & 0xff) == 0x58) && |
44 | ((mmp_chip_id & 0xffff) == 0x2128); |
45 | } |
46 | |
47 | static inline int cpu_is_mmp3_a0(void) |
48 | { |
49 | return (cpu_is_mmp3() && |
50 | ((mmp_chip_id & 0x00ff0000) == 0x00a00000)); |
51 | } |
52 | |
53 | static inline int cpu_is_mmp3_b0(void) |
54 | { |
55 | return (cpu_is_mmp3() && |
56 | ((mmp_chip_id & 0x00ff0000) == 0x00b00000)); |
57 | } |
58 | |
59 | #else |
60 | #define cpu_is_mmp3() (0) |
61 | #define cpu_is_mmp3_a0() (0) |
62 | #define cpu_is_mmp3_b0() (0) |
63 | #endif |
64 | |
65 | #endif /* __ASM_MACH_CPUTYPE_H */ |
66 | |