| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2018 Samsung Electronics Co., Ltd. |
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| 4 | * http://www.samsung.com/ |
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| 5 | * |
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| 6 | * Exynos - CHIPID support |
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| 7 | */ |
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| 8 | #ifndef __LINUX_SOC_EXYNOS_CHIPID_H |
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| 9 | #define __LINUX_SOC_EXYNOS_CHIPID_H |
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| 10 | |
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| 11 | #define EXYNOS_CHIPID_REG_PRO_ID 0x00 |
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| 12 | #define EXYNOS_REV_PART_MASK 0xf |
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| 13 | #define EXYNOS_REV_PART_SHIFT 4 |
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| 14 | #define EXYNOS_MASK 0xfffff000 |
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| 15 | |
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| 16 | #define EXYNOS_CHIPID_REG_PKG_ID 0x04 |
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| 17 | /* Bit field definitions for EXYNOS_CHIPID_REG_PKG_ID register */ |
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| 18 | #define EXYNOS5422_IDS_OFFSET 24 |
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| 19 | #define EXYNOS5422_IDS_MASK 0xff |
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| 20 | #define EXYNOS5422_USESG_OFFSET 3 |
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| 21 | #define EXYNOS5422_USESG_MASK 0x01 |
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| 22 | #define EXYNOS5422_SG_OFFSET 0 |
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| 23 | #define EXYNOS5422_SG_MASK 0x07 |
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| 24 | #define EXYNOS5422_TABLE_OFFSET 8 |
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| 25 | #define EXYNOS5422_TABLE_MASK 0x03 |
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| 26 | #define EXYNOS5422_SG_A_OFFSET 17 |
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| 27 | #define EXYNOS5422_SG_A_MASK 0x0f |
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| 28 | #define EXYNOS5422_SG_B_OFFSET 21 |
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| 29 | #define EXYNOS5422_SG_B_MASK 0x03 |
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| 30 | #define EXYNOS5422_SG_BSIGN_OFFSET 23 |
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| 31 | #define EXYNOS5422_SG_BSIGN_MASK 0x01 |
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| 32 | #define EXYNOS5422_BIN2_OFFSET 12 |
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| 33 | #define EXYNOS5422_BIN2_MASK 0x01 |
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| 34 | |
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| 35 | #define EXYNOS_CHIPID_REG_LOT_ID 0x14 |
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| 36 | |
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| 37 | #define EXYNOS_CHIPID_REG_AUX_INFO 0x1c |
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| 38 | /* Bit field definitions for EXYNOS_CHIPID_REG_AUX_INFO register */ |
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| 39 | #define EXYNOS5422_TMCB_OFFSET 0 |
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| 40 | #define EXYNOS5422_TMCB_MASK 0x7f |
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| 41 | #define EXYNOS5422_ARM_UP_OFFSET 8 |
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| 42 | #define EXYNOS5422_ARM_UP_MASK 0x03 |
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| 43 | #define EXYNOS5422_ARM_DN_OFFSET 10 |
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| 44 | #define EXYNOS5422_ARM_DN_MASK 0x03 |
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| 45 | #define EXYNOS5422_KFC_UP_OFFSET 12 |
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| 46 | #define EXYNOS5422_KFC_UP_MASK 0x03 |
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| 47 | #define EXYNOS5422_KFC_DN_OFFSET 14 |
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| 48 | #define EXYNOS5422_KFC_DN_MASK 0x03 |
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| 49 | |
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| 50 | #endif /*__LINUX_SOC_EXYNOS_CHIPID_H */ |
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| 51 | |
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