1 | /* SPDX-License-Identifier: GPL-2.0-or-later |
2 | * |
3 | * Copyright (C) 2005 David Brownell |
4 | */ |
5 | |
6 | #ifndef __LINUX_SPI_H |
7 | #define __LINUX_SPI_H |
8 | |
9 | #include <linux/acpi.h> |
10 | #include <linux/bits.h> |
11 | #include <linux/completion.h> |
12 | #include <linux/device.h> |
13 | #include <linux/gpio/consumer.h> |
14 | #include <linux/kthread.h> |
15 | #include <linux/mod_devicetable.h> |
16 | #include <linux/overflow.h> |
17 | #include <linux/scatterlist.h> |
18 | #include <linux/slab.h> |
19 | #include <linux/u64_stats_sync.h> |
20 | |
21 | #include <uapi/linux/spi/spi.h> |
22 | |
23 | struct dma_chan; |
24 | struct software_node; |
25 | struct ptp_system_timestamp; |
26 | struct spi_controller; |
27 | struct spi_transfer; |
28 | struct spi_controller_mem_ops; |
29 | struct spi_controller_mem_caps; |
30 | struct spi_message; |
31 | |
32 | /* |
33 | * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, |
34 | * and SPI infrastructure. |
35 | */ |
36 | extern struct bus_type spi_bus_type; |
37 | |
38 | /** |
39 | * struct spi_statistics - statistics for spi transfers |
40 | * @syncp: seqcount to protect members in this struct for per-cpu update |
41 | * on 32-bit systems |
42 | * |
43 | * @messages: number of spi-messages handled |
44 | * @transfers: number of spi_transfers handled |
45 | * @errors: number of errors during spi_transfer |
46 | * @timedout: number of timeouts during spi_transfer |
47 | * |
48 | * @spi_sync: number of times spi_sync is used |
49 | * @spi_sync_immediate: |
50 | * number of times spi_sync is executed immediately |
51 | * in calling context without queuing and scheduling |
52 | * @spi_async: number of times spi_async is used |
53 | * |
54 | * @bytes: number of bytes transferred to/from device |
55 | * @bytes_tx: number of bytes sent to device |
56 | * @bytes_rx: number of bytes received from device |
57 | * |
58 | * @transfer_bytes_histo: |
59 | * transfer bytes histogram |
60 | * |
61 | * @transfers_split_maxsize: |
62 | * number of transfers that have been split because of |
63 | * maxsize limit |
64 | */ |
65 | struct spi_statistics { |
66 | struct u64_stats_sync syncp; |
67 | |
68 | u64_stats_t messages; |
69 | u64_stats_t transfers; |
70 | u64_stats_t errors; |
71 | u64_stats_t timedout; |
72 | |
73 | u64_stats_t spi_sync; |
74 | u64_stats_t spi_sync_immediate; |
75 | u64_stats_t spi_async; |
76 | |
77 | u64_stats_t bytes; |
78 | u64_stats_t bytes_rx; |
79 | u64_stats_t bytes_tx; |
80 | |
81 | #define SPI_STATISTICS_HISTO_SIZE 17 |
82 | u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; |
83 | |
84 | u64_stats_t transfers_split_maxsize; |
85 | }; |
86 | |
87 | #define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ |
88 | do { \ |
89 | struct spi_statistics *__lstats; \ |
90 | get_cpu(); \ |
91 | __lstats = this_cpu_ptr(pcpu_stats); \ |
92 | u64_stats_update_begin(&__lstats->syncp); \ |
93 | u64_stats_add(&__lstats->field, count); \ |
94 | u64_stats_update_end(&__lstats->syncp); \ |
95 | put_cpu(); \ |
96 | } while (0) |
97 | |
98 | #define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ |
99 | do { \ |
100 | struct spi_statistics *__lstats; \ |
101 | get_cpu(); \ |
102 | __lstats = this_cpu_ptr(pcpu_stats); \ |
103 | u64_stats_update_begin(&__lstats->syncp); \ |
104 | u64_stats_inc(&__lstats->field); \ |
105 | u64_stats_update_end(&__lstats->syncp); \ |
106 | put_cpu(); \ |
107 | } while (0) |
108 | |
109 | /** |
110 | * struct spi_delay - SPI delay information |
111 | * @value: Value for the delay |
112 | * @unit: Unit for the delay |
113 | */ |
114 | struct spi_delay { |
115 | #define SPI_DELAY_UNIT_USECS 0 |
116 | #define SPI_DELAY_UNIT_NSECS 1 |
117 | #define SPI_DELAY_UNIT_SCK 2 |
118 | u16 value; |
119 | u8 unit; |
120 | }; |
121 | |
122 | extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); |
123 | extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); |
124 | extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, |
125 | struct spi_transfer *xfer); |
126 | |
127 | /** |
128 | * struct spi_device - Controller side proxy for an SPI slave device |
129 | * @dev: Driver model representation of the device. |
130 | * @controller: SPI controller used with the device. |
131 | * @master: Copy of controller, for backwards compatibility. |
132 | * @max_speed_hz: Maximum clock rate to be used with this chip |
133 | * (on this board); may be changed by the device's driver. |
134 | * The spi_transfer.speed_hz can override this for each transfer. |
135 | * @chip_select: Chipselect, distinguishing chips handled by @controller. |
136 | * @mode: The spi mode defines how data is clocked out and in. |
137 | * This may be changed by the device's driver. |
138 | * The "active low" default for chipselect mode can be overridden |
139 | * (by specifying SPI_CS_HIGH) as can the "MSB first" default for |
140 | * each word in a transfer (by specifying SPI_LSB_FIRST). |
141 | * @bits_per_word: Data transfers involve one or more words; word sizes |
142 | * like eight or 12 bits are common. In-memory wordsizes are |
143 | * powers of two bytes (e.g. 20 bit samples use 32 bits). |
144 | * This may be changed by the device's driver, or left at the |
145 | * default (0) indicating protocol words are eight bit bytes. |
146 | * The spi_transfer.bits_per_word can override this for each transfer. |
147 | * @rt: Make the pump thread real time priority. |
148 | * @irq: Negative, or the number passed to request_irq() to receive |
149 | * interrupts from this device. |
150 | * @controller_state: Controller's runtime state |
151 | * @controller_data: Board-specific definitions for controller, such as |
152 | * FIFO initialization parameters; from board_info.controller_data |
153 | * @modalias: Name of the driver to use with this device, or an alias |
154 | * for that name. This appears in the sysfs "modalias" attribute |
155 | * for driver coldplugging, and in uevents used for hotplugging |
156 | * @driver_override: If the name of a driver is written to this attribute, then |
157 | * the device will bind to the named driver and only the named driver. |
158 | * Do not set directly, because core frees it; use driver_set_override() to |
159 | * set or clear it. |
160 | * @cs_gpiod: GPIO descriptor of the chipselect line (optional, NULL when |
161 | * not using a GPIO line) |
162 | * @word_delay: delay to be inserted between consecutive |
163 | * words of a transfer |
164 | * @cs_setup: delay to be introduced by the controller after CS is asserted |
165 | * @cs_hold: delay to be introduced by the controller before CS is deasserted |
166 | * @cs_inactive: delay to be introduced by the controller after CS is |
167 | * deasserted. If @cs_change_delay is used from @spi_transfer, then the |
168 | * two delays will be added up. |
169 | * @pcpu_statistics: statistics for the spi_device |
170 | * |
171 | * A @spi_device is used to interchange data between an SPI slave |
172 | * (usually a discrete chip) and CPU memory. |
173 | * |
174 | * In @dev, the platform_data is used to hold information about this |
175 | * device that's meaningful to the device's protocol driver, but not |
176 | * to its controller. One example might be an identifier for a chip |
177 | * variant with slightly different functionality; another might be |
178 | * information about how this particular board wires the chip's pins. |
179 | */ |
180 | struct spi_device { |
181 | struct device dev; |
182 | struct spi_controller *controller; |
183 | struct spi_controller *master; /* Compatibility layer */ |
184 | u32 max_speed_hz; |
185 | u8 chip_select; |
186 | u8 bits_per_word; |
187 | bool rt; |
188 | #define SPI_NO_TX BIT(31) /* No transmit wire */ |
189 | #define SPI_NO_RX BIT(30) /* No receive wire */ |
190 | /* |
191 | * TPM specification defines flow control over SPI. Client device |
192 | * can insert a wait state on MISO when address is transmitted by |
193 | * controller on MOSI. Detecting the wait state in software is only |
194 | * possible for full duplex controllers. For controllers that support |
195 | * only half-duplex, the wait state detection needs to be implemented |
196 | * in hardware. TPM devices would set this flag when hardware flow |
197 | * control is expected from SPI controller. |
198 | */ |
199 | #define SPI_TPM_HW_FLOW BIT(29) /* TPM HW flow control */ |
200 | /* |
201 | * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. |
202 | * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, |
203 | * which is defined in 'include/uapi/linux/spi/spi.h'. |
204 | * The bits defined here are from bit 31 downwards, while in |
205 | * SPI_MODE_USER_MASK are from 0 upwards. |
206 | * These bits must not overlap. A static assert check should make sure of that. |
207 | * If adding extra bits, make sure to decrease the bit index below as well. |
208 | */ |
209 | #define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1)) |
210 | u32 mode; |
211 | int irq; |
212 | void *controller_state; |
213 | void *controller_data; |
214 | char modalias[SPI_NAME_SIZE]; |
215 | const char *driver_override; |
216 | struct gpio_desc *cs_gpiod; /* Chip select GPIO descriptor */ |
217 | struct spi_delay word_delay; /* Inter-word delay */ |
218 | /* CS delays */ |
219 | struct spi_delay cs_setup; |
220 | struct spi_delay cs_hold; |
221 | struct spi_delay cs_inactive; |
222 | |
223 | /* The statistics */ |
224 | struct spi_statistics __percpu *pcpu_statistics; |
225 | |
226 | /* |
227 | * Likely need more hooks for more protocol options affecting how |
228 | * the controller talks to each chip, like: |
229 | * - memory packing (12 bit samples into low bits, others zeroed) |
230 | * - priority |
231 | * - chipselect delays |
232 | * - ... |
233 | */ |
234 | }; |
235 | |
236 | /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ |
237 | static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, |
238 | "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap" ); |
239 | |
240 | static inline struct spi_device *to_spi_device(const struct device *dev) |
241 | { |
242 | return dev ? container_of(dev, struct spi_device, dev) : NULL; |
243 | } |
244 | |
245 | /* Most drivers won't need to care about device refcounting */ |
246 | static inline struct spi_device *spi_dev_get(struct spi_device *spi) |
247 | { |
248 | return (spi && get_device(dev: &spi->dev)) ? spi : NULL; |
249 | } |
250 | |
251 | static inline void spi_dev_put(struct spi_device *spi) |
252 | { |
253 | if (spi) |
254 | put_device(dev: &spi->dev); |
255 | } |
256 | |
257 | /* ctldata is for the bus_controller driver's runtime state */ |
258 | static inline void *spi_get_ctldata(const struct spi_device *spi) |
259 | { |
260 | return spi->controller_state; |
261 | } |
262 | |
263 | static inline void spi_set_ctldata(struct spi_device *spi, void *state) |
264 | { |
265 | spi->controller_state = state; |
266 | } |
267 | |
268 | /* Device driver data */ |
269 | |
270 | static inline void spi_set_drvdata(struct spi_device *spi, void *data) |
271 | { |
272 | dev_set_drvdata(dev: &spi->dev, data); |
273 | } |
274 | |
275 | static inline void *spi_get_drvdata(const struct spi_device *spi) |
276 | { |
277 | return dev_get_drvdata(dev: &spi->dev); |
278 | } |
279 | |
280 | static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx) |
281 | { |
282 | return spi->chip_select; |
283 | } |
284 | |
285 | static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect) |
286 | { |
287 | spi->chip_select = chipselect; |
288 | } |
289 | |
290 | static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx) |
291 | { |
292 | return spi->cs_gpiod; |
293 | } |
294 | |
295 | static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod) |
296 | { |
297 | spi->cs_gpiod = csgpiod; |
298 | } |
299 | |
300 | /** |
301 | * struct spi_driver - Host side "protocol" driver |
302 | * @id_table: List of SPI devices supported by this driver |
303 | * @probe: Binds this driver to the SPI device. Drivers can verify |
304 | * that the device is actually present, and may need to configure |
305 | * characteristics (such as bits_per_word) which weren't needed for |
306 | * the initial configuration done during system setup. |
307 | * @remove: Unbinds this driver from the SPI device |
308 | * @shutdown: Standard shutdown callback used during system state |
309 | * transitions such as powerdown/halt and kexec |
310 | * @driver: SPI device drivers should initialize the name and owner |
311 | * field of this structure. |
312 | * |
313 | * This represents the kind of device driver that uses SPI messages to |
314 | * interact with the hardware at the other end of a SPI link. It's called |
315 | * a "protocol" driver because it works through messages rather than talking |
316 | * directly to SPI hardware (which is what the underlying SPI controller |
317 | * driver does to pass those messages). These protocols are defined in the |
318 | * specification for the device(s) supported by the driver. |
319 | * |
320 | * As a rule, those device protocols represent the lowest level interface |
321 | * supported by a driver, and it will support upper level interfaces too. |
322 | * Examples of such upper levels include frameworks like MTD, networking, |
323 | * MMC, RTC, filesystem character device nodes, and hardware monitoring. |
324 | */ |
325 | struct spi_driver { |
326 | const struct spi_device_id *id_table; |
327 | int (*probe)(struct spi_device *spi); |
328 | void (*remove)(struct spi_device *spi); |
329 | void (*shutdown)(struct spi_device *spi); |
330 | struct device_driver driver; |
331 | }; |
332 | |
333 | static inline struct spi_driver *to_spi_driver(struct device_driver *drv) |
334 | { |
335 | return drv ? container_of(drv, struct spi_driver, driver) : NULL; |
336 | } |
337 | |
338 | extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); |
339 | |
340 | /** |
341 | * spi_unregister_driver - reverse effect of spi_register_driver |
342 | * @sdrv: the driver to unregister |
343 | * Context: can sleep |
344 | */ |
345 | static inline void spi_unregister_driver(struct spi_driver *sdrv) |
346 | { |
347 | if (sdrv) |
348 | driver_unregister(drv: &sdrv->driver); |
349 | } |
350 | |
351 | extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); |
352 | |
353 | /* Use a define to avoid include chaining to get THIS_MODULE */ |
354 | #define spi_register_driver(driver) \ |
355 | __spi_register_driver(THIS_MODULE, driver) |
356 | |
357 | /** |
358 | * module_spi_driver() - Helper macro for registering a SPI driver |
359 | * @__spi_driver: spi_driver struct |
360 | * |
361 | * Helper macro for SPI drivers which do not do anything special in module |
362 | * init/exit. This eliminates a lot of boilerplate. Each module may only |
363 | * use this macro once, and calling it replaces module_init() and module_exit() |
364 | */ |
365 | #define module_spi_driver(__spi_driver) \ |
366 | module_driver(__spi_driver, spi_register_driver, \ |
367 | spi_unregister_driver) |
368 | |
369 | /** |
370 | * struct spi_controller - interface to SPI master or slave controller |
371 | * @dev: device interface to this driver |
372 | * @list: link with the global spi_controller list |
373 | * @bus_num: board-specific (and often SOC-specific) identifier for a |
374 | * given SPI controller. |
375 | * @num_chipselect: chipselects are used to distinguish individual |
376 | * SPI slaves, and are numbered from zero to num_chipselects. |
377 | * each slave has a chipselect signal, but it's common that not |
378 | * every chipselect is connected to a slave. |
379 | * @dma_alignment: SPI controller constraint on DMA buffers alignment. |
380 | * @mode_bits: flags understood by this controller driver |
381 | * @buswidth_override_bits: flags to override for this controller driver |
382 | * @bits_per_word_mask: A mask indicating which values of bits_per_word are |
383 | * supported by the driver. Bit n indicates that a bits_per_word n+1 is |
384 | * supported. If set, the SPI core will reject any transfer with an |
385 | * unsupported bits_per_word. If not set, this value is simply ignored, |
386 | * and it's up to the individual driver to perform any validation. |
387 | * @min_speed_hz: Lowest supported transfer speed |
388 | * @max_speed_hz: Highest supported transfer speed |
389 | * @flags: other constraints relevant to this driver |
390 | * @slave: indicates that this is an SPI slave controller |
391 | * @target: indicates that this is an SPI target controller |
392 | * @devm_allocated: whether the allocation of this struct is devres-managed |
393 | * @max_transfer_size: function that returns the max transfer size for |
394 | * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. |
395 | * @max_message_size: function that returns the max message size for |
396 | * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. |
397 | * @io_mutex: mutex for physical bus access |
398 | * @add_lock: mutex to avoid adding devices to the same chipselect |
399 | * @bus_lock_spinlock: spinlock for SPI bus locking |
400 | * @bus_lock_mutex: mutex for exclusion of multiple callers |
401 | * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use |
402 | * @setup: updates the device mode and clocking records used by a |
403 | * device's SPI controller; protocol code may call this. This |
404 | * must fail if an unrecognized or unsupported mode is requested. |
405 | * It's always safe to call this unless transfers are pending on |
406 | * the device whose settings are being modified. |
407 | * @set_cs_timing: optional hook for SPI devices to request SPI master |
408 | * controller for configuring specific CS setup time, hold time and inactive |
409 | * delay interms of clock counts |
410 | * @transfer: adds a message to the controller's transfer queue. |
411 | * @cleanup: frees controller-specific state |
412 | * @can_dma: determine whether this controller supports DMA |
413 | * @dma_map_dev: device which can be used for DMA mapping |
414 | * @cur_rx_dma_dev: device which is currently used for RX DMA mapping |
415 | * @cur_tx_dma_dev: device which is currently used for TX DMA mapping |
416 | * @queued: whether this controller is providing an internal message queue |
417 | * @kworker: pointer to thread struct for message pump |
418 | * @pump_messages: work struct for scheduling work to the message pump |
419 | * @queue_lock: spinlock to synchronise access to message queue |
420 | * @queue: message queue |
421 | * @cur_msg: the currently in-flight message |
422 | * @cur_msg_completion: a completion for the current in-flight message |
423 | * @cur_msg_incomplete: Flag used internally to opportunistically skip |
424 | * the @cur_msg_completion. This flag is used to check if the driver has |
425 | * already called spi_finalize_current_message(). |
426 | * @cur_msg_need_completion: Flag used internally to opportunistically skip |
427 | * the @cur_msg_completion. This flag is used to signal the context that |
428 | * is running spi_finalize_current_message() that it needs to complete() |
429 | * @cur_msg_mapped: message has been mapped for DMA |
430 | * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip |
431 | * selected |
432 | * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. |
433 | * @xfer_completion: used by core transfer_one_message() |
434 | * @busy: message pump is busy |
435 | * @running: message pump is running |
436 | * @rt: whether this queue is set to run as a realtime task |
437 | * @auto_runtime_pm: the core should ensure a runtime PM reference is held |
438 | * while the hardware is prepared, using the parent |
439 | * device for the spidev |
440 | * @max_dma_len: Maximum length of a DMA transfer for the device. |
441 | * @prepare_transfer_hardware: a message will soon arrive from the queue |
442 | * so the subsystem requests the driver to prepare the transfer hardware |
443 | * by issuing this call |
444 | * @transfer_one_message: the subsystem calls the driver to transfer a single |
445 | * message while queuing transfers that arrive in the meantime. When the |
446 | * driver is finished with this message, it must call |
447 | * spi_finalize_current_message() so the subsystem can issue the next |
448 | * message |
449 | * @unprepare_transfer_hardware: there are currently no more messages on the |
450 | * queue so the subsystem notifies the driver that it may relax the |
451 | * hardware by issuing this call |
452 | * |
453 | * @set_cs: set the logic level of the chip select line. May be called |
454 | * from interrupt context. |
455 | * @prepare_message: set up the controller to transfer a single message, |
456 | * for example doing DMA mapping. Called from threaded |
457 | * context. |
458 | * @transfer_one: transfer a single spi_transfer. |
459 | * |
460 | * - return 0 if the transfer is finished, |
461 | * - return 1 if the transfer is still in progress. When |
462 | * the driver is finished with this transfer it must |
463 | * call spi_finalize_current_transfer() so the subsystem |
464 | * can issue the next transfer. Note: transfer_one and |
465 | * transfer_one_message are mutually exclusive; when both |
466 | * are set, the generic subsystem does not call your |
467 | * transfer_one callback. |
468 | * @handle_err: the subsystem calls the driver to handle an error that occurs |
469 | * in the generic implementation of transfer_one_message(). |
470 | * @mem_ops: optimized/dedicated operations for interactions with SPI memory. |
471 | * This field is optional and should only be implemented if the |
472 | * controller has native support for memory like operations. |
473 | * @mem_caps: controller capabilities for the handling of memory operations. |
474 | * @unprepare_message: undo any work done by prepare_message(). |
475 | * @slave_abort: abort the ongoing transfer request on an SPI slave controller |
476 | * @target_abort: abort the ongoing transfer request on an SPI target controller |
477 | * @cs_gpiods: Array of GPIO descriptors to use as chip select lines; one per CS |
478 | * number. Any individual value may be NULL for CS lines that |
479 | * are not GPIOs (driven by the SPI controller itself). |
480 | * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab |
481 | * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have |
482 | * the cs_gpiod assigned if a GPIO line is found for the chipselect. |
483 | * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will |
484 | * fill in this field with the first unused native CS, to be used by SPI |
485 | * controller drivers that need to drive a native CS when using GPIO CS. |
486 | * @max_native_cs: When cs_gpiods is used, and this field is filled in, |
487 | * spi_register_controller() will validate all native CS (including the |
488 | * unused native CS) against this value. |
489 | * @pcpu_statistics: statistics for the spi_controller |
490 | * @dma_tx: DMA transmit channel |
491 | * @dma_rx: DMA receive channel |
492 | * @dummy_rx: dummy receive buffer for full-duplex devices |
493 | * @dummy_tx: dummy transmit buffer for full-duplex devices |
494 | * @fw_translate_cs: If the boot firmware uses different numbering scheme |
495 | * what Linux expects, this optional hook can be used to translate |
496 | * between the two. |
497 | * @ptp_sts_supported: If the driver sets this to true, it must provide a |
498 | * time snapshot in @spi_transfer->ptp_sts as close as possible to the |
499 | * moment in time when @spi_transfer->ptp_sts_word_pre and |
500 | * @spi_transfer->ptp_sts_word_post were transmitted. |
501 | * If the driver does not set this, the SPI core takes the snapshot as |
502 | * close to the driver hand-over as possible. |
503 | * @irq_flags: Interrupt enable state during PTP system timestamping |
504 | * @fallback: fallback to PIO if DMA transfer return failure with |
505 | * SPI_TRANS_FAIL_NO_START. |
506 | * @queue_empty: signal green light for opportunistically skipping the queue |
507 | * for spi_sync transfers. |
508 | * @must_async: disable all fast paths in the core |
509 | * |
510 | * Each SPI controller can communicate with one or more @spi_device |
511 | * children. These make a small bus, sharing MOSI, MISO and SCK signals |
512 | * but not chip select signals. Each device may be configured to use a |
513 | * different clock rate, since those shared signals are ignored unless |
514 | * the chip is selected. |
515 | * |
516 | * The driver for an SPI controller manages access to those devices through |
517 | * a queue of spi_message transactions, copying data between CPU memory and |
518 | * an SPI slave device. For each such message it queues, it calls the |
519 | * message's completion function when the transaction completes. |
520 | */ |
521 | struct spi_controller { |
522 | struct device dev; |
523 | |
524 | struct list_head list; |
525 | |
526 | /* |
527 | * Other than negative (== assign one dynamically), bus_num is fully |
528 | * board-specific. Usually that simplifies to being SoC-specific. |
529 | * example: one SoC has three SPI controllers, numbered 0..2, |
530 | * and one board's schematics might show it using SPI-2. Software |
531 | * would normally use bus_num=2 for that controller. |
532 | */ |
533 | s16 bus_num; |
534 | |
535 | /* |
536 | * Chipselects will be integral to many controllers; some others |
537 | * might use board-specific GPIOs. |
538 | */ |
539 | u16 num_chipselect; |
540 | |
541 | /* Some SPI controllers pose alignment requirements on DMAable |
542 | * buffers; let protocol drivers know about these requirements. |
543 | */ |
544 | u16 dma_alignment; |
545 | |
546 | /* spi_device.mode flags understood by this controller driver */ |
547 | u32 mode_bits; |
548 | |
549 | /* spi_device.mode flags override flags for this controller */ |
550 | u32 buswidth_override_bits; |
551 | |
552 | /* Bitmask of supported bits_per_word for transfers */ |
553 | u32 bits_per_word_mask; |
554 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) |
555 | #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) |
556 | |
557 | /* Limits on transfer speed */ |
558 | u32 min_speed_hz; |
559 | u32 max_speed_hz; |
560 | |
561 | /* Other constraints relevant to this driver */ |
562 | u16 flags; |
563 | #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ |
564 | #define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ |
565 | #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ |
566 | #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ |
567 | #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ |
568 | #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */ |
569 | |
570 | /* Flag indicating if the allocation of this struct is devres-managed */ |
571 | bool devm_allocated; |
572 | |
573 | union { |
574 | /* Flag indicating this is an SPI slave controller */ |
575 | bool slave; |
576 | /* Flag indicating this is an SPI target controller */ |
577 | bool target; |
578 | }; |
579 | |
580 | /* |
581 | * On some hardware transfer / message size may be constrained |
582 | * the limit may depend on device transfer settings. |
583 | */ |
584 | size_t (*max_transfer_size)(struct spi_device *spi); |
585 | size_t (*max_message_size)(struct spi_device *spi); |
586 | |
587 | /* I/O mutex */ |
588 | struct mutex io_mutex; |
589 | |
590 | /* Used to avoid adding the same CS twice */ |
591 | struct mutex add_lock; |
592 | |
593 | /* Lock and mutex for SPI bus locking */ |
594 | spinlock_t bus_lock_spinlock; |
595 | struct mutex bus_lock_mutex; |
596 | |
597 | /* Flag indicating that the SPI bus is locked for exclusive use */ |
598 | bool bus_lock_flag; |
599 | |
600 | /* |
601 | * Setup mode and clock, etc (SPI driver may call many times). |
602 | * |
603 | * IMPORTANT: this may be called when transfers to another |
604 | * device are active. DO NOT UPDATE SHARED REGISTERS in ways |
605 | * which could break those transfers. |
606 | */ |
607 | int (*setup)(struct spi_device *spi); |
608 | |
609 | /* |
610 | * set_cs_timing() method is for SPI controllers that supports |
611 | * configuring CS timing. |
612 | * |
613 | * This hook allows SPI client drivers to request SPI controllers |
614 | * to configure specific CS timing through spi_set_cs_timing() after |
615 | * spi_setup(). |
616 | */ |
617 | int (*set_cs_timing)(struct spi_device *spi); |
618 | |
619 | /* |
620 | * Bidirectional bulk transfers |
621 | * |
622 | * + The transfer() method may not sleep; its main role is |
623 | * just to add the message to the queue. |
624 | * + For now there's no remove-from-queue operation, or |
625 | * any other request management |
626 | * + To a given spi_device, message queueing is pure FIFO |
627 | * |
628 | * + The controller's main job is to process its message queue, |
629 | * selecting a chip (for masters), then transferring data |
630 | * + If there are multiple spi_device children, the i/o queue |
631 | * arbitration algorithm is unspecified (round robin, FIFO, |
632 | * priority, reservations, preemption, etc) |
633 | * |
634 | * + Chipselect stays active during the entire message |
635 | * (unless modified by spi_transfer.cs_change != 0). |
636 | * + The message transfers use clock and SPI mode parameters |
637 | * previously established by setup() for this device |
638 | */ |
639 | int (*transfer)(struct spi_device *spi, |
640 | struct spi_message *mesg); |
641 | |
642 | /* Called on release() to free memory provided by spi_controller */ |
643 | void (*cleanup)(struct spi_device *spi); |
644 | |
645 | /* |
646 | * Used to enable core support for DMA handling, if can_dma() |
647 | * exists and returns true then the transfer will be mapped |
648 | * prior to transfer_one() being called. The driver should |
649 | * not modify or store xfer and dma_tx and dma_rx must be set |
650 | * while the device is prepared. |
651 | */ |
652 | bool (*can_dma)(struct spi_controller *ctlr, |
653 | struct spi_device *spi, |
654 | struct spi_transfer *xfer); |
655 | struct device *dma_map_dev; |
656 | struct device *cur_rx_dma_dev; |
657 | struct device *cur_tx_dma_dev; |
658 | |
659 | /* |
660 | * These hooks are for drivers that want to use the generic |
661 | * controller transfer queueing mechanism. If these are used, the |
662 | * transfer() function above must NOT be specified by the driver. |
663 | * Over time we expect SPI drivers to be phased over to this API. |
664 | */ |
665 | bool queued; |
666 | struct kthread_worker *kworker; |
667 | struct kthread_work pump_messages; |
668 | spinlock_t queue_lock; |
669 | struct list_head queue; |
670 | struct spi_message *cur_msg; |
671 | struct completion cur_msg_completion; |
672 | bool cur_msg_incomplete; |
673 | bool cur_msg_need_completion; |
674 | bool busy; |
675 | bool running; |
676 | bool rt; |
677 | bool auto_runtime_pm; |
678 | bool cur_msg_mapped; |
679 | char last_cs; |
680 | bool last_cs_mode_high; |
681 | bool fallback; |
682 | struct completion xfer_completion; |
683 | size_t max_dma_len; |
684 | |
685 | int (*prepare_transfer_hardware)(struct spi_controller *ctlr); |
686 | int (*transfer_one_message)(struct spi_controller *ctlr, |
687 | struct spi_message *mesg); |
688 | int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); |
689 | int (*prepare_message)(struct spi_controller *ctlr, |
690 | struct spi_message *message); |
691 | int (*unprepare_message)(struct spi_controller *ctlr, |
692 | struct spi_message *message); |
693 | union { |
694 | int (*slave_abort)(struct spi_controller *ctlr); |
695 | int (*target_abort)(struct spi_controller *ctlr); |
696 | }; |
697 | |
698 | /* |
699 | * These hooks are for drivers that use a generic implementation |
700 | * of transfer_one_message() provided by the core. |
701 | */ |
702 | void (*set_cs)(struct spi_device *spi, bool enable); |
703 | int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, |
704 | struct spi_transfer *transfer); |
705 | void (*handle_err)(struct spi_controller *ctlr, |
706 | struct spi_message *message); |
707 | |
708 | /* Optimized handlers for SPI memory-like operations. */ |
709 | const struct spi_controller_mem_ops *mem_ops; |
710 | const struct spi_controller_mem_caps *mem_caps; |
711 | |
712 | /* GPIO chip select */ |
713 | struct gpio_desc **cs_gpiods; |
714 | bool use_gpio_descriptors; |
715 | s8 unused_native_cs; |
716 | s8 max_native_cs; |
717 | |
718 | /* Statistics */ |
719 | struct spi_statistics __percpu *pcpu_statistics; |
720 | |
721 | /* DMA channels for use with core dmaengine helpers */ |
722 | struct dma_chan *dma_tx; |
723 | struct dma_chan *dma_rx; |
724 | |
725 | /* Dummy data for full duplex devices */ |
726 | void *dummy_rx; |
727 | void *dummy_tx; |
728 | |
729 | int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); |
730 | |
731 | /* |
732 | * Driver sets this field to indicate it is able to snapshot SPI |
733 | * transfers (needed e.g. for reading the time of POSIX clocks) |
734 | */ |
735 | bool ptp_sts_supported; |
736 | |
737 | /* Interrupt enable state during PTP system timestamping */ |
738 | unsigned long irq_flags; |
739 | |
740 | /* Flag for enabling opportunistic skipping of the queue in spi_sync */ |
741 | bool queue_empty; |
742 | bool must_async; |
743 | }; |
744 | |
745 | static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) |
746 | { |
747 | return dev_get_drvdata(dev: &ctlr->dev); |
748 | } |
749 | |
750 | static inline void spi_controller_set_devdata(struct spi_controller *ctlr, |
751 | void *data) |
752 | { |
753 | dev_set_drvdata(dev: &ctlr->dev, data); |
754 | } |
755 | |
756 | static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) |
757 | { |
758 | if (!ctlr || !get_device(dev: &ctlr->dev)) |
759 | return NULL; |
760 | return ctlr; |
761 | } |
762 | |
763 | static inline void spi_controller_put(struct spi_controller *ctlr) |
764 | { |
765 | if (ctlr) |
766 | put_device(dev: &ctlr->dev); |
767 | } |
768 | |
769 | static inline bool spi_controller_is_slave(struct spi_controller *ctlr) |
770 | { |
771 | return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; |
772 | } |
773 | |
774 | static inline bool spi_controller_is_target(struct spi_controller *ctlr) |
775 | { |
776 | return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target; |
777 | } |
778 | |
779 | /* PM calls that need to be issued by the driver */ |
780 | extern int spi_controller_suspend(struct spi_controller *ctlr); |
781 | extern int spi_controller_resume(struct spi_controller *ctlr); |
782 | |
783 | /* Calls the driver make to interact with the message queue */ |
784 | extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); |
785 | extern void spi_finalize_current_message(struct spi_controller *ctlr); |
786 | extern void spi_finalize_current_transfer(struct spi_controller *ctlr); |
787 | |
788 | /* Helper calls for driver to timestamp transfer */ |
789 | void spi_take_timestamp_pre(struct spi_controller *ctlr, |
790 | struct spi_transfer *xfer, |
791 | size_t progress, bool irqs_off); |
792 | void spi_take_timestamp_post(struct spi_controller *ctlr, |
793 | struct spi_transfer *xfer, |
794 | size_t progress, bool irqs_off); |
795 | |
796 | /* The SPI driver core manages memory for the spi_controller classdev */ |
797 | extern struct spi_controller *__spi_alloc_controller(struct device *host, |
798 | unsigned int size, bool slave); |
799 | |
800 | static inline struct spi_controller *spi_alloc_master(struct device *host, |
801 | unsigned int size) |
802 | { |
803 | return __spi_alloc_controller(host, size, slave: false); |
804 | } |
805 | |
806 | static inline struct spi_controller *spi_alloc_slave(struct device *host, |
807 | unsigned int size) |
808 | { |
809 | if (!IS_ENABLED(CONFIG_SPI_SLAVE)) |
810 | return NULL; |
811 | |
812 | return __spi_alloc_controller(host, size, slave: true); |
813 | } |
814 | |
815 | static inline struct spi_controller *spi_alloc_host(struct device *dev, |
816 | unsigned int size) |
817 | { |
818 | return __spi_alloc_controller(host: dev, size, slave: false); |
819 | } |
820 | |
821 | static inline struct spi_controller *spi_alloc_target(struct device *dev, |
822 | unsigned int size) |
823 | { |
824 | if (!IS_ENABLED(CONFIG_SPI_SLAVE)) |
825 | return NULL; |
826 | |
827 | return __spi_alloc_controller(host: dev, size, slave: true); |
828 | } |
829 | |
830 | struct spi_controller *__devm_spi_alloc_controller(struct device *dev, |
831 | unsigned int size, |
832 | bool slave); |
833 | |
834 | static inline struct spi_controller *devm_spi_alloc_master(struct device *dev, |
835 | unsigned int size) |
836 | { |
837 | return __devm_spi_alloc_controller(dev, size, slave: false); |
838 | } |
839 | |
840 | static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev, |
841 | unsigned int size) |
842 | { |
843 | if (!IS_ENABLED(CONFIG_SPI_SLAVE)) |
844 | return NULL; |
845 | |
846 | return __devm_spi_alloc_controller(dev, size, slave: true); |
847 | } |
848 | |
849 | static inline struct spi_controller *devm_spi_alloc_host(struct device *dev, |
850 | unsigned int size) |
851 | { |
852 | return __devm_spi_alloc_controller(dev, size, slave: false); |
853 | } |
854 | |
855 | static inline struct spi_controller *devm_spi_alloc_target(struct device *dev, |
856 | unsigned int size) |
857 | { |
858 | if (!IS_ENABLED(CONFIG_SPI_SLAVE)) |
859 | return NULL; |
860 | |
861 | return __devm_spi_alloc_controller(dev, size, slave: true); |
862 | } |
863 | |
864 | extern int spi_register_controller(struct spi_controller *ctlr); |
865 | extern int devm_spi_register_controller(struct device *dev, |
866 | struct spi_controller *ctlr); |
867 | extern void spi_unregister_controller(struct spi_controller *ctlr); |
868 | |
869 | #if IS_ENABLED(CONFIG_ACPI) |
870 | extern struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev); |
871 | extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, |
872 | struct acpi_device *adev, |
873 | int index); |
874 | int acpi_spi_count_resources(struct acpi_device *adev); |
875 | #endif |
876 | |
877 | /* |
878 | * SPI resource management while processing a SPI message |
879 | */ |
880 | |
881 | typedef void (*spi_res_release_t)(struct spi_controller *ctlr, |
882 | struct spi_message *msg, |
883 | void *res); |
884 | |
885 | /** |
886 | * struct spi_res - SPI resource management structure |
887 | * @entry: list entry |
888 | * @release: release code called prior to freeing this resource |
889 | * @data: extra data allocated for the specific use-case |
890 | * |
891 | * This is based on ideas from devres, but focused on life-cycle |
892 | * management during spi_message processing. |
893 | */ |
894 | struct spi_res { |
895 | struct list_head entry; |
896 | spi_res_release_t release; |
897 | unsigned long long data[]; /* Guarantee ull alignment */ |
898 | }; |
899 | |
900 | /*---------------------------------------------------------------------------*/ |
901 | |
902 | /* |
903 | * I/O INTERFACE between SPI controller and protocol drivers |
904 | * |
905 | * Protocol drivers use a queue of spi_messages, each transferring data |
906 | * between the controller and memory buffers. |
907 | * |
908 | * The spi_messages themselves consist of a series of read+write transfer |
909 | * segments. Those segments always read the same number of bits as they |
910 | * write; but one or the other is easily ignored by passing a NULL buffer |
911 | * pointer. (This is unlike most types of I/O API, because SPI hardware |
912 | * is full duplex.) |
913 | * |
914 | * NOTE: Allocation of spi_transfer and spi_message memory is entirely |
915 | * up to the protocol driver, which guarantees the integrity of both (as |
916 | * well as the data buffers) for as long as the message is queued. |
917 | */ |
918 | |
919 | /** |
920 | * struct spi_transfer - a read/write buffer pair |
921 | * @tx_buf: data to be written (DMA-safe memory), or NULL |
922 | * @rx_buf: data to be read (DMA-safe memory), or NULL |
923 | * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped |
924 | * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped |
925 | * @tx_nbits: number of bits used for writing. If 0 the default |
926 | * (SPI_NBITS_SINGLE) is used. |
927 | * @rx_nbits: number of bits used for reading. If 0 the default |
928 | * (SPI_NBITS_SINGLE) is used. |
929 | * @len: size of rx and tx buffers (in bytes) |
930 | * @speed_hz: Select a speed other than the device default for this |
931 | * transfer. If 0 the default (from @spi_device) is used. |
932 | * @bits_per_word: select a bits_per_word other than the device default |
933 | * for this transfer. If 0 the default (from @spi_device) is used. |
934 | * @dummy_data: indicates transfer is dummy bytes transfer. |
935 | * @cs_off: performs the transfer with chipselect off. |
936 | * @cs_change: affects chipselect after this transfer completes |
937 | * @cs_change_delay: delay between cs deassert and assert when |
938 | * @cs_change is set and @spi_transfer is not the last in @spi_message |
939 | * @delay: delay to be introduced after this transfer before |
940 | * (optionally) changing the chipselect status, then starting |
941 | * the next transfer or completing this @spi_message. |
942 | * @word_delay: inter word delay to be introduced after each word size |
943 | * (set by bits_per_word) transmission. |
944 | * @effective_speed_hz: the effective SCK-speed that was used to |
945 | * transfer this transfer. Set to 0 if the SPI bus driver does |
946 | * not support it. |
947 | * @transfer_list: transfers are sequenced through @spi_message.transfers |
948 | * @tx_sg: Scatterlist for transmit, currently not for client use |
949 | * @rx_sg: Scatterlist for receive, currently not for client use |
950 | * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset |
951 | * within @tx_buf for which the SPI device is requesting that the time |
952 | * snapshot for this transfer begins. Upon completing the SPI transfer, |
953 | * this value may have changed compared to what was requested, depending |
954 | * on the available snapshotting resolution (DMA transfer, |
955 | * @ptp_sts_supported is false, etc). |
956 | * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning |
957 | * that a single byte should be snapshotted). |
958 | * If the core takes care of the timestamp (if @ptp_sts_supported is false |
959 | * for this controller), it will set @ptp_sts_word_pre to 0, and |
960 | * @ptp_sts_word_post to the length of the transfer. This is done |
961 | * purposefully (instead of setting to spi_transfer->len - 1) to denote |
962 | * that a transfer-level snapshot taken from within the driver may still |
963 | * be of higher quality. |
964 | * @ptp_sts: Pointer to a memory location held by the SPI slave device where a |
965 | * PTP system timestamp structure may lie. If drivers use PIO or their |
966 | * hardware has some sort of assist for retrieving exact transfer timing, |
967 | * they can (and should) assert @ptp_sts_supported and populate this |
968 | * structure using the ptp_read_system_*ts helper functions. |
969 | * The timestamp must represent the time at which the SPI slave device has |
970 | * processed the word, i.e. the "pre" timestamp should be taken before |
971 | * transmitting the "pre" word, and the "post" timestamp after receiving |
972 | * transmit confirmation from the controller for the "post" word. |
973 | * @timestamped: true if the transfer has been timestamped |
974 | * @error: Error status logged by SPI controller driver. |
975 | * |
976 | * SPI transfers always write the same number of bytes as they read. |
977 | * Protocol drivers should always provide @rx_buf and/or @tx_buf. |
978 | * In some cases, they may also want to provide DMA addresses for |
979 | * the data being transferred; that may reduce overhead, when the |
980 | * underlying driver uses DMA. |
981 | * |
982 | * If the transmit buffer is NULL, zeroes will be shifted out |
983 | * while filling @rx_buf. If the receive buffer is NULL, the data |
984 | * shifted in will be discarded. Only "len" bytes shift out (or in). |
985 | * It's an error to try to shift out a partial word. (For example, by |
986 | * shifting out three bytes with word size of sixteen or twenty bits; |
987 | * the former uses two bytes per word, the latter uses four bytes.) |
988 | * |
989 | * In-memory data values are always in native CPU byte order, translated |
990 | * from the wire byte order (big-endian except with SPI_LSB_FIRST). So |
991 | * for example when bits_per_word is sixteen, buffers are 2N bytes long |
992 | * (@len = 2N) and hold N sixteen bit words in CPU byte order. |
993 | * |
994 | * When the word size of the SPI transfer is not a power-of-two multiple |
995 | * of eight bits, those in-memory words include extra bits. In-memory |
996 | * words are always seen by protocol drivers as right-justified, so the |
997 | * undefined (rx) or unused (tx) bits are always the most significant bits. |
998 | * |
999 | * All SPI transfers start with the relevant chipselect active. Normally |
1000 | * it stays selected until after the last transfer in a message. Drivers |
1001 | * can affect the chipselect signal using cs_change. |
1002 | * |
1003 | * (i) If the transfer isn't the last one in the message, this flag is |
1004 | * used to make the chipselect briefly go inactive in the middle of the |
1005 | * message. Toggling chipselect in this way may be needed to terminate |
1006 | * a chip command, letting a single spi_message perform all of group of |
1007 | * chip transactions together. |
1008 | * |
1009 | * (ii) When the transfer is the last one in the message, the chip may |
1010 | * stay selected until the next transfer. On multi-device SPI busses |
1011 | * with nothing blocking messages going to other devices, this is just |
1012 | * a performance hint; starting a message to another device deselects |
1013 | * this one. But in other cases, this can be used to ensure correctness. |
1014 | * Some devices need protocol transactions to be built from a series of |
1015 | * spi_message submissions, where the content of one message is determined |
1016 | * by the results of previous messages and where the whole transaction |
1017 | * ends when the chipselect goes inactive. |
1018 | * |
1019 | * When SPI can transfer in 1x,2x or 4x. It can get this transfer information |
1020 | * from device through @tx_nbits and @rx_nbits. In Bi-direction, these |
1021 | * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) |
1022 | * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. |
1023 | * |
1024 | * The code that submits an spi_message (and its spi_transfers) |
1025 | * to the lower layers is responsible for managing its memory. |
1026 | * Zero-initialize every field you don't set up explicitly, to |
1027 | * insulate against future API updates. After you submit a message |
1028 | * and its transfers, ignore them until its completion callback. |
1029 | */ |
1030 | struct spi_transfer { |
1031 | /* |
1032 | * It's okay if tx_buf == rx_buf (right?). |
1033 | * For MicroWire, one buffer must be NULL. |
1034 | * Buffers must work with dma_*map_single() calls, unless |
1035 | * spi_message.is_dma_mapped reports a pre-existing mapping. |
1036 | */ |
1037 | const void *tx_buf; |
1038 | void *rx_buf; |
1039 | unsigned len; |
1040 | |
1041 | #define SPI_TRANS_FAIL_NO_START BIT(0) |
1042 | u16 error; |
1043 | |
1044 | dma_addr_t tx_dma; |
1045 | dma_addr_t rx_dma; |
1046 | struct sg_table tx_sg; |
1047 | struct sg_table rx_sg; |
1048 | |
1049 | unsigned dummy_data:1; |
1050 | unsigned cs_off:1; |
1051 | unsigned cs_change:1; |
1052 | unsigned tx_nbits:3; |
1053 | unsigned rx_nbits:3; |
1054 | unsigned timestamped:1; |
1055 | #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ |
1056 | #define SPI_NBITS_DUAL 0x02 /* 2-bit transfer */ |
1057 | #define SPI_NBITS_QUAD 0x04 /* 4-bit transfer */ |
1058 | u8 bits_per_word; |
1059 | struct spi_delay delay; |
1060 | struct spi_delay cs_change_delay; |
1061 | struct spi_delay word_delay; |
1062 | u32 speed_hz; |
1063 | |
1064 | u32 effective_speed_hz; |
1065 | |
1066 | unsigned int ptp_sts_word_pre; |
1067 | unsigned int ptp_sts_word_post; |
1068 | |
1069 | struct ptp_system_timestamp *ptp_sts; |
1070 | |
1071 | struct list_head transfer_list; |
1072 | }; |
1073 | |
1074 | /** |
1075 | * struct spi_message - one multi-segment SPI transaction |
1076 | * @transfers: list of transfer segments in this transaction |
1077 | * @spi: SPI device to which the transaction is queued |
1078 | * @is_dma_mapped: if true, the caller provided both DMA and CPU virtual |
1079 | * addresses for each transfer buffer |
1080 | * @complete: called to report transaction completions |
1081 | * @context: the argument to complete() when it's called |
1082 | * @frame_length: the total number of bytes in the message |
1083 | * @actual_length: the total number of bytes that were transferred in all |
1084 | * successful segments |
1085 | * @status: zero for success, else negative errno |
1086 | * @queue: for use by whichever driver currently owns the message |
1087 | * @state: for use by whichever driver currently owns the message |
1088 | * @resources: for resource management when the SPI message is processed |
1089 | * @prepared: spi_prepare_message was called for the this message |
1090 | * |
1091 | * A @spi_message is used to execute an atomic sequence of data transfers, |
1092 | * each represented by a struct spi_transfer. The sequence is "atomic" |
1093 | * in the sense that no other spi_message may use that SPI bus until that |
1094 | * sequence completes. On some systems, many such sequences can execute as |
1095 | * a single programmed DMA transfer. On all systems, these messages are |
1096 | * queued, and might complete after transactions to other devices. Messages |
1097 | * sent to a given spi_device are always executed in FIFO order. |
1098 | * |
1099 | * The code that submits an spi_message (and its spi_transfers) |
1100 | * to the lower layers is responsible for managing its memory. |
1101 | * Zero-initialize every field you don't set up explicitly, to |
1102 | * insulate against future API updates. After you submit a message |
1103 | * and its transfers, ignore them until its completion callback. |
1104 | */ |
1105 | struct spi_message { |
1106 | struct list_head transfers; |
1107 | |
1108 | struct spi_device *spi; |
1109 | |
1110 | unsigned is_dma_mapped:1; |
1111 | |
1112 | /* spi_prepare_message() was called for this message */ |
1113 | bool prepared; |
1114 | |
1115 | /* |
1116 | * REVISIT: we might want a flag affecting the behavior of the |
1117 | * last transfer ... allowing things like "read 16 bit length L" |
1118 | * immediately followed by "read L bytes". Basically imposing |
1119 | * a specific message scheduling algorithm. |
1120 | * |
1121 | * Some controller drivers (message-at-a-time queue processing) |
1122 | * could provide that as their default scheduling algorithm. But |
1123 | * others (with multi-message pipelines) could need a flag to |
1124 | * tell them about such special cases. |
1125 | */ |
1126 | |
1127 | /* Completion is reported through a callback */ |
1128 | int status; |
1129 | void (*complete)(void *context); |
1130 | void *context; |
1131 | unsigned frame_length; |
1132 | unsigned actual_length; |
1133 | |
1134 | /* |
1135 | * For optional use by whatever driver currently owns the |
1136 | * spi_message ... between calls to spi_async and then later |
1137 | * complete(), that's the spi_controller controller driver. |
1138 | */ |
1139 | struct list_head queue; |
1140 | void *state; |
1141 | |
1142 | /* List of spi_res resources when the SPI message is processed */ |
1143 | struct list_head resources; |
1144 | }; |
1145 | |
1146 | static inline void spi_message_init_no_memset(struct spi_message *m) |
1147 | { |
1148 | INIT_LIST_HEAD(list: &m->transfers); |
1149 | INIT_LIST_HEAD(list: &m->resources); |
1150 | } |
1151 | |
1152 | static inline void spi_message_init(struct spi_message *m) |
1153 | { |
1154 | memset(m, 0, sizeof *m); |
1155 | spi_message_init_no_memset(m); |
1156 | } |
1157 | |
1158 | static inline void |
1159 | spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) |
1160 | { |
1161 | list_add_tail(new: &t->transfer_list, head: &m->transfers); |
1162 | } |
1163 | |
1164 | static inline void |
1165 | spi_transfer_del(struct spi_transfer *t) |
1166 | { |
1167 | list_del(entry: &t->transfer_list); |
1168 | } |
1169 | |
1170 | static inline int |
1171 | spi_transfer_delay_exec(struct spi_transfer *t) |
1172 | { |
1173 | return spi_delay_exec(delay: &t->delay, xfer: t); |
1174 | } |
1175 | |
1176 | /** |
1177 | * spi_message_init_with_transfers - Initialize spi_message and append transfers |
1178 | * @m: spi_message to be initialized |
1179 | * @xfers: An array of SPI transfers |
1180 | * @num_xfers: Number of items in the xfer array |
1181 | * |
1182 | * This function initializes the given spi_message and adds each spi_transfer in |
1183 | * the given array to the message. |
1184 | */ |
1185 | static inline void |
1186 | spi_message_init_with_transfers(struct spi_message *m, |
1187 | struct spi_transfer *xfers, unsigned int num_xfers) |
1188 | { |
1189 | unsigned int i; |
1190 | |
1191 | spi_message_init(m); |
1192 | for (i = 0; i < num_xfers; ++i) |
1193 | spi_message_add_tail(t: &xfers[i], m); |
1194 | } |
1195 | |
1196 | /* |
1197 | * It's fine to embed message and transaction structures in other data |
1198 | * structures so long as you don't free them while they're in use. |
1199 | */ |
1200 | static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) |
1201 | { |
1202 | struct spi_message_with_transfers { |
1203 | struct spi_message m; |
1204 | struct spi_transfer t[]; |
1205 | } *mwt; |
1206 | unsigned i; |
1207 | |
1208 | mwt = kzalloc(struct_size(mwt, t, ntrans), flags); |
1209 | if (!mwt) |
1210 | return NULL; |
1211 | |
1212 | spi_message_init_no_memset(m: &mwt->m); |
1213 | for (i = 0; i < ntrans; i++) |
1214 | spi_message_add_tail(t: &mwt->t[i], m: &mwt->m); |
1215 | |
1216 | return &mwt->m; |
1217 | } |
1218 | |
1219 | static inline void spi_message_free(struct spi_message *m) |
1220 | { |
1221 | kfree(objp: m); |
1222 | } |
1223 | |
1224 | extern int spi_setup(struct spi_device *spi); |
1225 | extern int spi_async(struct spi_device *spi, struct spi_message *message); |
1226 | extern int spi_slave_abort(struct spi_device *spi); |
1227 | extern int spi_target_abort(struct spi_device *spi); |
1228 | |
1229 | static inline size_t |
1230 | spi_max_message_size(struct spi_device *spi) |
1231 | { |
1232 | struct spi_controller *ctlr = spi->controller; |
1233 | |
1234 | if (!ctlr->max_message_size) |
1235 | return SIZE_MAX; |
1236 | return ctlr->max_message_size(spi); |
1237 | } |
1238 | |
1239 | static inline size_t |
1240 | spi_max_transfer_size(struct spi_device *spi) |
1241 | { |
1242 | struct spi_controller *ctlr = spi->controller; |
1243 | size_t tr_max = SIZE_MAX; |
1244 | size_t msg_max = spi_max_message_size(spi); |
1245 | |
1246 | if (ctlr->max_transfer_size) |
1247 | tr_max = ctlr->max_transfer_size(spi); |
1248 | |
1249 | /* Transfer size limit must not be greater than message size limit */ |
1250 | return min(tr_max, msg_max); |
1251 | } |
1252 | |
1253 | /** |
1254 | * spi_is_bpw_supported - Check if bits per word is supported |
1255 | * @spi: SPI device |
1256 | * @bpw: Bits per word |
1257 | * |
1258 | * This function checks to see if the SPI controller supports @bpw. |
1259 | * |
1260 | * Returns: |
1261 | * True if @bpw is supported, false otherwise. |
1262 | */ |
1263 | static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) |
1264 | { |
1265 | u32 bpw_mask = spi->master->bits_per_word_mask; |
1266 | |
1267 | if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) |
1268 | return true; |
1269 | |
1270 | return false; |
1271 | } |
1272 | |
1273 | /** |
1274 | * spi_controller_xfer_timeout - Compute a suitable timeout value |
1275 | * @ctlr: SPI device |
1276 | * @xfer: Transfer descriptor |
1277 | * |
1278 | * Compute a relevant timeout value for the given transfer. We derive the time |
1279 | * that it would take on a single data line and take twice this amount of time |
1280 | * with a minimum of 500ms to avoid false positives on loaded systems. |
1281 | * |
1282 | * Returns: Transfer timeout value in milliseconds. |
1283 | */ |
1284 | static inline unsigned int spi_controller_xfer_timeout(struct spi_controller *ctlr, |
1285 | struct spi_transfer *xfer) |
1286 | { |
1287 | return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U); |
1288 | } |
1289 | |
1290 | /*---------------------------------------------------------------------------*/ |
1291 | |
1292 | /* SPI transfer replacement methods which make use of spi_res */ |
1293 | |
1294 | struct spi_replaced_transfers; |
1295 | typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, |
1296 | struct spi_message *msg, |
1297 | struct spi_replaced_transfers *res); |
1298 | /** |
1299 | * struct spi_replaced_transfers - structure describing the spi_transfer |
1300 | * replacements that have occurred |
1301 | * so that they can get reverted |
1302 | * @release: some extra release code to get executed prior to |
1303 | * releasing this structure |
1304 | * @extradata: pointer to some extra data if requested or NULL |
1305 | * @replaced_transfers: transfers that have been replaced and which need |
1306 | * to get restored |
1307 | * @replaced_after: the transfer after which the @replaced_transfers |
1308 | * are to get re-inserted |
1309 | * @inserted: number of transfers inserted |
1310 | * @inserted_transfers: array of spi_transfers of array-size @inserted, |
1311 | * that have been replacing replaced_transfers |
1312 | * |
1313 | * Note: that @extradata will point to @inserted_transfers[@inserted] |
1314 | * if some extra allocation is requested, so alignment will be the same |
1315 | * as for spi_transfers. |
1316 | */ |
1317 | struct spi_replaced_transfers { |
1318 | spi_replaced_release_t release; |
1319 | void *; |
1320 | struct list_head replaced_transfers; |
1321 | struct list_head *replaced_after; |
1322 | size_t inserted; |
1323 | struct spi_transfer inserted_transfers[]; |
1324 | }; |
1325 | |
1326 | /*---------------------------------------------------------------------------*/ |
1327 | |
1328 | /* SPI transfer transformation methods */ |
1329 | |
1330 | extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, |
1331 | struct spi_message *msg, |
1332 | size_t maxsize, |
1333 | gfp_t gfp); |
1334 | extern int spi_split_transfers_maxwords(struct spi_controller *ctlr, |
1335 | struct spi_message *msg, |
1336 | size_t maxwords, |
1337 | gfp_t gfp); |
1338 | |
1339 | /*---------------------------------------------------------------------------*/ |
1340 | |
1341 | /* |
1342 | * All these synchronous SPI transfer routines are utilities layered |
1343 | * over the core async transfer primitive. Here, "synchronous" means |
1344 | * they will sleep uninterruptibly until the async transfer completes. |
1345 | */ |
1346 | |
1347 | extern int spi_sync(struct spi_device *spi, struct spi_message *message); |
1348 | extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); |
1349 | extern int spi_bus_lock(struct spi_controller *ctlr); |
1350 | extern int spi_bus_unlock(struct spi_controller *ctlr); |
1351 | |
1352 | /** |
1353 | * spi_sync_transfer - synchronous SPI data transfer |
1354 | * @spi: device with which data will be exchanged |
1355 | * @xfers: An array of spi_transfers |
1356 | * @num_xfers: Number of items in the xfer array |
1357 | * Context: can sleep |
1358 | * |
1359 | * Does a synchronous SPI data transfer of the given spi_transfer array. |
1360 | * |
1361 | * For more specific semantics see spi_sync(). |
1362 | * |
1363 | * Return: zero on success, else a negative error code. |
1364 | */ |
1365 | static inline int |
1366 | spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, |
1367 | unsigned int num_xfers) |
1368 | { |
1369 | struct spi_message msg; |
1370 | |
1371 | spi_message_init_with_transfers(m: &msg, xfers, num_xfers); |
1372 | |
1373 | return spi_sync(spi, message: &msg); |
1374 | } |
1375 | |
1376 | /** |
1377 | * spi_write - SPI synchronous write |
1378 | * @spi: device to which data will be written |
1379 | * @buf: data buffer |
1380 | * @len: data buffer size |
1381 | * Context: can sleep |
1382 | * |
1383 | * This function writes the buffer @buf. |
1384 | * Callable only from contexts that can sleep. |
1385 | * |
1386 | * Return: zero on success, else a negative error code. |
1387 | */ |
1388 | static inline int |
1389 | spi_write(struct spi_device *spi, const void *buf, size_t len) |
1390 | { |
1391 | struct spi_transfer t = { |
1392 | .tx_buf = buf, |
1393 | .len = len, |
1394 | }; |
1395 | |
1396 | return spi_sync_transfer(spi, xfers: &t, num_xfers: 1); |
1397 | } |
1398 | |
1399 | /** |
1400 | * spi_read - SPI synchronous read |
1401 | * @spi: device from which data will be read |
1402 | * @buf: data buffer |
1403 | * @len: data buffer size |
1404 | * Context: can sleep |
1405 | * |
1406 | * This function reads the buffer @buf. |
1407 | * Callable only from contexts that can sleep. |
1408 | * |
1409 | * Return: zero on success, else a negative error code. |
1410 | */ |
1411 | static inline int |
1412 | spi_read(struct spi_device *spi, void *buf, size_t len) |
1413 | { |
1414 | struct spi_transfer t = { |
1415 | .rx_buf = buf, |
1416 | .len = len, |
1417 | }; |
1418 | |
1419 | return spi_sync_transfer(spi, xfers: &t, num_xfers: 1); |
1420 | } |
1421 | |
1422 | /* This copies txbuf and rxbuf data; for small transfers only! */ |
1423 | extern int spi_write_then_read(struct spi_device *spi, |
1424 | const void *txbuf, unsigned n_tx, |
1425 | void *rxbuf, unsigned n_rx); |
1426 | |
1427 | /** |
1428 | * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read |
1429 | * @spi: device with which data will be exchanged |
1430 | * @cmd: command to be written before data is read back |
1431 | * Context: can sleep |
1432 | * |
1433 | * Callable only from contexts that can sleep. |
1434 | * |
1435 | * Return: the (unsigned) eight bit number returned by the |
1436 | * device, or else a negative error code. |
1437 | */ |
1438 | static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) |
1439 | { |
1440 | ssize_t status; |
1441 | u8 result; |
1442 | |
1443 | status = spi_write_then_read(spi, txbuf: &cmd, n_tx: 1, rxbuf: &result, n_rx: 1); |
1444 | |
1445 | /* Return negative errno or unsigned value */ |
1446 | return (status < 0) ? status : result; |
1447 | } |
1448 | |
1449 | /** |
1450 | * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read |
1451 | * @spi: device with which data will be exchanged |
1452 | * @cmd: command to be written before data is read back |
1453 | * Context: can sleep |
1454 | * |
1455 | * The number is returned in wire-order, which is at least sometimes |
1456 | * big-endian. |
1457 | * |
1458 | * Callable only from contexts that can sleep. |
1459 | * |
1460 | * Return: the (unsigned) sixteen bit number returned by the |
1461 | * device, or else a negative error code. |
1462 | */ |
1463 | static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) |
1464 | { |
1465 | ssize_t status; |
1466 | u16 result; |
1467 | |
1468 | status = spi_write_then_read(spi, txbuf: &cmd, n_tx: 1, rxbuf: &result, n_rx: 2); |
1469 | |
1470 | /* Return negative errno or unsigned value */ |
1471 | return (status < 0) ? status : result; |
1472 | } |
1473 | |
1474 | /** |
1475 | * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read |
1476 | * @spi: device with which data will be exchanged |
1477 | * @cmd: command to be written before data is read back |
1478 | * Context: can sleep |
1479 | * |
1480 | * This function is similar to spi_w8r16, with the exception that it will |
1481 | * convert the read 16 bit data word from big-endian to native endianness. |
1482 | * |
1483 | * Callable only from contexts that can sleep. |
1484 | * |
1485 | * Return: the (unsigned) sixteen bit number returned by the device in CPU |
1486 | * endianness, or else a negative error code. |
1487 | */ |
1488 | static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) |
1489 | |
1490 | { |
1491 | ssize_t status; |
1492 | __be16 result; |
1493 | |
1494 | status = spi_write_then_read(spi, txbuf: &cmd, n_tx: 1, rxbuf: &result, n_rx: 2); |
1495 | if (status < 0) |
1496 | return status; |
1497 | |
1498 | return be16_to_cpu(result); |
1499 | } |
1500 | |
1501 | /*---------------------------------------------------------------------------*/ |
1502 | |
1503 | /* |
1504 | * INTERFACE between board init code and SPI infrastructure. |
1505 | * |
1506 | * No SPI driver ever sees these SPI device table segments, but |
1507 | * it's how the SPI core (or adapters that get hotplugged) grows |
1508 | * the driver model tree. |
1509 | * |
1510 | * As a rule, SPI devices can't be probed. Instead, board init code |
1511 | * provides a table listing the devices which are present, with enough |
1512 | * information to bind and set up the device's driver. There's basic |
1513 | * support for non-static configurations too; enough to handle adding |
1514 | * parport adapters, or microcontrollers acting as USB-to-SPI bridges. |
1515 | */ |
1516 | |
1517 | /** |
1518 | * struct spi_board_info - board-specific template for a SPI device |
1519 | * @modalias: Initializes spi_device.modalias; identifies the driver. |
1520 | * @platform_data: Initializes spi_device.platform_data; the particular |
1521 | * data stored there is driver-specific. |
1522 | * @swnode: Software node for the device. |
1523 | * @controller_data: Initializes spi_device.controller_data; some |
1524 | * controllers need hints about hardware setup, e.g. for DMA. |
1525 | * @irq: Initializes spi_device.irq; depends on how the board is wired. |
1526 | * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits |
1527 | * from the chip datasheet and board-specific signal quality issues. |
1528 | * @bus_num: Identifies which spi_controller parents the spi_device; unused |
1529 | * by spi_new_device(), and otherwise depends on board wiring. |
1530 | * @chip_select: Initializes spi_device.chip_select; depends on how |
1531 | * the board is wired. |
1532 | * @mode: Initializes spi_device.mode; based on the chip datasheet, board |
1533 | * wiring (some devices support both 3WIRE and standard modes), and |
1534 | * possibly presence of an inverter in the chipselect path. |
1535 | * |
1536 | * When adding new SPI devices to the device tree, these structures serve |
1537 | * as a partial device template. They hold information which can't always |
1538 | * be determined by drivers. Information that probe() can establish (such |
1539 | * as the default transfer wordsize) is not included here. |
1540 | * |
1541 | * These structures are used in two places. Their primary role is to |
1542 | * be stored in tables of board-specific device descriptors, which are |
1543 | * declared early in board initialization and then used (much later) to |
1544 | * populate a controller's device tree after the that controller's driver |
1545 | * initializes. A secondary (and atypical) role is as a parameter to |
1546 | * spi_new_device() call, which happens after those controller drivers |
1547 | * are active in some dynamic board configuration models. |
1548 | */ |
1549 | struct spi_board_info { |
1550 | /* |
1551 | * The device name and module name are coupled, like platform_bus; |
1552 | * "modalias" is normally the driver name. |
1553 | * |
1554 | * platform_data goes to spi_device.dev.platform_data, |
1555 | * controller_data goes to spi_device.controller_data, |
1556 | * IRQ is copied too. |
1557 | */ |
1558 | char modalias[SPI_NAME_SIZE]; |
1559 | const void *platform_data; |
1560 | const struct software_node *swnode; |
1561 | void *controller_data; |
1562 | int irq; |
1563 | |
1564 | /* Slower signaling on noisy or low voltage boards */ |
1565 | u32 max_speed_hz; |
1566 | |
1567 | |
1568 | /* |
1569 | * bus_num is board specific and matches the bus_num of some |
1570 | * spi_controller that will probably be registered later. |
1571 | * |
1572 | * chip_select reflects how this chip is wired to that master; |
1573 | * it's less than num_chipselect. |
1574 | */ |
1575 | u16 bus_num; |
1576 | u16 chip_select; |
1577 | |
1578 | /* |
1579 | * mode becomes spi_device.mode, and is essential for chips |
1580 | * where the default of SPI_CS_HIGH = 0 is wrong. |
1581 | */ |
1582 | u32 mode; |
1583 | |
1584 | /* |
1585 | * ... may need additional spi_device chip config data here. |
1586 | * avoid stuff protocol drivers can set; but include stuff |
1587 | * needed to behave without being bound to a driver: |
1588 | * - quirks like clock rate mattering when not selected |
1589 | */ |
1590 | }; |
1591 | |
1592 | #ifdef CONFIG_SPI |
1593 | extern int |
1594 | spi_register_board_info(struct spi_board_info const *info, unsigned n); |
1595 | #else |
1596 | /* Board init code may ignore whether SPI is configured or not */ |
1597 | static inline int |
1598 | spi_register_board_info(struct spi_board_info const *info, unsigned n) |
1599 | { return 0; } |
1600 | #endif |
1601 | |
1602 | /* |
1603 | * If you're hotplugging an adapter with devices (parport, USB, etc) |
1604 | * use spi_new_device() to describe each device. You can also call |
1605 | * spi_unregister_device() to start making that device vanish, but |
1606 | * normally that would be handled by spi_unregister_controller(). |
1607 | * |
1608 | * You can also use spi_alloc_device() and spi_add_device() to use a two |
1609 | * stage registration sequence for each spi_device. This gives the caller |
1610 | * some more control over the spi_device structure before it is registered, |
1611 | * but requires that caller to initialize fields that would otherwise |
1612 | * be defined using the board info. |
1613 | */ |
1614 | extern struct spi_device * |
1615 | spi_alloc_device(struct spi_controller *ctlr); |
1616 | |
1617 | extern int |
1618 | spi_add_device(struct spi_device *spi); |
1619 | |
1620 | extern struct spi_device * |
1621 | spi_new_device(struct spi_controller *, struct spi_board_info *); |
1622 | |
1623 | extern void spi_unregister_device(struct spi_device *spi); |
1624 | |
1625 | extern const struct spi_device_id * |
1626 | spi_get_device_id(const struct spi_device *sdev); |
1627 | |
1628 | extern const void * |
1629 | spi_get_device_match_data(const struct spi_device *sdev); |
1630 | |
1631 | static inline bool |
1632 | spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) |
1633 | { |
1634 | return list_is_last(list: &xfer->transfer_list, head: &ctlr->cur_msg->transfers); |
1635 | } |
1636 | |
1637 | /* Compatibility layer */ |
1638 | #define spi_master spi_controller |
1639 | |
1640 | #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX |
1641 | |
1642 | #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) |
1643 | #define spi_master_set_devdata(_ctlr, _data) \ |
1644 | spi_controller_set_devdata(_ctlr, _data) |
1645 | #define spi_master_get(_ctlr) spi_controller_get(_ctlr) |
1646 | #define spi_master_put(_ctlr) spi_controller_put(_ctlr) |
1647 | #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) |
1648 | #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) |
1649 | |
1650 | #define spi_register_master(_ctlr) spi_register_controller(_ctlr) |
1651 | #define devm_spi_register_master(_dev, _ctlr) \ |
1652 | devm_spi_register_controller(_dev, _ctlr) |
1653 | #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) |
1654 | |
1655 | #endif /* __LINUX_SPI_H */ |
1656 | |