1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * NetChip 2280 high/full speed USB device controller.
4 * Unlike many such controllers, this one talks PCI.
5 *
6 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
7 * Copyright (C) 2003 David Brownell
8 */
9
10#ifndef __LINUX_USB_NET2280_H
11#define __LINUX_USB_NET2280_H
12
13/*-------------------------------------------------------------------------*/
14
15/* NET2280 MEMORY MAPPED REGISTERS
16 *
17 * The register layout came from the chip documentation, and the bit
18 * number definitions were extracted from chip specification.
19 *
20 * Use the shift operator ('<<') to build bit masks, with readl/writel
21 * to access the registers through PCI.
22 */
23
24/* main registers, BAR0 + 0x0000 */
25struct net2280_regs {
26 /* offset 0x0000 */
27 u32 devinit;
28#define LOCAL_CLOCK_FREQUENCY 8
29#define FORCE_PCI_RESET 7
30#define PCI_ID 6
31#define PCI_ENABLE 5
32#define FIFO_SOFT_RESET 4
33#define CFG_SOFT_RESET 3
34#define PCI_SOFT_RESET 2
35#define USB_SOFT_RESET 1
36#define M8051_RESET 0
37 u32 eectl;
38#define EEPROM_ADDRESS_WIDTH 23
39#define EEPROM_CHIP_SELECT_ACTIVE 22
40#define EEPROM_PRESENT 21
41#define EEPROM_VALID 20
42#define EEPROM_BUSY 19
43#define EEPROM_CHIP_SELECT_ENABLE 18
44#define EEPROM_BYTE_READ_START 17
45#define EEPROM_BYTE_WRITE_START 16
46#define EEPROM_READ_DATA 8
47#define EEPROM_WRITE_DATA 0
48 u32 eeclkfreq;
49 u32 _unused0;
50 /* offset 0x0010 */
51
52 u32 pciirqenb0; /* interrupt PCI master ... */
53#define SETUP_PACKET_INTERRUPT_ENABLE 7
54#define ENDPOINT_F_INTERRUPT_ENABLE 6
55#define ENDPOINT_E_INTERRUPT_ENABLE 5
56#define ENDPOINT_D_INTERRUPT_ENABLE 4
57#define ENDPOINT_C_INTERRUPT_ENABLE 3
58#define ENDPOINT_B_INTERRUPT_ENABLE 2
59#define ENDPOINT_A_INTERRUPT_ENABLE 1
60#define ENDPOINT_0_INTERRUPT_ENABLE 0
61 u32 pciirqenb1;
62#define PCI_INTERRUPT_ENABLE 31
63#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
64#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
65#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
66#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
67#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
68#define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18
69#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
70#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
71#define GPIO_INTERRUPT_ENABLE 13
72#define DMA_D_INTERRUPT_ENABLE 12
73#define DMA_C_INTERRUPT_ENABLE 11
74#define DMA_B_INTERRUPT_ENABLE 10
75#define DMA_A_INTERRUPT_ENABLE 9
76#define EEPROM_DONE_INTERRUPT_ENABLE 8
77#define VBUS_INTERRUPT_ENABLE 7
78#define CONTROL_STATUS_INTERRUPT_ENABLE 6
79#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
80#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
81#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
82#define RESUME_INTERRUPT_ENABLE 1
83#define SOF_INTERRUPT_ENABLE 0
84 u32 cpu_irqenb0; /* ... or onboard 8051 */
85#define SETUP_PACKET_INTERRUPT_ENABLE 7
86#define ENDPOINT_F_INTERRUPT_ENABLE 6
87#define ENDPOINT_E_INTERRUPT_ENABLE 5
88#define ENDPOINT_D_INTERRUPT_ENABLE 4
89#define ENDPOINT_C_INTERRUPT_ENABLE 3
90#define ENDPOINT_B_INTERRUPT_ENABLE 2
91#define ENDPOINT_A_INTERRUPT_ENABLE 1
92#define ENDPOINT_0_INTERRUPT_ENABLE 0
93 u32 cpu_irqenb1;
94#define CPU_INTERRUPT_ENABLE 31
95#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
96#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
97#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
98#define PCI_INTA_INTERRUPT_ENABLE 24
99#define PCI_PME_INTERRUPT_ENABLE 23
100#define PCI_SERR_INTERRUPT_ENABLE 22
101#define PCI_PERR_INTERRUPT_ENABLE 21
102#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
103#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
104#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
105#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
106#define GPIO_INTERRUPT_ENABLE 13
107#define DMA_D_INTERRUPT_ENABLE 12
108#define DMA_C_INTERRUPT_ENABLE 11
109#define DMA_B_INTERRUPT_ENABLE 10
110#define DMA_A_INTERRUPT_ENABLE 9
111#define EEPROM_DONE_INTERRUPT_ENABLE 8
112#define VBUS_INTERRUPT_ENABLE 7
113#define CONTROL_STATUS_INTERRUPT_ENABLE 6
114#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
115#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
116#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
117#define RESUME_INTERRUPT_ENABLE 1
118#define SOF_INTERRUPT_ENABLE 0
119
120 /* offset 0x0020 */
121 u32 _unused1;
122 u32 usbirqenb1;
123#define USB_INTERRUPT_ENABLE 31
124#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
125#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
126#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
127#define PCI_INTA_INTERRUPT_ENABLE 24
128#define PCI_PME_INTERRUPT_ENABLE 23
129#define PCI_SERR_INTERRUPT_ENABLE 22
130#define PCI_PERR_INTERRUPT_ENABLE 21
131#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
132#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
133#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
134#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
135#define GPIO_INTERRUPT_ENABLE 13
136#define DMA_D_INTERRUPT_ENABLE 12
137#define DMA_C_INTERRUPT_ENABLE 11
138#define DMA_B_INTERRUPT_ENABLE 10
139#define DMA_A_INTERRUPT_ENABLE 9
140#define EEPROM_DONE_INTERRUPT_ENABLE 8
141#define VBUS_INTERRUPT_ENABLE 7
142#define CONTROL_STATUS_INTERRUPT_ENABLE 6
143#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
144#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
145#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
146#define RESUME_INTERRUPT_ENABLE 1
147#define SOF_INTERRUPT_ENABLE 0
148 u32 irqstat0;
149#define INTA_ASSERTED 12
150#define SETUP_PACKET_INTERRUPT 7
151#define ENDPOINT_F_INTERRUPT 6
152#define ENDPOINT_E_INTERRUPT 5
153#define ENDPOINT_D_INTERRUPT 4
154#define ENDPOINT_C_INTERRUPT 3
155#define ENDPOINT_B_INTERRUPT 2
156#define ENDPOINT_A_INTERRUPT 1
157#define ENDPOINT_0_INTERRUPT 0
158#define USB3380_IRQSTAT0_EP_INTR_MASK_IN (0xF << 17)
159#define USB3380_IRQSTAT0_EP_INTR_MASK_OUT (0xF << 1)
160
161 u32 irqstat1;
162#define POWER_STATE_CHANGE_INTERRUPT 27
163#define PCI_ARBITER_TIMEOUT_INTERRUPT 26
164#define PCI_PARITY_ERROR_INTERRUPT 25
165#define PCI_INTA_INTERRUPT 24
166#define PCI_PME_INTERRUPT 23
167#define PCI_SERR_INTERRUPT 22
168#define PCI_PERR_INTERRUPT 21
169#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20
170#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19
171#define PCI_RETRY_ABORT_INTERRUPT 17
172#define PCI_MASTER_CYCLE_DONE_INTERRUPT 16
173#define SOF_DOWN_INTERRUPT 14
174#define GPIO_INTERRUPT 13
175#define DMA_D_INTERRUPT 12
176#define DMA_C_INTERRUPT 11
177#define DMA_B_INTERRUPT 10
178#define DMA_A_INTERRUPT 9
179#define EEPROM_DONE_INTERRUPT 8
180#define VBUS_INTERRUPT 7
181#define CONTROL_STATUS_INTERRUPT 6
182#define ROOT_PORT_RESET_INTERRUPT 4
183#define SUSPEND_REQUEST_INTERRUPT 3
184#define SUSPEND_REQUEST_CHANGE_INTERRUPT 2
185#define RESUME_INTERRUPT 1
186#define SOF_INTERRUPT 0
187 /* offset 0x0030 */
188 u32 idxaddr;
189 u32 idxdata;
190 u32 fifoctl;
191#define PCI_BASE2_RANGE 16
192#define IGNORE_FIFO_AVAILABILITY 3
193#define PCI_BASE2_SELECT 2
194#define FIFO_CONFIGURATION_SELECT 0
195 u32 _unused2;
196 /* offset 0x0040 */
197 u32 memaddr;
198#define START 28
199#define DIRECTION 27
200#define FIFO_DIAGNOSTIC_SELECT 24
201#define MEMORY_ADDRESS 0
202 u32 memdata0;
203 u32 memdata1;
204 u32 _unused3;
205 /* offset 0x0050 */
206 u32 gpioctl;
207#define GPIO3_LED_SELECT 12
208#define GPIO3_INTERRUPT_ENABLE 11
209#define GPIO2_INTERRUPT_ENABLE 10
210#define GPIO1_INTERRUPT_ENABLE 9
211#define GPIO0_INTERRUPT_ENABLE 8
212#define GPIO3_OUTPUT_ENABLE 7
213#define GPIO2_OUTPUT_ENABLE 6
214#define GPIO1_OUTPUT_ENABLE 5
215#define GPIO0_OUTPUT_ENABLE 4
216#define GPIO3_DATA 3
217#define GPIO2_DATA 2
218#define GPIO1_DATA 1
219#define GPIO0_DATA 0
220 u32 gpiostat;
221#define GPIO3_INTERRUPT 3
222#define GPIO2_INTERRUPT 2
223#define GPIO1_INTERRUPT 1
224#define GPIO0_INTERRUPT 0
225} __attribute__ ((packed));
226
227/* usb control, BAR0 + 0x0080 */
228struct net2280_usb_regs {
229 /* offset 0x0080 */
230 u32 stdrsp;
231#define STALL_UNSUPPORTED_REQUESTS 31
232#define SET_TEST_MODE 16
233#define GET_OTHER_SPEED_CONFIGURATION 15
234#define GET_DEVICE_QUALIFIER 14
235#define SET_ADDRESS 13
236#define ENDPOINT_SET_CLEAR_HALT 12
237#define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11
238#define GET_STRING_DESCRIPTOR_2 10
239#define GET_STRING_DESCRIPTOR_1 9
240#define GET_STRING_DESCRIPTOR_0 8
241#define GET_SET_INTERFACE 6
242#define GET_SET_CONFIGURATION 5
243#define GET_CONFIGURATION_DESCRIPTOR 4
244#define GET_DEVICE_DESCRIPTOR 3
245#define GET_ENDPOINT_STATUS 2
246#define GET_INTERFACE_STATUS 1
247#define GET_DEVICE_STATUS 0
248 u32 prodvendid;
249#define PRODUCT_ID 16
250#define VENDOR_ID 0
251 u32 relnum;
252 u32 usbctl;
253#define SERIAL_NUMBER_INDEX 16
254#define PRODUCT_ID_STRING_ENABLE 13
255#define VENDOR_ID_STRING_ENABLE 12
256#define USB_ROOT_PORT_WAKEUP_ENABLE 11
257#define VBUS_PIN 10
258#define TIMED_DISCONNECT 9
259#define SUSPEND_IMMEDIATELY 7
260#define SELF_POWERED_USB_DEVICE 6
261#define REMOTE_WAKEUP_SUPPORT 5
262#define PME_POLARITY 4
263#define USB_DETECT_ENABLE 3
264#define PME_WAKEUP_ENABLE 2
265#define DEVICE_REMOTE_WAKEUP_ENABLE 1
266#define SELF_POWERED_STATUS 0
267 /* offset 0x0090 */
268 u32 usbstat;
269#define HIGH_SPEED 7
270#define FULL_SPEED 6
271#define GENERATE_RESUME 5
272#define GENERATE_DEVICE_REMOTE_WAKEUP 4
273 u32 xcvrdiag;
274#define FORCE_HIGH_SPEED_MODE 31
275#define FORCE_FULL_SPEED_MODE 30
276#define USB_TEST_MODE 24
277#define LINE_STATE 16
278#define TRANSCEIVER_OPERATION_MODE 2
279#define TRANSCEIVER_SELECT 1
280#define TERMINATION_SELECT 0
281 u32 setup0123;
282 u32 setup4567;
283 /* offset 0x0090 */
284 u32 _unused0;
285 u32 ouraddr;
286#define FORCE_IMMEDIATE 7
287#define OUR_USB_ADDRESS 0
288 u32 ourconfig;
289} __attribute__ ((packed));
290
291/* pci control, BAR0 + 0x0100 */
292struct net2280_pci_regs {
293 /* offset 0x0100 */
294 u32 pcimstctl;
295#define PCI_ARBITER_PARK_SELECT 13
296#define PCI_MULTI LEVEL_ARBITER 12
297#define PCI_RETRY_ABORT_ENABLE 11
298#define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10
299#define DMA_READ_MULTIPLE_ENABLE 9
300#define DMA_READ_LINE_ENABLE 8
301#define PCI_MASTER_COMMAND_SELECT 6
302#define MEM_READ_OR_WRITE 0
303#define IO_READ_OR_WRITE 1
304#define CFG_READ_OR_WRITE 2
305#define PCI_MASTER_START 5
306#define PCI_MASTER_READ_WRITE 4
307#define PCI_MASTER_WRITE 0
308#define PCI_MASTER_READ 1
309#define PCI_MASTER_BYTE_WRITE_ENABLES 0
310 u32 pcimstaddr;
311 u32 pcimstdata;
312 u32 pcimststat;
313#define PCI_ARBITER_CLEAR 2
314#define PCI_EXTERNAL_ARBITER 1
315#define PCI_HOST_MODE 0
316} __attribute__ ((packed));
317
318/* dma control, BAR0 + 0x0180 ... array of four structs like this,
319 * for channels 0..3. see also struct net2280_dma: descriptor
320 * that can be loaded into some of these registers.
321 */
322struct net2280_dma_regs { /* [11.7] */
323 /* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */
324 u32 dmactl;
325#define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25
326#define DMA_CLEAR_COUNT_ENABLE 21
327#define DESCRIPTOR_POLLING_RATE 19
328#define POLL_CONTINUOUS 0
329#define POLL_1_USEC 1
330#define POLL_100_USEC 2
331#define POLL_1_MSEC 3
332#define DMA_VALID_BIT_POLLING_ENABLE 18
333#define DMA_VALID_BIT_ENABLE 17
334#define DMA_SCATTER_GATHER_ENABLE 16
335#define DMA_OUT_AUTO_START_ENABLE 4
336#define DMA_PREEMPT_ENABLE 3
337#define DMA_FIFO_VALIDATE 2
338#define DMA_ENABLE 1
339#define DMA_ADDRESS_HOLD 0
340 u32 dmastat;
341#define DMA_ABORT_DONE_INTERRUPT 27
342#define DMA_SCATTER_GATHER_DONE_INTERRUPT 25
343#define DMA_TRANSACTION_DONE_INTERRUPT 24
344#define DMA_ABORT 1
345#define DMA_START 0
346 u32 _unused0[2];
347 /* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */
348 u32 dmacount;
349#define VALID_BIT 31
350#define DMA_DIRECTION 30
351#define DMA_DONE_INTERRUPT_ENABLE 29
352#define END_OF_CHAIN 28
353#define DMA_BYTE_COUNT_MASK ((1<<24)-1)
354#define DMA_BYTE_COUNT 0
355 u32 dmaaddr;
356 u32 dmadesc;
357 u32 _unused1;
358} __attribute__ ((packed));
359
360/* dedicated endpoint registers, BAR0 + 0x0200 */
361
362struct net2280_dep_regs { /* [11.8] */
363 /* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */
364 u32 dep_cfg;
365 /* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */
366 u32 dep_rsp;
367 u32 _unused[2];
368} __attribute__ ((packed));
369
370/* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
371 * like this, for ep0 then the configurable endpoints A..F
372 * ep0 reserved for control; E and F have only 64 bytes of fifo
373 */
374struct net2280_ep_regs { /* [11.9] */
375 /* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */
376 u32 ep_cfg;
377#define ENDPOINT_BYTE_COUNT 16
378#define ENDPOINT_ENABLE 10
379#define ENDPOINT_TYPE 8
380#define ENDPOINT_DIRECTION 7
381#define ENDPOINT_NUMBER 0
382 u32 ep_rsp;
383#define SET_NAK_OUT_PACKETS 15
384#define SET_EP_HIDE_STATUS_PHASE 14
385#define SET_EP_FORCE_CRC_ERROR 13
386#define SET_INTERRUPT_MODE 12
387#define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11
388#define SET_NAK_OUT_PACKETS_MODE 10
389#define SET_ENDPOINT_TOGGLE 9
390#define SET_ENDPOINT_HALT 8
391#define CLEAR_NAK_OUT_PACKETS 7
392#define CLEAR_EP_HIDE_STATUS_PHASE 6
393#define CLEAR_EP_FORCE_CRC_ERROR 5
394#define CLEAR_INTERRUPT_MODE 4
395#define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3
396#define CLEAR_NAK_OUT_PACKETS_MODE 2
397#define CLEAR_ENDPOINT_TOGGLE 1
398#define CLEAR_ENDPOINT_HALT 0
399 u32 ep_irqenb;
400#define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6
401#define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5
402#define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
403#define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
404#define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1
405#define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
406 u32 ep_stat;
407#define FIFO_VALID_COUNT 24
408#define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22
409#define TIMEOUT 21
410#define USB_STALL_SENT 20
411#define USB_IN_NAK_SENT 19
412#define USB_IN_ACK_RCVD 18
413#define USB_OUT_PING_NAK_SENT 17
414#define USB_OUT_ACK_SENT 16
415#define FIFO_OVERFLOW 13
416#define FIFO_UNDERFLOW 12
417#define FIFO_FULL 11
418#define FIFO_EMPTY 10
419#define FIFO_FLUSH 9
420#define SHORT_PACKET_OUT_DONE_INTERRUPT 6
421#define SHORT_PACKET_TRANSFERRED_INTERRUPT 5
422#define NAK_OUT_PACKETS 4
423#define DATA_PACKET_RECEIVED_INTERRUPT 3
424#define DATA_PACKET_TRANSMITTED_INTERRUPT 2
425#define DATA_OUT_PING_TOKEN_INTERRUPT 1
426#define DATA_IN_TOKEN_INTERRUPT 0
427 /* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */
428 u32 ep_avail;
429 u32 ep_data;
430 u32 _unused0[2];
431} __attribute__ ((packed));
432
433#endif /* __LINUX_USB_NET2280_H */
434

source code of linux/include/linux/usb/net2280.h