| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * cisreg.h |
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| 4 | * |
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| 5 | * The initial developer of the original code is David A. Hinds |
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| 6 | * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds |
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| 7 | * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. |
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| 8 | * |
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| 9 | * (C) 1999 David A. Hinds |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _LINUX_CISREG_H |
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| 13 | #define _LINUX_CISREG_H |
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| 14 | |
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| 15 | /* |
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| 16 | * Offsets from ConfigBase for CIS registers |
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| 17 | */ |
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| 18 | #define CISREG_COR 0x00 |
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| 19 | #define CISREG_CCSR 0x02 |
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| 20 | #define CISREG_PRR 0x04 |
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| 21 | #define CISREG_SCR 0x06 |
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| 22 | #define CISREG_ESR 0x08 |
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| 23 | #define CISREG_IOBASE_0 0x0a |
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| 24 | #define CISREG_IOBASE_1 0x0c |
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| 25 | #define CISREG_IOBASE_2 0x0e |
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| 26 | #define CISREG_IOBASE_3 0x10 |
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| 27 | #define CISREG_IOSIZE 0x12 |
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| 28 | |
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| 29 | /* |
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| 30 | * Configuration Option Register |
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| 31 | */ |
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| 32 | #define COR_CONFIG_MASK 0x3f |
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| 33 | #define COR_MFC_CONFIG_MASK 0x38 |
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| 34 | #define COR_FUNC_ENA 0x01 |
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| 35 | #define COR_ADDR_DECODE 0x02 |
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| 36 | #define COR_IREQ_ENA 0x04 |
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| 37 | #define COR_LEVEL_REQ 0x40 |
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| 38 | #define COR_SOFT_RESET 0x80 |
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| 39 | |
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| 40 | /* |
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| 41 | * Card Configuration and Status Register |
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| 42 | */ |
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| 43 | #define CCSR_INTR_ACK 0x01 |
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| 44 | #define CCSR_INTR_PENDING 0x02 |
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| 45 | #define CCSR_POWER_DOWN 0x04 |
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| 46 | #define CCSR_AUDIO_ENA 0x08 |
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| 47 | #define CCSR_IOIS8 0x20 |
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| 48 | #define CCSR_SIGCHG_ENA 0x40 |
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| 49 | #define CCSR_CHANGED 0x80 |
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| 50 | |
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| 51 | /* |
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| 52 | * Pin Replacement Register |
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| 53 | */ |
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| 54 | #define PRR_WP_STATUS 0x01 |
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| 55 | #define PRR_READY_STATUS 0x02 |
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| 56 | #define PRR_BVD2_STATUS 0x04 |
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| 57 | #define PRR_BVD1_STATUS 0x08 |
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| 58 | #define PRR_WP_EVENT 0x10 |
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| 59 | #define PRR_READY_EVENT 0x20 |
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| 60 | #define PRR_BVD2_EVENT 0x40 |
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| 61 | #define PRR_BVD1_EVENT 0x80 |
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| 62 | |
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| 63 | /* |
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| 64 | * Socket and Copy Register |
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| 65 | */ |
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| 66 | #define SCR_SOCKET_NUM 0x0f |
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| 67 | #define SCR_COPY_NUM 0x70 |
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| 68 | |
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| 69 | /* |
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| 70 | * Extended Status Register |
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| 71 | */ |
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| 72 | #define ESR_REQ_ATTN_ENA 0x01 |
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| 73 | #define ESR_REQ_ATTN 0x10 |
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| 74 | |
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| 75 | /* |
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| 76 | * CardBus Function Status Registers |
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| 77 | */ |
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| 78 | #define CBFN_EVENT 0x00 |
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| 79 | #define CBFN_MASK 0x04 |
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| 80 | #define CBFN_STATE 0x08 |
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| 81 | #define CBFN_FORCE 0x0c |
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| 82 | |
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| 83 | /* |
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| 84 | * These apply to all the CardBus function registers |
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| 85 | */ |
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| 86 | #define CBFN_WP 0x0001 |
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| 87 | #define CBFN_READY 0x0002 |
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| 88 | #define CBFN_BVD2 0x0004 |
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| 89 | #define CBFN_BVD1 0x0008 |
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| 90 | #define CBFN_GWAKE 0x0010 |
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| 91 | #define CBFN_INTR 0x8000 |
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| 92 | |
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| 93 | /* |
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| 94 | * Extra bits in the Function Event Mask Register |
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| 95 | */ |
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| 96 | #define FEMR_BAM_ENA 0x0020 |
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| 97 | #define FEMR_PWM_ENA 0x0040 |
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| 98 | #define FEMR_WKUP_MASK 0x4000 |
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| 99 | |
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| 100 | /* |
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| 101 | * Indirect Addressing Registers for Zoomed Video: these are addresses |
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| 102 | * in common memory space |
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| 103 | */ |
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| 104 | #define CISREG_ICTRL0 0x02 /* control registers */ |
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| 105 | #define CISREG_ICTRL1 0x03 |
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| 106 | #define CISREG_IADDR0 0x04 /* address registers */ |
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| 107 | #define CISREG_IADDR1 0x05 |
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| 108 | #define CISREG_IADDR2 0x06 |
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| 109 | #define CISREG_IADDR3 0x07 |
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| 110 | #define CISREG_IDATA0 0x08 /* data registers */ |
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| 111 | #define CISREG_IDATA1 0x09 |
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| 112 | |
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| 113 | #define ICTRL0_COMMON 0x01 |
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| 114 | #define ICTRL0_AUTOINC 0x02 |
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| 115 | #define ICTRL0_BYTEGRAN 0x04 |
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| 116 | |
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| 117 | #endif /* _LINUX_CISREG_H */ |
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| 118 | |
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