| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Microchip SAMA7 SFRBU registers offsets and bit definitions. |
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| 4 | * |
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| 5 | * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries |
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| 6 | * |
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| 7 | * Author: Claudu Beznea <claudiu.beznea@microchip.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __SAMA7_SFRBU_H__ |
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| 11 | #define __SAMA7_SFRBU_H__ |
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| 12 | |
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| 13 | #ifdef CONFIG_SOC_SAMA7 |
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| 14 | |
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| 15 | #define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ |
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| 16 | #define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ |
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| 17 | #define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ |
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| 18 | #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ |
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| 19 | #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ |
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| 20 | |
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| 21 | #define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ |
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| 22 | #define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ |
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| 23 | #define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ |
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| 24 | #define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ |
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| 25 | #define AT91_SFRBU_PD_VALUE_MSK (0x3) |
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| 26 | #define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ |
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| 27 | |
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| 28 | #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ |
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| 29 | #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ |
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| 30 | |
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| 31 | #endif /* CONFIG_SOC_SAMA7 */ |
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| 32 | |
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| 33 | #endif /* __SAMA7_SFRBU_H__ */ |
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| 34 | |
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| 35 | |
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