| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> |
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| 4 | * Copyright (c) 2020 Western Digital Corporation or its affiliates. |
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| 5 | */ |
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| 6 | #ifndef K210_SYSCTL_H |
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| 7 | #define K210_SYSCTL_H |
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| 8 | |
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| 9 | /* |
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| 10 | * Kendryte K210 SoC system controller registers offsets. |
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| 11 | * Taken from Kendryte SDK (kendryte-standalone-sdk). |
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| 12 | */ |
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| 13 | #define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ |
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| 14 | #define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ |
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| 15 | #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ |
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| 16 | #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ |
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| 17 | #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ |
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| 18 | #define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ |
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| 19 | #define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ |
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| 20 | #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ |
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| 21 | #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ |
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| 22 | #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ |
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| 23 | #define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ |
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| 24 | #define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ |
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| 25 | #define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ |
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| 26 | #define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ |
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| 27 | #define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ |
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| 28 | #define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ |
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| 29 | #define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ |
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| 30 | #define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ |
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| 31 | #define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ |
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| 32 | #define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ |
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| 33 | #define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ |
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| 34 | #define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ |
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| 35 | #define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ |
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| 36 | #define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ |
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| 37 | #define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ |
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| 38 | #define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ |
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| 39 | #define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ |
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| 40 | |
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| 41 | void k210_clk_early_init(void __iomem *regs); |
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| 42 | |
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| 43 | #endif |
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| 44 | |
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