1 | /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */ |
2 | /* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */ |
3 | |
4 | #ifndef __LIMA_DRM_H__ |
5 | #define __LIMA_DRM_H__ |
6 | |
7 | #include "drm.h" |
8 | |
9 | #if defined(__cplusplus) |
10 | extern "C" { |
11 | #endif |
12 | |
13 | enum drm_lima_param_gpu_id { |
14 | DRM_LIMA_PARAM_GPU_ID_UNKNOWN, |
15 | DRM_LIMA_PARAM_GPU_ID_MALI400, |
16 | DRM_LIMA_PARAM_GPU_ID_MALI450, |
17 | }; |
18 | |
19 | enum drm_lima_param { |
20 | DRM_LIMA_PARAM_GPU_ID, |
21 | DRM_LIMA_PARAM_NUM_PP, |
22 | DRM_LIMA_PARAM_GP_VERSION, |
23 | DRM_LIMA_PARAM_PP_VERSION, |
24 | }; |
25 | |
26 | /** |
27 | * get various information of the GPU |
28 | */ |
29 | struct drm_lima_get_param { |
30 | __u32 param; /* in, value in enum drm_lima_param */ |
31 | __u32 pad; /* pad, must be zero */ |
32 | __u64 value; /* out, parameter value */ |
33 | }; |
34 | |
35 | /* |
36 | * heap buffer dynamically increase backup memory size when GP task fail |
37 | * due to lack of heap memory. size field of heap buffer is an up bound of |
38 | * the backup memory which can be set to a fairly large value. |
39 | */ |
40 | #define LIMA_BO_FLAG_HEAP (1 << 0) |
41 | |
42 | /** |
43 | * create a buffer for used by GPU |
44 | */ |
45 | struct drm_lima_gem_create { |
46 | __u32 size; /* in, buffer size */ |
47 | __u32 flags; /* in, buffer flags */ |
48 | __u32 handle; /* out, GEM buffer handle */ |
49 | __u32 pad; /* pad, must be zero */ |
50 | }; |
51 | |
52 | /** |
53 | * get information of a buffer |
54 | */ |
55 | struct drm_lima_gem_info { |
56 | __u32 handle; /* in, GEM buffer handle */ |
57 | __u32 va; /* out, virtual address mapped into GPU MMU */ |
58 | __u64 offset; /* out, used to mmap this buffer to CPU */ |
59 | }; |
60 | |
61 | #define LIMA_SUBMIT_BO_READ 0x01 |
62 | #define LIMA_SUBMIT_BO_WRITE 0x02 |
63 | |
64 | /* buffer information used by one task */ |
65 | struct drm_lima_gem_submit_bo { |
66 | __u32 handle; /* in, GEM buffer handle */ |
67 | __u32 flags; /* in, buffer read/write by GPU */ |
68 | }; |
69 | |
70 | #define LIMA_GP_FRAME_REG_NUM 6 |
71 | |
72 | /* frame used to setup GP for each task */ |
73 | struct drm_lima_gp_frame { |
74 | __u32 frame[LIMA_GP_FRAME_REG_NUM]; |
75 | }; |
76 | |
77 | #define LIMA_PP_FRAME_REG_NUM 23 |
78 | #define LIMA_PP_WB_REG_NUM 12 |
79 | |
80 | /* frame used to setup mali400 GPU PP for each task */ |
81 | struct drm_lima_m400_pp_frame { |
82 | __u32 frame[LIMA_PP_FRAME_REG_NUM]; |
83 | __u32 num_pp; |
84 | __u32 wb[3 * LIMA_PP_WB_REG_NUM]; |
85 | __u32 plbu_array_address[4]; |
86 | __u32 fragment_stack_address[4]; |
87 | }; |
88 | |
89 | /* frame used to setup mali450 GPU PP for each task */ |
90 | struct drm_lima_m450_pp_frame { |
91 | __u32 frame[LIMA_PP_FRAME_REG_NUM]; |
92 | __u32 num_pp; |
93 | __u32 wb[3 * LIMA_PP_WB_REG_NUM]; |
94 | __u32 use_dlbu; |
95 | __u32 _pad; |
96 | union { |
97 | __u32 plbu_array_address[8]; |
98 | __u32 dlbu_regs[4]; |
99 | }; |
100 | __u32 fragment_stack_address[8]; |
101 | }; |
102 | |
103 | #define LIMA_PIPE_GP 0x00 |
104 | #define LIMA_PIPE_PP 0x01 |
105 | |
106 | #define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0) |
107 | |
108 | /** |
109 | * submit a task to GPU |
110 | * |
111 | * User can always merge multi sync_file and drm_syncobj |
112 | * into one drm_syncobj as in_sync[0], but we reserve |
113 | * in_sync[1] for another task's out_sync to avoid the |
114 | * export/import/merge pass when explicit sync. |
115 | */ |
116 | struct drm_lima_gem_submit { |
117 | __u32 ctx; /* in, context handle task is submitted to */ |
118 | __u32 pipe; /* in, which pipe to use, GP/PP */ |
119 | __u32 nr_bos; /* in, array length of bos field */ |
120 | __u32 frame_size; /* in, size of frame field */ |
121 | __u64 bos; /* in, array of drm_lima_gem_submit_bo */ |
122 | __u64 frame; /* in, GP/PP frame */ |
123 | __u32 flags; /* in, submit flags */ |
124 | __u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */ |
125 | __u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */ |
126 | }; |
127 | |
128 | #define LIMA_GEM_WAIT_READ 0x01 |
129 | #define LIMA_GEM_WAIT_WRITE 0x02 |
130 | |
131 | /** |
132 | * wait pending GPU task finish of a buffer |
133 | */ |
134 | struct drm_lima_gem_wait { |
135 | __u32 handle; /* in, GEM buffer handle */ |
136 | __u32 op; /* in, CPU want to read/write this buffer */ |
137 | __s64 timeout_ns; /* in, wait timeout in absulute time */ |
138 | }; |
139 | |
140 | /** |
141 | * create a context |
142 | */ |
143 | struct drm_lima_ctx_create { |
144 | __u32 id; /* out, context handle */ |
145 | __u32 _pad; /* pad, must be zero */ |
146 | }; |
147 | |
148 | /** |
149 | * free a context |
150 | */ |
151 | struct drm_lima_ctx_free { |
152 | __u32 id; /* in, context handle */ |
153 | __u32 _pad; /* pad, must be zero */ |
154 | }; |
155 | |
156 | #define DRM_LIMA_GET_PARAM 0x00 |
157 | #define DRM_LIMA_GEM_CREATE 0x01 |
158 | #define DRM_LIMA_GEM_INFO 0x02 |
159 | #define DRM_LIMA_GEM_SUBMIT 0x03 |
160 | #define DRM_LIMA_GEM_WAIT 0x04 |
161 | #define DRM_LIMA_CTX_CREATE 0x05 |
162 | #define DRM_LIMA_CTX_FREE 0x06 |
163 | |
164 | #define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) |
165 | #define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create) |
166 | #define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) |
167 | #define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) |
168 | #define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) |
169 | #define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create) |
170 | #define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) |
171 | |
172 | #if defined(__cplusplus) |
173 | } |
174 | #endif |
175 | |
176 | #endif /* __LIMA_DRM_H__ */ |
177 | |