1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2009 Marvell International Ltd. |
4 | */ |
5 | |
6 | #ifndef __ASM_MACH_PXA168FB_H |
7 | #define __ASM_MACH_PXA168FB_H |
8 | |
9 | #include <linux/fb.h> |
10 | #include <linux/interrupt.h> |
11 | |
12 | /* Dumb interface */ |
13 | #define PIN_MODE_DUMB_24 0 |
14 | #define PIN_MODE_DUMB_18_SPI 1 |
15 | #define PIN_MODE_DUMB_18_GPIO 2 |
16 | #define PIN_MODE_DUMB_16_SPI 3 |
17 | #define PIN_MODE_DUMB_16_GPIO 4 |
18 | #define PIN_MODE_DUMB_12_SPI_GPIO 5 |
19 | #define PIN_MODE_SMART_18_SPI 6 |
20 | #define PIN_MODE_SMART_16_SPI 7 |
21 | #define PIN_MODE_SMART_8_SPI_GPIO 8 |
22 | |
23 | /* Dumb interface pin allocation */ |
24 | #define DUMB_MODE_RGB565 0 |
25 | #define DUMB_MODE_RGB565_UPPER 1 |
26 | #define DUMB_MODE_RGB666 2 |
27 | #define DUMB_MODE_RGB666_UPPER 3 |
28 | #define DUMB_MODE_RGB444 4 |
29 | #define DUMB_MODE_RGB444_UPPER 5 |
30 | #define DUMB_MODE_RGB888 6 |
31 | |
32 | /* default fb buffer size WVGA-32bits */ |
33 | #define DEFAULT_FB_SIZE (800 * 480 * 4) |
34 | |
35 | /* |
36 | * Buffer pixel format |
37 | * bit0 is for rb swap. |
38 | * bit12 is for Y UorV swap |
39 | */ |
40 | #define PIX_FMT_RGB565 0 |
41 | #define PIX_FMT_BGR565 1 |
42 | #define PIX_FMT_RGB1555 2 |
43 | #define PIX_FMT_BGR1555 3 |
44 | #define PIX_FMT_RGB888PACK 4 |
45 | #define PIX_FMT_BGR888PACK 5 |
46 | #define PIX_FMT_RGB888UNPACK 6 |
47 | #define PIX_FMT_BGR888UNPACK 7 |
48 | #define PIX_FMT_RGBA888 8 |
49 | #define PIX_FMT_BGRA888 9 |
50 | #define PIX_FMT_YUV422PACK 10 |
51 | #define PIX_FMT_YVU422PACK 11 |
52 | #define PIX_FMT_YUV422PLANAR 12 |
53 | #define PIX_FMT_YVU422PLANAR 13 |
54 | #define PIX_FMT_YUV420PLANAR 14 |
55 | #define PIX_FMT_YVU420PLANAR 15 |
56 | #define PIX_FMT_PSEUDOCOLOR 20 |
57 | #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) |
58 | |
59 | /* |
60 | * PXA LCD controller private state. |
61 | */ |
62 | struct pxa168fb_info { |
63 | struct device *dev; |
64 | struct clk *clk; |
65 | struct fb_info *info; |
66 | |
67 | void __iomem *reg_base; |
68 | dma_addr_t fb_start_dma; |
69 | u32 pseudo_palette[16]; |
70 | |
71 | int pix_fmt; |
72 | unsigned is_blanked:1; |
73 | unsigned panel_rbswap:1; |
74 | unsigned active:1; |
75 | }; |
76 | |
77 | /* |
78 | * PXA fb machine information |
79 | */ |
80 | struct pxa168fb_mach_info { |
81 | char id[16]; |
82 | |
83 | int num_modes; |
84 | struct fb_videomode *modes; |
85 | |
86 | /* |
87 | * Pix_fmt |
88 | */ |
89 | unsigned pix_fmt; |
90 | |
91 | /* |
92 | * I/O pin allocation. |
93 | */ |
94 | unsigned io_pin_allocation_mode:4; |
95 | |
96 | /* |
97 | * Dumb panel -- assignment of R/G/B component info to the 24 |
98 | * available external data lanes. |
99 | */ |
100 | unsigned dumb_mode:4; |
101 | unsigned panel_rgb_reverse_lanes:1; |
102 | |
103 | /* |
104 | * Dumb panel -- GPIO output data. |
105 | */ |
106 | unsigned gpio_output_mask:8; |
107 | unsigned gpio_output_data:8; |
108 | |
109 | /* |
110 | * Dumb panel -- configurable output signal polarity. |
111 | */ |
112 | unsigned invert_composite_blank:1; |
113 | unsigned invert_pix_val_ena:1; |
114 | unsigned invert_pixclock:1; |
115 | unsigned panel_rbswap:1; |
116 | unsigned active:1; |
117 | unsigned enable_lcd:1; |
118 | }; |
119 | |
120 | #endif /* __ASM_MACH_PXA168FB_H */ |
121 | |