| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Copyright (c) 2022 Analog Devices Inc. */ |
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| 3 | |
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| 4 | #ifndef _MAX98363_H |
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| 5 | #define _MAX98363_H |
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| 6 | |
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| 7 | #define MAX98363_R2000_SW_RESET 0x2000 |
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| 8 | #define MAX98363_R2001_INTR_RAW 0x2001 |
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| 9 | #define MAX98363_R2003_INTR_STATE 0x2003 |
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| 10 | #define MAX98363_R2005_INTR_FALG 0x2005 |
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| 11 | #define MAX98363_R2007_INTR_EN 0x2007 |
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| 12 | #define MAX98363_R2009_INTR_CLR 0x2009 |
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| 13 | #define MAX98363_R2021_ERR_MON_CTRL 0x2021 |
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| 14 | #define MAX98363_R2022_SPK_MON_THRESH 0x2022 |
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| 15 | #define MAX98363_R2023_SPK_MON_DURATION 0x2023 |
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| 16 | #define MAX98363_R2030_TONE_GEN_CFG 0x2030 |
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| 17 | #define MAX98363_R203F_TONE_GEN_EN 0x203F |
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| 18 | #define MAX98363_R2040_AMP_VOL 0x2040 |
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| 19 | #define MAX98363_R2041_AMP_GAIN 0x2041 |
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| 20 | #define MAX98363_R2042_DSP_CFG 0x2042 |
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| 21 | #define MAX98363_R21FF_REV_ID 0x21FF |
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| 22 | |
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| 23 | /* MAX98363_R2021_ERR_MON_CTRL */ |
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| 24 | #define MAX98363_SPKMON_SHIFT (3) |
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| 25 | #define MAX98363_CLOCK_MON_SHIFT (0) |
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| 26 | |
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| 27 | /* MAX98363_R2042_DSP_CFG */ |
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| 28 | #define MAX98363_AMP_DSP_CFG_RMP_SHIFT (3) |
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| 29 | |
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| 30 | struct max98363_priv { |
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| 31 | struct regmap *regmap; |
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| 32 | struct sdw_slave *slave; |
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| 33 | bool hw_init; |
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| 34 | bool first_hw_init; |
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| 35 | }; |
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| 36 | #endif |
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| 37 | |
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