| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * sma1303.h -- sma1303 ALSA SoC Audio driver |
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| 4 | * |
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| 5 | * Copyright 2023 Iron Device Corporation |
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| 6 | * |
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| 7 | * Author: Kiseok Jo <kiseok.jo@irondevice.com> |
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| 8 | * |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _SMA1303_H |
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| 12 | #define _SMA1303_H |
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| 13 | |
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| 14 | #define SMA1303_I2C_ADDR_00 0x1e |
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| 15 | #define SMA1303_I2C_ADDR_01 0x3e |
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| 16 | #define SMA1303_I2C_ADDR_10 0x5e |
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| 17 | #define SMA1303_I2C_ADDR_11 0x7e |
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| 18 | |
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| 19 | #define SMA1303_EXTERNAL_CLOCK_19_2 0x00 |
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| 20 | #define SMA1303_EXTERNAL_CLOCK_24_576 0x01 |
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| 21 | #define SMA1303_PLL_CLKIN_MCLK 0x02 |
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| 22 | #define SMA1303_PLL_CLKIN_BCLK 0x03 |
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| 23 | |
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| 24 | #define SMA1303_MONO 0x00 |
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| 25 | #define SMA1303_STEREO 0x01 |
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| 26 | |
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| 27 | #define SMA1303_I2C_RETRY_COUNT 3 |
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| 28 | |
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| 29 | /* |
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| 30 | * SMA1303 Register Definition |
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| 31 | */ |
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| 32 | |
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| 33 | /* SMA1303 Register Addresses */ |
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| 34 | #define SMA1303_00_SYSTEM_CTRL 0x00 |
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| 35 | #define SMA1303_01_INPUT1_CTRL1 0x01 |
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| 36 | #define SMA1303_02_INPUT1_CTRL2 0x02 |
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| 37 | #define SMA1303_03_INPUT1_CTRL3 0x03 |
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| 38 | #define SMA1303_04_INPUT1_CTRL4 0x04 |
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| 39 | /* 0x05 ~ 0x08 : Reserved */ |
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| 40 | #define SMA1303_09_OUTPUT_CTRL 0x09 |
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| 41 | #define SMA1303_0A_SPK_VOL 0x0a |
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| 42 | #define SMA1303_0B_BST_TEST 0x0b |
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| 43 | #define SMA1303_0C_BST_TEST1 0x0c |
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| 44 | #define SMA1303_0D_SPK_TEST 0x0d |
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| 45 | #define SMA1303_0E_MUTE_VOL_CTRL 0x0e |
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| 46 | /* 0x0F : Reserved */ |
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| 47 | #define SMA1303_10_SYSTEM_CTRL1 0x10 |
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| 48 | #define SMA1303_11_SYSTEM_CTRL2 0x11 |
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| 49 | #define SMA1303_12_SYSTEM_CTRL3 0x12 |
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| 50 | /* 0x13 : Reserved */ |
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| 51 | #define SMA1303_14_MODULATOR 0x14 |
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| 52 | #define SMA1303_15_BASS_SPK1 0x15 |
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| 53 | #define SMA1303_16_BASS_SPK2 0x16 |
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| 54 | #define SMA1303_17_BASS_SPK3 0x17 |
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| 55 | #define SMA1303_18_BASS_SPK4 0x18 |
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| 56 | #define SMA1303_19_BASS_SPK5 0x19 |
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| 57 | #define SMA1303_1A_BASS_SPK6 0x1a |
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| 58 | #define SMA1303_1B_BASS_SPK7 0x1b |
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| 59 | /* 0x1C ~ 0x22 : Reserved */ |
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| 60 | #define SMA1303_23_COMP_LIM1 0x23 |
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| 61 | #define SMA1303_24_COMP_LIM2 0x24 |
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| 62 | #define SMA1303_25_COMP_LIM3 0x25 |
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| 63 | #define SMA1303_26_COMP_LIM4 0x26 |
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| 64 | /* 0x27 ~ 0x32 : Reserved */ |
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| 65 | #define SMA1303_33_SDM_CTRL 0x33 |
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| 66 | #define SMA1303_34_OTP_DATA1 0x34 |
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| 67 | /* 0x35 : Reserved */ |
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| 68 | #define SMA1303_36_PROTECTION 0x36 |
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| 69 | #define SMA1303_37_SLOPE_CTRL 0x37 |
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| 70 | #define SMA1303_38_OTP_TRM0 0x38 |
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| 71 | /* 0x39 ~ 0x3A : Reserved */ |
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| 72 | #define SMA1303_3B_TEST1 0x3b |
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| 73 | #define SMA1303_3C_TEST2 0x3c |
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| 74 | #define SMA1303_3D_TEST3 0x3d |
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| 75 | #define SMA1303_3E_ATEST1 0x3e |
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| 76 | #define SMA1303_3F_ATEST2 0x3f |
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| 77 | /* 0x40 ~ 0x8A : Reserved */ |
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| 78 | #define SMA1303_8B_PLL_POST_N 0x8b |
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| 79 | #define SMA1303_8C_PLL_N 0x8c |
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| 80 | #define SMA1303_8D_PLL_A_SETTING 0x8d |
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| 81 | #define SMA1303_8E_PLL_CTRL 0x8e |
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| 82 | #define SMA1303_8F_PLL_P_CP 0x8f |
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| 83 | #define SMA1303_90_POSTSCALER 0x90 |
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| 84 | #define SMA1303_91_CLASS_G_CTRL 0x91 |
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| 85 | #define SMA1303_92_FDPEC_CTRL 0x92 |
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| 86 | /* 0x93 : Reserved */ |
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| 87 | #define SMA1303_94_BOOST_CTRL1 0x94 |
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| 88 | #define SMA1303_95_BOOST_CTRL2 0x95 |
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| 89 | #define SMA1303_96_BOOST_CTRL3 0x96 |
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| 90 | #define SMA1303_97_BOOST_CTRL4 0x97 |
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| 91 | /* 0x98 ~ 0x9F : Reserved */ |
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| 92 | #define SMA1303_A0_PAD_CTRL0 0xa0 |
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| 93 | #define SMA1303_A1_PAD_CTRL1 0xa1 |
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| 94 | #define SMA1303_A2_TOP_MAN1 0xa2 |
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| 95 | #define SMA1303_A3_TOP_MAN2 0xa3 |
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| 96 | #define SMA1303_A4_TOP_MAN3 0xa4 |
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| 97 | #define SMA1303_A5_TDM1 0xa5 |
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| 98 | #define SMA1303_A6_TDM2 0xa6 |
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| 99 | #define SMA1303_A7_CLK_MON 0xa7 |
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| 100 | /* 0xA8 ~ 0xF9 : Reserved */ |
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| 101 | #define SMA1303_FA_STATUS1 0xfa |
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| 102 | #define SMA1303_FB_STATUS2 0xfb |
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| 103 | /* 0xFC ~ 0xFE : Reserved */ |
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| 104 | #define SMA1303_FF_DEVICE_INDEX 0xff |
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| 105 | |
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| 106 | /* SMA1303 Registers Bit Fields */ |
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| 107 | |
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| 108 | /* SYSTEM_CTRL : 0x00 */ |
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| 109 | #define SMA1303_RESETBYI2C_MASK (1<<1) |
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| 110 | #define SMA1303_RESETBYI2C_NORMAL (0<<1) |
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| 111 | #define SMA1303_RESETBYI2C_RESET (1<<1) |
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| 112 | |
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| 113 | #define SMA1303_POWER_MASK (1<<0) |
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| 114 | #define SMA1303_POWER_OFF (0<<0) |
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| 115 | #define SMA1303_POWER_ON (1<<0) |
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| 116 | |
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| 117 | /* INTPUT CTRL1 : 0x01 */ |
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| 118 | #define SMA1303_CONTROLLER_DEVICE_MASK (1<<7) |
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| 119 | #define SMA1303_DEVICE_MODE (0<<7) |
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| 120 | #define SMA1303_CONTROLLER_MODE (1<<7) |
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| 121 | |
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| 122 | #define SMA1303_I2S_MODE_MASK (7<<4) |
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| 123 | #define SMA1303_STANDARD_I2S (0<<4) |
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| 124 | #define SMA1303_LJ (1<<4) |
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| 125 | #define SMA1303_RJ_16BIT (4<<4) |
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| 126 | #define SMA1303_RJ_18BIT (5<<4) |
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| 127 | #define SMA1303_RJ_20BIT (6<<4) |
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| 128 | #define SMA1303_RJ_24BIT (7<<4) |
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| 129 | |
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| 130 | #define SMA1303_LEFTPOL_MASK (1<<3) |
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| 131 | #define SMA1303_LOW_FIRST_CH (0<<3) |
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| 132 | #define SMA1303_HIGH_FIRST_CH (1<<3) |
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| 133 | |
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| 134 | #define SMA1303_SCK_RISING_MASK (1<<2) |
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| 135 | #define SMA1303_SCK_FALLING_EDGE (0<<2) |
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| 136 | #define SMA1303_SCK_RISING_EDGE (1<<2) |
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| 137 | |
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| 138 | /* INTPUT CTRL2 : 0x02 */ |
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| 139 | #define SMA1303_IMODE_MASK (3<<6) |
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| 140 | #define SMA1303_I2S (0<<6) |
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| 141 | #define SMA1303_PCM_SHORT (1<<6) |
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| 142 | #define SMA1303_PCM_LONG (2<<6) |
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| 143 | |
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| 144 | #define RSMA1303_IGHT_FIRST_MASK (1<<5) |
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| 145 | #define SMA1303_LEFT_NORMAL (0<<5) |
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| 146 | #define SMA1303_RIGHT_INVERTED (1<<5) |
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| 147 | |
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| 148 | #define SMA1303_PCM_ALAW_MASK (1<<4) |
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| 149 | #define SMA1303_PCM_U_DECODING (0<<4) |
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| 150 | #define SMA1303_PCM_A_DECODING (1<<4) |
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| 151 | |
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| 152 | #define SMA1303_PCM_COMP_MASK (1<<3) |
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| 153 | #define SMA1303_PCM_LINEAR (0<<3) |
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| 154 | #define SMA1303_PCM_COMPANDING (1<<3) |
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| 155 | |
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| 156 | #define SMA1303_INPUTSEL_MASK (1<<2) |
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| 157 | #define SMA1303_PCM_8KHZ (0<<2) |
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| 158 | #define SMA1303_PCM_16KHZ (1<<2) |
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| 159 | |
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| 160 | #define SMA1303_PCM_STEREO_MASK (1<<1) |
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| 161 | #define SMA1303_PCM_MONO (0<<1) |
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| 162 | #define SMA1303_PCM_STEREO (1<<1) |
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| 163 | |
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| 164 | #define SMA1303_PCM_DL_MASK (1<<0) |
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| 165 | #define SMA1303_PCM_8BIT (0<<0) |
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| 166 | #define SMA1303_PCM_16BIT (1<<0) |
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| 167 | |
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| 168 | /* INTPUT CTRL3 : 0x03 */ |
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| 169 | #define SMA1303_PCM_N_SLOT_MASK (15<<0) |
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| 170 | #define SMA1303_PCM_N_SLOT1 (0<<0) |
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| 171 | #define SMA1303_PCM_N_SLOT2 (1<<0) |
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| 172 | #define SMA1303_PCM_N_SLOT3 (2<<0) |
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| 173 | #define SMA1303_PCM_N_SLOT4 (3<<0) |
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| 174 | #define SMA1303_PCM_N_SLOT5 (4<<0) |
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| 175 | #define SMA1303_PCM_N_SLOT6 (5<<0) |
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| 176 | #define SMA1303_PCM_N_SLOT7 (6<<0) |
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| 177 | #define SMA1303_PCM_N_SLOT8 (7<<0) |
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| 178 | #define SMA1303_PCM_N_SLOT9 (8<<0) |
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| 179 | #define SMA1303_PCM_N_SLOT10 (9<<0) |
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| 180 | #define SMA1303_PCM_N_SLOT11 (10<<0) |
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| 181 | #define SMA1303_PCM_N_SLOT12 (11<<0) |
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| 182 | #define SMA1303_PCM_N_SLOT13 (12<<0) |
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| 183 | #define SMA1303_PCM_N_SLOT14 (13<<0) |
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| 184 | #define SMA1303_PCM_N_SLOT15 (14<<0) |
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| 185 | #define SMA1303_PCM_N_SLOT16 (15<<0) |
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| 186 | |
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| 187 | /* INTPUT CTRL4 : 0x04 */ |
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| 188 | #define SMA1303_PCM1_SLOT_MASK (15<<4) |
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| 189 | #define SMA1303_PCM1_SLOT1 (0<<4) |
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| 190 | #define SMA1303_PCM1_SLOT2 (1<<4) |
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| 191 | #define SMA1303_PCM1_SLOT3 (2<<4) |
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| 192 | #define SMA1303_PCM1_SLOT4 (3<<4) |
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| 193 | #define SMA1303_PCM1_SLOT5 (4<<4) |
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| 194 | #define SMA1303_PCM1_SLOT6 (5<<4) |
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| 195 | #define SMA1303_PCM1_SLOT7 (6<<4) |
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| 196 | #define SMA1303_PCM1_SLOT8 (7<<4) |
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| 197 | #define SMA1303_PCM1_SLOT9 (8<<4) |
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| 198 | #define SMA1303_PCM1_SLOT10 (9<<4) |
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| 199 | #define SMA1303_PCM1_SLOT11 (10<<4) |
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| 200 | #define SMA1303_PCM1_SLOT12 (11<<4) |
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| 201 | #define SMA1303_PCM1_SLOT13 (12<<4) |
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| 202 | #define SMA1303_PCM1_SLOT14 (13<<4) |
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| 203 | #define SMA1303_PCM1_SLOT15 (14<<4) |
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| 204 | #define SMA1303_PCM1_SLOT16 (15<<4) |
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| 205 | |
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| 206 | #define SMA1303_PCM2_SLOT_MASK (15<<0) |
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| 207 | #define SMA1303_PCM2_SLOT1 (0<<0) |
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| 208 | #define SMA1303_PCM2_SLOT2 (1<<0) |
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| 209 | #define SMA1303_PCM2_SLOT3 (2<<0) |
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| 210 | #define SMA1303_PCM2_SLOT4 (3<<0) |
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| 211 | #define SMA1303_PCM2_SLOT5 (4<<0) |
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| 212 | #define SMA1303_PCM2_SLOT6 (5<<0) |
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| 213 | #define SMA1303_PCM2_SLOT7 (6<<0) |
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| 214 | #define SMA1303_PCM2_SLOT8 (7<<0) |
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| 215 | #define SMA1303_PCM2_SLOT9 (8<<0) |
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| 216 | #define SMA1303_PCM2_SLOT10 (9<<0) |
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| 217 | #define SMA1303_PCM2_SLOT11 (10<<0) |
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| 218 | #define SMA1303_PCM2_SLOT12 (11<<0) |
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| 219 | #define SMA1303_PCM2_SLOT13 (12<<0) |
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| 220 | #define SMA1303_PCM2_SLOT14 (13<<0) |
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| 221 | #define SMA1303_PCM2_SLOT15 (14<<0) |
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| 222 | #define SMA1303_PCM2_SLOT16 (15<<0) |
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| 223 | |
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| 224 | /* OUTPUT CTRL : 0x09 */ |
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| 225 | #define SMA1303_PORT_CONFIG_MASK (3<<5) |
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| 226 | #define SMA1303_INPUT_PORT_ONLY (0<<5) |
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| 227 | #define SMA1303_OUTPUT_PORT_ENABLE (2<<5) |
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| 228 | |
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| 229 | #define SMA1303_PORT_OUT_SEL_MASK (7<<0) |
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| 230 | #define SMA1303_OUT_SEL_DISABLE (0<<0) |
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| 231 | #define SMA1303_FORMAT_CONVERTER (1<<0) |
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| 232 | #define SMA1303_MIXER_OUTPUT (2<<0) |
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| 233 | #define SMA1303_SPEAKER_PATH (3<<0) |
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| 234 | #define SMA1303_POSTSCALER_OUTPUT (4<<0) |
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| 235 | |
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| 236 | /* BST_TEST : 0x0B */ |
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| 237 | #define SMA1303_BST_OFF_SLOPE_MASK (3<<6) |
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| 238 | #define SMA1303_BST_OFF_SLOPE_6_7ns (0<<6) |
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| 239 | #define SMA1303_BST_OFF_SLOPE_4_8ns (1<<6) |
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| 240 | #define SMA1303_BST_OFF_SLOPE_2_6ns (2<<6) |
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| 241 | #define SMA1303_BST_OFF_SLOPE_1_2ns (3<<6) |
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| 242 | |
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| 243 | #define SMA1303_OCP_TEST_MASK (1<<5) |
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| 244 | #define SMA1303_OCP_NORMAL_MODE (0<<5) |
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| 245 | #define SMA1303_OCP_TEST_MODE (1<<5) |
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| 246 | |
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| 247 | #define SMA1303_BST_FAST_LEBN_MASK (1<<4) |
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| 248 | #define SMA1303_BST_SHORT_LEB (0<<4) |
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| 249 | #define SMA1303_BST_LONG_LEB (1<<4) |
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| 250 | |
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| 251 | #define SMA1303_HIGH_PGAIN_MASK (1<<3) |
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| 252 | #define SMA1303_NORMAL_P_GAIN (0<<3) |
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| 253 | #define SMA1303_HIGH_P_GAIN (1<<3) |
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| 254 | |
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| 255 | #define SMA1303_VCOMP_MASK (1<<2) |
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| 256 | #define SMA1303_VCOMP_NORMAL_MODE (0<<2) |
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| 257 | #define SMA1303_VCOMP_V_MON_MODE (1<<2) |
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| 258 | |
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| 259 | #define SMA1303_PMOS_ON_MASK (1<<1) |
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| 260 | #define SMA1303_PMOS_NORMAL_MODE (0<<1) |
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| 261 | #define SMA1303_PMOS_TEST_MODE (1<<1) |
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| 262 | |
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| 263 | #define SMA1303_NMOS_ON_MASK (1<<0) |
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| 264 | #define SMA1303_NMOS_NORMAL_MODE (0<<0) |
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| 265 | #define SMA1303_NMOS_TEST_MODE (1<<0) |
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| 266 | |
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| 267 | /* BST_TEST1 : 0x0C */ |
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| 268 | #define SMA1303_SET_OCP_H_MASK (3<<6) |
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| 269 | #define SMA1303_HIGH_OCP_4_5_LVL (0<<6) |
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| 270 | #define SMA1303_HIGH_OCP_3_2_LVL (1<<6) |
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| 271 | #define SMA1303_HIGH_OCP_2_1_LVL (2<<6) |
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| 272 | #define SMA1303_HIGH_OCP_0_9_LVL (3<<6) |
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| 273 | |
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| 274 | #define SMA1303_OCL_TEST_MASK (1<<5) |
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| 275 | #define SMA1303_OCL_NORMAL_MODE (0<<5) |
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| 276 | #define SMA1303_OCL_TEST_MODE (1<<5) |
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| 277 | |
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| 278 | #define SMA1303_LOOP_CHECK_MASK (1<<4) |
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| 279 | #define SMA1303_BST_LOOP_NORMAL_MODE (0<<4) |
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| 280 | #define SMA1303_BST_LOOP_CHECK_MODE (1<<4) |
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| 281 | |
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| 282 | #define SMA1303_EN_SH_PRT_MASK (1<<3) |
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| 283 | #define SMA1303_EN_SH_PRT_DISABLE (0<<3) |
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| 284 | #define SMA1303_EN_SH_PRT_ENABLE (1<<3) |
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| 285 | |
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| 286 | /* SPK_TEST : 0x0D */ |
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| 287 | #define SMA1303_VREF_MON_MASK (1<<3) |
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| 288 | #define SMA1303_VREF_NORMAL_MODE (0<<3) |
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| 289 | #define SMA1303_VREF_V_MON_MODE (1<<3) |
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| 290 | |
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| 291 | #define SMA1303_SPK_OCP_DLYN_MASK (1<<2) |
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| 292 | #define SMA1303_SPK_OCP_LONG_DELAY (0<<2) |
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| 293 | #define SMA1303_SPK_OCP_NORMAL (1<<2) |
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| 294 | |
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| 295 | #define SMA1303_SPK_OFF_SLOPE_MASK (3<<0) |
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| 296 | #define SMA1303_SPK_OFF_SLOPE_SLOW (0<<0) |
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| 297 | #define SMA1303_SPK_OFF_SLOPE_FAST (3<<0) |
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| 298 | |
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| 299 | /* MUTE_VOL_CTRL : 0x0E */ |
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| 300 | #define SMA1303_VOL_SLOPE_MASK (3<<6) |
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| 301 | #define SMA1303_VOL_SLOPE_OFF (0<<6) |
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| 302 | #define SMA1303_VOL_SLOPE_SLOW (1<<6) |
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| 303 | #define SMA1303_VOL_SLOPE_MID (2<<6) |
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| 304 | #define SMA1303_VOL_SLOPE_FAST (3<<6) |
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| 305 | |
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| 306 | #define SMA1303_MUTE_SLOPE_MASK (3<<4) |
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| 307 | #define SMA1303_MUTE_SLOPE_OFF (0<<4) |
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| 308 | #define SMA1303_MUTE_SLOPE_SLOW (1<<4) |
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| 309 | #define SMA1303_MUTE_SLOPE_MID (2<<4) |
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| 310 | #define SMA1303_MUTE_SLOPE_FAST (3<<4) |
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| 311 | |
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| 312 | #define SMA1303_SPK_MUTE_MASK (1<<0) |
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| 313 | #define SMA1303_SPK_UNMUTE (0<<0) |
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| 314 | #define SMA1303_SPK_MUTE (1<<0) |
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| 315 | |
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| 316 | /* SYSTEM_CTRL1 :0x10 */ |
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| 317 | #define SMA1303_SPK_MODE_MASK (7<<2) |
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| 318 | #define SMA1303_SPK_OFF (0<<2) |
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| 319 | #define SMA1303_SPK_MONO (1<<2) |
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| 320 | #define SMA1303_SPK_STEREO (4<<2) |
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| 321 | |
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| 322 | /* SYSTEM_CTRL2 : 0x11 */ |
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| 323 | #define SMA1303_SPK_BS_MASK (1<<6) |
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| 324 | #define SMA1303_SPK_BS_BYP (0<<6) |
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| 325 | #define SMA1303_SPK_BS_EN (1<<6) |
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| 326 | #define SMA1303_SPK_LIM_MASK (1<<5) |
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| 327 | #define SMA1303_SPK_LIM_BYP (0<<5) |
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| 328 | #define SMA1303_SPK_LIM_EN (1<<5) |
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| 329 | |
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| 330 | #define SMA1303_LR_DATA_SW_MASK (1<<4) |
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| 331 | #define SMA1303_LR_DATA_SW_NORMAL (0<<4) |
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| 332 | #define SMA1303_LR_DATA_SW_SWAP (1<<4) |
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| 333 | |
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| 334 | #define SMA1303_MONOMIX_MASK (1<<0) |
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| 335 | #define SMA1303_MONOMIX_OFF (0<<0) |
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| 336 | #define SMA1303_MONOMIX_ON (1<<0) |
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| 337 | |
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| 338 | /* SYSTEM_CTRL3 : 0x12 */ |
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| 339 | #define SMA1303_INPUT_MASK (3<<6) |
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| 340 | #define SMA1303_INPUT_0_DB (0<<6) |
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| 341 | #define SMA1303_INPUT_M6_DB (1<<6) |
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| 342 | #define SMA1303_INPUT_M12_DB (2<<6) |
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| 343 | #define SMA1303_INPUT_INFI_DB (3<<6) |
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| 344 | #define SMA1303_INPUT_R_MASK (3<<4) |
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| 345 | #define SMA1303_INPUT_R_0_DB (0<<4) |
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| 346 | #define SMA1303_INPUT_R_M6_DB (1<<4) |
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| 347 | #define SMA1303_INPUT_R_M12_DB (2<<4) |
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| 348 | #define SMA1303_INPUT_R_INFI_DB (3<<4) |
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| 349 | |
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| 350 | /* Modulator : 0x14 */ |
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| 351 | #define SMA1303_SPK_HYSFB_MASK (3<<6) |
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| 352 | #define SMA1303_HYSFB_625K (0<<6) |
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| 353 | #define SMA1303_HYSFB_414K (1<<6) |
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| 354 | #define SMA1303_HYSFB_297K (2<<6) |
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| 355 | #define SMA1303_HYSFB_226K (3<<6) |
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| 356 | #define SMA1303_SPK_BDELAY_MASK (63<<0) |
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| 357 | |
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| 358 | /* SDM CONTROL : 0x33 */ |
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| 359 | #define SMA1303_SDM_Q_SEL_MASK (1<<2) |
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| 360 | #define SMA1303_QUART_SEL_1_DIV_4 (0<<2) |
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| 361 | #define SMA1303_QUART_SEL_1_DIV_8 (1<<2) |
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| 362 | |
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| 363 | /* OTP_DATA1 : 0x34 */ |
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| 364 | #define SMA1303_OTP_LVL_MASK (1<<5) |
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| 365 | #define SMA1303_OTP_LVL_NORMAL (0<<5) |
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| 366 | #define SMA1303_OTP_LVL_LOW (1<<5) |
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| 367 | |
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| 368 | /* PROTECTION : 0x36 */ |
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| 369 | #define SMA1303_EDGE_DIS_MASK (1<<7) |
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| 370 | #define SMA1303_EDGE_DIS_ENABLE (0<<7) |
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| 371 | #define SMA1303_EDGE_DIS_DISABLE (1<<7) |
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| 372 | |
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| 373 | #define SMA1303_SPK_OCP_DIS_MASK (1<<3) |
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| 374 | #define SMA1303_SPK_OCP_ENABLE (0<<3) |
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| 375 | #define SMA1303_SPK_OCP_DISABLE (1<<3) |
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| 376 | |
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| 377 | #define SMA1303_OCP_MODE_MASK (1<<2) |
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| 378 | #define SMA1303_AUTO_RECOVER (0<<2) |
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| 379 | #define SMA1303_SHUT_DOWN_PERMANENT (1<<2) |
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| 380 | |
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| 381 | #define SMA1303_OTP_MODE_MASK (3<<0) |
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| 382 | #define SMA1303_OTP_MODE_DISABLE (0<<0) |
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| 383 | #define SMA1303_IG_THR1_SHUT_THR2 (1<<0) |
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| 384 | #define SMA1303_REC_THR1_SHUT_THR2 (2<<0) |
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| 385 | #define SMA1303_SHUT_THR1_SHUT_THR2 (3<<0) |
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| 386 | |
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| 387 | /* TEST2 : 0x3C */ |
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| 388 | #define SMA1303_SPK_HSDM_BP_MASK (1<<4) |
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| 389 | #define SMA1303_SPK_HSDM_ENABLE (0<<4) |
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| 390 | #define SMA1303_SPK_HSDM_BYPASS (1<<4) |
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| 391 | |
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| 392 | #define SMA1303_SDM_SYNC_DIS_MASK (1<<5) |
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| 393 | #define SMA1303_SDM_SYNC_NORMAL (0<<5) |
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| 394 | #define SMA1303_SDM_SYNC_DISABLE (1<<5) |
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| 395 | |
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| 396 | /* ATEST2 : 0x3F */ |
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| 397 | #define SMA1303_SPK_OUT_FREQ_MASK (1<<2) |
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| 398 | #define SMA1303_SPK_OUT_FREQ_360K (0<<2) |
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| 399 | #define SMA1303_SPK_OUT_FREQ_410K (1<<2) |
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| 400 | |
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| 401 | #define SMA1303_LOW_POWER_MODE_MASK (1<<3) |
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| 402 | #define SMA1303_LOW_POWER_MODE_DISABLE (0<<3) |
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| 403 | #define SMA1303_LOW_POWER_MODE_ENABLE (1<<3) |
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| 404 | |
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| 405 | #define SMA1303_THERMAL_ADJUST_MASK (3<<5) |
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| 406 | #define SMA1303_THERMAL_150_110 (0<<5) |
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| 407 | #define SMA1303_THERMAL_160_120 (1<<5) |
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| 408 | #define SMA1303_THERMAL_140_100 (2<<5) |
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| 409 | |
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| 410 | #define SMA1303_FAST_OFF_DRIVE_SPK_MASK (1<<0) |
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| 411 | #define SMA1303_FAST_OFF_DRIVE_SPK_DISABLE (0<<0) |
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| 412 | #define SMA1303_FAST_OFF_DRIVE_SPK_ENABLE (1<<0) |
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| 413 | |
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| 414 | /* PLL_CTRL : 0x8E */ |
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| 415 | #define SMA1303_TRM_LVL_MASK (1<<4) |
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| 416 | #define SMA1303_TRM_LVL_NORMAL (0<<4) |
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| 417 | #define SMA1303_TRM_LVL_LOW (1<<4) |
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| 418 | |
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| 419 | #define SMA1303_LOW_OCL_MODE_MASK (1<<3) |
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| 420 | #define SMA1303_LOW_OCL_MODE (0<<3) |
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| 421 | #define SMA1303_NORMAL_OCL_MODE (1<<3) |
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| 422 | |
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| 423 | #define SMA1303_PLL_PD2_MASK (7<<0) |
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| 424 | #define SMA1303_PLL_PD2 (7<<0) |
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| 425 | #define SMA1303_PLL_OPERATION2 (0<<0) |
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| 426 | |
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| 427 | /* POSTSCALER : 0x90 */ |
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| 428 | #define SMA1303_BYP_POST_MASK (1<<0) |
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| 429 | #define SMA1303_EN_POST_SCALER (0<<0) |
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| 430 | #define SMA1303_BYP_POST_SCALER (1<<0) |
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| 431 | |
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| 432 | /* FDPEC CONTROL : 0x92 */ |
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| 433 | #define SMA1303_FLT_VDD_GAIN_MASK (15<<4) |
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| 434 | #define SMA1303_FLT_VDD_GAIN_2P40 (0<<4) |
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| 435 | #define SMA1303_FLT_VDD_GAIN_2P45 (1<<4) |
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| 436 | #define SMA1303_FLT_VDD_GAIN_2P50 (2<<4) |
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| 437 | #define SMA1303_FLT_VDD_GAIN_2P55 (3<<4) |
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| 438 | #define SMA1303_FLT_VDD_GAIN_2P60 (4<<4) |
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| 439 | #define SMA1303_FLT_VDD_GAIN_2P65 (5<<4) |
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| 440 | #define SMA1303_FLT_VDD_GAIN_2P70 (6<<4) |
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| 441 | #define SMA1303_FLT_VDD_GAIN_2P75 (7<<4) |
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| 442 | #define SMA1303_FLT_VDD_GAIN_2P80 (8<<4) |
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| 443 | #define SMA1303_FLT_VDD_GAIN_2P85 (9<<4) |
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| 444 | #define SMA1303_FLT_VDD_GAIN_2P90 (10<<4) |
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| 445 | #define SMA1303_FLT_VDD_GAIN_2P95 (11<<4) |
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| 446 | #define SMA1303_FLT_VDD_GAIN_3P00 (12<<4) |
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| 447 | #define SMA1303_FLT_VDD_GAIN_3P05 (13<<4) |
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| 448 | #define SMA1303_FLT_VDD_GAIN_3P10 (14<<4) |
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| 449 | #define SMA1303_FLT_VDD_GAIN_3P15 (15<<4) |
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| 450 | |
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| 451 | #define SMA1303_DIS_FCHG_MASK (1<<2) |
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| 452 | #define SMA1303_EN_FAST_CHARGE (0<<2) |
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| 453 | #define SMA1303_DIS_FAST_CHARGE (1<<2) |
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| 454 | |
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| 455 | /* BOOST_CONTROL4 : 0x97 */ |
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| 456 | #define SMA1303_TRM_VBST_MASK (7<<2) |
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| 457 | #define SMA1303_TRM_VBST_5P5 (0<<2) |
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| 458 | #define SMA1303_TRM_VBST_5P6 (1<<2) |
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| 459 | #define SMA1303_TRM_VBST_5P7 (2<<2) |
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| 460 | #define SMA1303_TRM_VBST_5P8 (3<<2) |
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| 461 | #define SMA1303_TRM_VBST_5P9 (4<<2) |
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| 462 | #define SMA1303_TRM_VBST_6P0 (5<<2) |
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| 463 | #define SMA1303_TRM_VBST_6P1 (6<<2) |
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| 464 | #define SMA1303_TRM_VBST_6P2 (7<<2) |
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| 465 | |
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| 466 | /* TOP_MAN1 : 0xA2 */ |
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| 467 | #define SMA1303_PLL_LOCK_SKIP_MASK (1<<7) |
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| 468 | #define SMA1303_PLL_LOCK_ENABLE (0<<7) |
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| 469 | #define SMA1303_PLL_LOCK_DISABLE (1<<7) |
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| 470 | |
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| 471 | #define SMA1303_PLL_PD_MASK (1<<6) |
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| 472 | #define SMA1303_PLL_OPERATION (0<<6) |
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| 473 | #define SMA1303_PLL_PD (1<<6) |
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| 474 | |
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| 475 | #define SMA1303_PLL_DIV_MASK (3<<4) |
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| 476 | #define SMA1303_PLL_OUT (0<<4) |
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| 477 | #define SMA1303_PLL_OUT_2 (1<<4) |
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| 478 | #define SMA1303_PLL_OUT_4 (2<<4) |
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| 479 | #define SMA1303_PLL_OUT_8 (3<<4) |
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| 480 | |
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| 481 | #define SMA1303_PLL_REF_CLK_MASK (1<<3) |
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| 482 | #define SMA1303_PLL_REF_CLK1 (0<<3) |
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| 483 | #define SMA1303_PLL_SCK (1<<3) |
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| 484 | |
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| 485 | #define SMA1303_DAC_DN_CONV_MASK (1<<2) |
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| 486 | #define SMA1303_DAC_DN_CONV_DISABLE (0<<2) |
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| 487 | #define SMA1303_DAC_DN_CONV_ENABLE (1<<2) |
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| 488 | |
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| 489 | #define SMA1303_SDO_IO_MASK (1<<1) |
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| 490 | #define SMA1303_HIGH_Z_LRCK_H (0<<1) |
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| 491 | #define SMA1303_HIGH_Z_LRCK_L (1<<1) |
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| 492 | |
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| 493 | #define SMA1303_SDO_OUTPUT2_MASK (1<<0) |
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| 494 | #define SMA1303_SDO_NORMAL (0<<0) |
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| 495 | #define SMA1303_SDO_OUTPUT_ONLY (1<<0) |
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| 496 | |
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| 497 | /* TOP_MAN2 : 0xA3 */ |
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| 498 | #define SMA1303_MON_OSC_PLL_MASK (1<<7) |
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| 499 | #define SMA1303_PLL_SDO (0<<7) |
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| 500 | #define SMA1303_OSC_SDO (1<<7) |
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| 501 | |
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| 502 | #define SMA1303_TEST_CLKO_EN_MASK (1<<6) |
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| 503 | #define SMA1303_NORMAL_SDO (0<<6) |
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| 504 | #define SMA1303_CLK_OUT_SDO (1<<6) |
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| 505 | |
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| 506 | #define SMA1303_SDO_OUTPUT_MASK (1<<3) |
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| 507 | #define SMA1303_NORMAL_OUT (0<<3) |
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| 508 | #define SMA1303_HIGH_Z_OUT (1<<3) |
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| 509 | |
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| 510 | #define SMA1303_CLOCK_MON_MASK (1<<1) |
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| 511 | #define SMA1303_CLOCK_MON (0<<1) |
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| 512 | #define SMA1303_CLOCK_NOT_MON (1<<1) |
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| 513 | |
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| 514 | #define SMA1303_OSC_PD_MASK (1<<0) |
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| 515 | #define SMA1303_NORMAL_OPERATION_OSC (0<<0) |
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| 516 | #define SMA1303_POWER_DOWN_OSC (1<<0) |
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| 517 | |
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| 518 | /* TOP_MAN3 0xA4 */ |
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| 519 | #define SMA1303_O_FORMAT_MASK (7<<5) |
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| 520 | #define SMA1303_O_FMT_LJ (1<<5) |
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| 521 | #define SMA1303_O_FMT_I2S (2<<5) |
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| 522 | #define SMA1303_O_FMT_TDM (4<<5) |
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| 523 | |
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| 524 | #define SMA1303_SCK_RATE_MASK (1<<3) |
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| 525 | #define SMA1303_SCK_64FS (0<<3) |
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| 526 | #define SMA1303_SCK_32FS (2<<3) |
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| 527 | |
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| 528 | #define SMA1303_LRCK_POL_MASK (1<<0) |
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| 529 | #define SMA1303_L_VALID (0<<0) |
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| 530 | #define SMA1303_R_VALID (1<<0) |
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| 531 | |
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| 532 | /* TDM1 FORMAT : 0xA5 */ |
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| 533 | #define SMA1303_TDM_CLK_POL_MASK (1<<7) |
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| 534 | #define SMA1303_TDM_CLK_POL_RISE (0<<7) |
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| 535 | #define SMA1303_TDM_CLK_POL_FALL (1<<7) |
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| 536 | |
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| 537 | #define SMA1303_TDM_TX_MODE_MASK (1<<6) |
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| 538 | #define SMA1303_TDM_TX_MONO (0<<6) |
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| 539 | #define SMA1303_TDM_TX_STEREO (1<<6) |
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| 540 | |
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| 541 | #define SMA1303_TDM_SLOT1_RX_POS_MASK (7<<3) |
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| 542 | #define SMA1303_TDM_SLOT1_RX_POS_0 (0<<3) |
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| 543 | #define SMA1303_TDM_SLOT1_RX_POS_1 (1<<3) |
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| 544 | #define SMA1303_TDM_SLOT1_RX_POS_2 (2<<3) |
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| 545 | #define SMA1303_TDM_SLOT1_RX_POS_3 (3<<3) |
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| 546 | #define SMA1303_TDM_SLOT1_RX_POS_4 (4<<3) |
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| 547 | #define SMA1303_TDM_SLOT1_RX_POS_5 (5<<3) |
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| 548 | #define SMA1303_TDM_SLOT1_RX_POS_6 (6<<3) |
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| 549 | #define SMA1303_TDM_SLOT1_RX_POS_7 (7<<3) |
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| 550 | |
|---|
| 551 | #define SMA1303_TDM_SLOT2_RX_POS_MASK (7<<0) |
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| 552 | #define SMA1303_TDM_SLOT2_RX_POS_0 (0<<0) |
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| 553 | #define SMA1303_TDM_SLOT2_RX_POS_1 (1<<0) |
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| 554 | #define SMA1303_TDM_SLOT2_RX_POS_2 (2<<0) |
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| 555 | #define SMA1303_TDM_SLOT2_RX_POS_3 (3<<0) |
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| 556 | #define SMA1303_TDM_SLOT2_RX_POS_4 (4<<0) |
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| 557 | #define SMA1303_TDM_SLOT2_RX_POS_5 (5<<0) |
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| 558 | #define SMA1303_TDM_SLOT2_RX_POS_6 (6<<0) |
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| 559 | #define SMA1303_TDM_SLOT2_RX_POS_7 (7<<0) |
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| 560 | |
|---|
| 561 | /* TDM2 FORMAT : 0xA6 */ |
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| 562 | #define SMA1303_TDM_DL_MASK (1<<7) |
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| 563 | #define SMA1303_TDM_DL_16 (0<<7) |
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| 564 | #define SMA1303_TDM_DL_32 (1<<7) |
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| 565 | |
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| 566 | #define SMA1303_TDM_N_SLOT_MASK (1<<6) |
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| 567 | #define SMA1303_TDM_N_SLOT_4 (0<<6) |
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| 568 | #define SMA1303_TDM_N_SLOT_8 (1<<6) |
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| 569 | |
|---|
| 570 | #define SMA1303_TDM_SLOT1_TX_POS_MASK (7<<3) |
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| 571 | #define SMA1303_TDM_SLOT1_TX_POS_0 (0<<3) |
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| 572 | #define SMA1303_TDM_SLOT1_TX_POS_1 (1<<3) |
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| 573 | #define SMA1303_TDM_SLOT1_TX_POS_2 (2<<3) |
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| 574 | #define SMA1303_TDM_SLOT1_TX_POS_3 (3<<3) |
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| 575 | #define SMA1303_TDM_SLOT1_TX_POS_4 (4<<3) |
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| 576 | #define SMA1303_TDM_SLOT1_TX_POS_5 (5<<3) |
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| 577 | #define SMA1303_TDM_SLOT1_TX_POS_6 (6<<3) |
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| 578 | #define SMA1303_TDM_SLOT1_TX_POS_7 (7<<3) |
|---|
| 579 | |
|---|
| 580 | #define SMA1303_TDM_SLOT2_TX_POS_MASK (7<<0) |
|---|
| 581 | #define SMA1303_TDM_SLOT2_TX_POS_0 (0<<0) |
|---|
| 582 | #define SMA1303_TDM_SLOT2_TX_POS_1 (1<<0) |
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| 583 | #define SMA1303_TDM_SLOT2_TX_POS_2 (2<<0) |
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| 584 | #define SMA1303_TDM_SLOT2_TX_POS_3 (3<<0) |
|---|
| 585 | #define SMA1303_TDM_SLOT2_TX_POS_4 (4<<0) |
|---|
| 586 | #define SMA1303_TDM_SLOT2_TX_POS_5 (5<<0) |
|---|
| 587 | #define SMA1303_TDM_SLOT2_TX_POS_6 (6<<0) |
|---|
| 588 | #define SMA1303_TDM_SLOT2_TX_POS_7 (7<<0) |
|---|
| 589 | |
|---|
| 590 | /* STATUS1 : 0xFA */ |
|---|
| 591 | #define SMA1303_OT1_OK_STATUS (1<<7) |
|---|
| 592 | #define SMA1303_OT2_OK_STATUS (1<<6) |
|---|
| 593 | |
|---|
| 594 | /* STATUS2 : 0xFB */ |
|---|
| 595 | #define SMA1303_OCP_SPK_STATUS (1<<5) |
|---|
| 596 | #define SMA1303_OCP_BST_STATUS (1<<4) |
|---|
| 597 | #define SMA1303_OTP_STAT_OK_0 (5<<1) |
|---|
| 598 | #define SMA1303_OTP_STAT_OK_1 (2<<2) |
|---|
| 599 | |
|---|
| 600 | #define SMA1303_CLK_MON_STATUS (1<<0) |
|---|
| 601 | |
|---|
| 602 | /* DEVICE_INFO : 0xFF */ |
|---|
| 603 | #define SMA1303_DEVICE_ID (2<<3) |
|---|
| 604 | #define SMA1303_UVLO_BST_STATUS (1<<2) |
|---|
| 605 | #define SMA1303_REV_NUM_STATUS (3<<0) |
|---|
| 606 | #define SMA1303_REV_NUM_TV0 (0<<0) |
|---|
| 607 | #define SMA1303_REV_NUM_TV1 (1<<0) |
|---|
| 608 | |
|---|
| 609 | #endif |
|---|
| 610 | |
|---|
