| 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | // |
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| 3 | // src4xxx.h -- SRC4XXX ALSA SoC audio driver |
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| 4 | // |
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| 5 | // Copyright 2021-2022 Deqx Pty Ltd |
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| 6 | // Author: Matt R Flax <flatmax@flatmax.com> |
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| 7 | |
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| 8 | #ifndef __SRC4XXX_H__ |
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| 9 | #define __SRC4XXX_H__ |
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| 10 | |
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| 11 | #define SRC4XXX_RES_00 0x00 |
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| 12 | #define SRC4XXX_PWR_RST_01 0x01 |
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| 13 | #define SRC4XXX_RESET 0x80 |
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| 14 | #define SRC4XXX_POWER_DOWN 0x00 |
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| 15 | #define SRC4XXX_POWER_ENABLE 0x20 |
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| 16 | #define SRC4XXX_ENABLE_SRC 0x1 |
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| 17 | #define SRC4XXX_ENABLE_SRC_SHIFT 0 |
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| 18 | #define SRC4XXX_ENABLE_DIR 0x2 |
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| 19 | #define SRC4XXX_ENABLE_DIR_SHIFT 1 |
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| 20 | #define SRC4XXX_ENABLE_DIT 0x4 |
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| 21 | #define SRC4XXX_ENABLE_DIT_SHIFT 2 |
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| 22 | #define SRC4XXX_ENABLE_PORT_B 0x8 |
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| 23 | #define SRC4XXX_ENABLE_PORT_B_SHIFT 3 |
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| 24 | #define SRC4XXX_ENABLE_PORT_A 0x10 |
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| 25 | #define SRC4XXX_ENABLE_PORT_A_SHIFT 4 |
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| 26 | |
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| 27 | #define SRC4XXX_PORTA_CTL_03 0x03 |
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| 28 | #define SRC4XXX_BUS_MASTER 0x8 |
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| 29 | #define SRC4XXX_BUS_LEFT_J 0x0 |
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| 30 | #define SRC4XXX_BUS_I2S 0x1 |
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| 31 | #define SRC4XXX_BUS_RIGHT_J_16 0x4 |
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| 32 | #define SRC4XXX_BUS_RIGHT_J_18 0x5 |
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| 33 | #define SRC4XXX_BUS_RIGHT_J_20 0x6 |
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| 34 | #define SRC4XXX_BUS_RIGHT_J_24 0x7 |
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| 35 | #define SRC4XXX_BUS_FMT_MS_MASK 0xf |
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| 36 | |
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| 37 | #define SRC4XXX_PORTA_CTL_04 0x04 |
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| 38 | #define SRC4XXX_MCLK_DIV_MASK 0x3 |
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| 39 | |
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| 40 | #define SRC4XXX_BUS_FMT(id) (SRC4XXX_PORTA_CTL_03+2*id) |
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| 41 | #define SRC4XXX_BUS_CLK(id) (SRC4XXX_PORTA_CTL_04+2*id) |
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| 42 | |
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| 43 | #define SRC4XXX_PORTB_CTL_05 0x05 |
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| 44 | #define SRC4XXX_PORTB_CTL_06 0x06 |
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| 45 | |
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| 46 | #define SRC4XXX_TX_CTL_07 0x07 |
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| 47 | #define SRC4XXX_TX_MCLK_DIV_MASK 0x60 |
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| 48 | #define SRC4XXX_TX_MCLK_DIV_SHIFT 5 |
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| 49 | |
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| 50 | #define SRC4XXX_TX_CTL_08 0x08 |
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| 51 | #define SRC4XXX_TX_CTL_09 0x09 |
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| 52 | #define SRC4XXX_SRC_DIT_IRQ_MSK_0B 0x0B |
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| 53 | #define SRC4XXX_SRC_BTI_EN 0x01 |
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| 54 | #define SRC4XXX_SRC_TSLIP_EN 0x02 |
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| 55 | #define SRC4XXX_SRC_DIT_IRQ_MODE_0C 0x0C |
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| 56 | #define SRC4XXX_RCV_CTL_0D 0x0D |
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| 57 | #define SRC4XXX_RXCLK_RXCKI 0x0 |
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| 58 | #define SRC4XXX_RXCLK_MCLK 0x8 |
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| 59 | #define SRC4XXX_RCV_CTL_0E 0x0E |
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| 60 | #define SRC4XXX_REC_MCLK_EN 0x1 |
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| 61 | #define SRC4XXX_PLL2_DIV_0 (0x0<<1) |
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| 62 | #define SRC4XXX_PLL2_DIV_2 (0x1<<1) |
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| 63 | #define SRC4XXX_PLL2_DIV_4 (0x2<<1) |
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| 64 | #define SRC4XXX_PLL2_DIV_8 (0x3<<1) |
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| 65 | #define SRC4XXX_PLL2_LOL 0x8 |
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| 66 | #define SRC4XXX_RCV_PLL_0F 0x0F |
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| 67 | #define SRC4XXX_RCV_PLL_10 0x10 |
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| 68 | #define SRC4XXX_RCV_PLL_11 0x11 |
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| 69 | #define SRC4XXX_RVC_IRQ_MSK_16 0x16 |
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| 70 | #define SRC4XXX_RVC_IRQ_MSK_17 0x17 |
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| 71 | #define SRC4XXX_RVC_IRQ_MODE_18 0x18 |
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| 72 | #define SRC4XXX_RVC_IRQ_MODE_19 0x19 |
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| 73 | #define SRC4XXX_RVC_IRQ_MODE_1A 0x1A |
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| 74 | #define SRC4XXX_GPIO_1_1B 0x1B |
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| 75 | #define SRC4XXX_GPIO_2_1C 0x1C |
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| 76 | #define SRC4XXX_GPIO_3_1D 0x1D |
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| 77 | #define SRC4XXX_GPIO_4_1E 0x1E |
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| 78 | #define SRC4XXX_SCR_CTL_2D 0x2D |
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| 79 | #define SRC4XXX_SCR_CTL_2E 0x2E |
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| 80 | #define SRC4XXX_SCR_CTL_2F 0x2F |
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| 81 | #define SRC4XXX_SCR_CTL_30 0x30 |
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| 82 | #define SRC4XXX_SCR_CTL_31 0x31 |
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| 83 | #define SRC4XXX_PAGE_SEL_7F 0x7F |
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| 84 | |
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| 85 | // read only registers |
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| 86 | #define SRC4XXX_GLOBAL_ITR_STS_02 0x02 |
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| 87 | #define SRC4XXX_SRC_DIT_STS_0A 0x0A |
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| 88 | #define SRC4XXX_NON_AUDIO_D_12 0x12 |
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| 89 | #define SRC4XXX_RVC_STS_13 0x13 |
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| 90 | #define SRC4XXX_RVC_STS_14 0x14 |
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| 91 | #define SRC4XXX_RVC_STS_15 0x15 |
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| 92 | #define SRC4XXX_SUB_CODE_1F 0x1F |
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| 93 | #define SRC4XXX_SUB_CODE_20 0x20 |
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| 94 | #define SRC4XXX_SUB_CODE_21 0x21 |
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| 95 | #define SRC4XXX_SUB_CODE_22 0x22 |
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| 96 | #define SRC4XXX_SUB_CODE_23 0x23 |
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| 97 | #define SRC4XXX_SUB_CODE_24 0x24 |
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| 98 | #define SRC4XXX_SUB_CODE_25 0x25 |
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| 99 | #define SRC4XXX_SUB_CODE_26 0x26 |
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| 100 | #define SRC4XXX_SUB_CODE_27 0x27 |
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| 101 | #define SRC4XXX_SUB_CODE_28 0x28 |
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| 102 | #define SRC4XXX_PC_PREAMBLE_HI_29 0x29 |
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| 103 | #define SRC4XXX_PC_PREAMBLE_LO_2A 0x2A |
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| 104 | #define SRC4XXX_PD_PREAMBLE_HI_2B 0x2B |
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| 105 | #define SRC4XXX_PC_PREAMBLE_LO_2C 0x2C |
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| 106 | #define SRC4XXX_IO_RATIO_32 0x32 |
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| 107 | #define SRC4XXX_IO_RATIO_33 0x33 |
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| 108 | |
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| 109 | int src4xxx_probe(struct device *dev, struct regmap *regmap, |
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| 110 | void (*switch_mode)(struct device *dev)); |
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| 111 | extern const struct regmap_config src4xxx_regmap_config; |
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| 112 | |
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| 113 | #endif /* __SRC4XXX_H__ */ |
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| 114 | |
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