| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * tas2562.h - ALSA SoC Texas Instruments TAS2562 Mono Audio Amplifier |
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| 4 | * |
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| 5 | * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | * |
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| 7 | * Author: Dan Murphy <dmurphy@ti.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __TAS2562_H__ |
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| 11 | #define __TAS2562_H__ |
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| 12 | |
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| 13 | #define TAS2562_PAGE_CTRL 0x00 |
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| 14 | |
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| 15 | #define TAS2562_REG(page, reg) ((page * 128) + reg) |
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| 16 | |
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| 17 | #define TAS2562_SW_RESET TAS2562_REG(0, 0x01) |
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| 18 | #define TAS2562_PWR_CTRL TAS2562_REG(0, 0x02) |
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| 19 | #define TAS2562_PB_CFG1 TAS2562_REG(0, 0x03) |
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| 20 | #define TAS2562_MISC_CFG1 TAS2562_REG(0, 0x04) |
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| 21 | #define TAS2562_MISC_CFG2 TAS2562_REG(0, 0x05) |
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| 22 | |
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| 23 | #define TAS2562_TDM_CFG0 TAS2562_REG(0, 0x06) |
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| 24 | #define TAS2562_TDM_CFG1 TAS2562_REG(0, 0x07) |
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| 25 | #define TAS2562_TDM_CFG2 TAS2562_REG(0, 0x08) |
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| 26 | #define TAS2562_TDM_CFG3 TAS2562_REG(0, 0x09) |
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| 27 | #define TAS2562_TDM_CFG4 TAS2562_REG(0, 0x0a) |
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| 28 | #define TAS2562_TDM_CFG5 TAS2562_REG(0, 0x0b) |
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| 29 | #define TAS2562_TDM_CFG6 TAS2562_REG(0, 0x0c) |
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| 30 | #define TAS2562_TDM_CFG7 TAS2562_REG(0, 0x0d) |
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| 31 | #define TAS2562_TDM_CFG8 TAS2562_REG(0, 0x0e) |
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| 32 | #define TAS2562_TDM_CFG9 TAS2562_REG(0, 0x0f) |
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| 33 | #define TAS2562_TDM_CFG10 TAS2562_REG(0, 0x10) |
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| 34 | #define TAS2562_TDM_DET TAS2562_REG(0, 0x11) |
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| 35 | #define TAS2562_REV_ID TAS2562_REG(0, 0x7d) |
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| 36 | |
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| 37 | #define TAS2562_RX_OFF_MASK GENMASK(5, 1) |
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| 38 | #define TAS2562_TX_OFF_MASK GENMASK(3, 1) |
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| 39 | #define TAS2562_RIGHT_SLOT_SHIFT 4 |
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| 40 | |
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| 41 | /* Page 2 */ |
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| 42 | #define TAS2562_DVC_CFG1 TAS2562_REG(2, 0x0c) |
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| 43 | #define TAS2562_DVC_CFG2 TAS2562_REG(2, 0x0d) |
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| 44 | #define TAS2562_DVC_CFG3 TAS2562_REG(2, 0x0e) |
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| 45 | #define TAS2562_DVC_CFG4 TAS2562_REG(2, 0x0f) |
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| 46 | |
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| 47 | #define TAS2562_RESET BIT(0) |
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| 48 | |
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| 49 | #define TAS2562_MODE_MASK GENMASK(1,0) |
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| 50 | #define TAS2562_ACTIVE 0x0 |
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| 51 | #define TAS2562_MUTE 0x1 |
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| 52 | #define TAS2562_SHUTDOWN 0x2 |
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| 53 | |
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| 54 | #define TAS2562_TDM_CFG1_RX_EDGE_MASK BIT(0) |
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| 55 | #define TAS2562_TDM_CFG1_RX_FALLING 1 |
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| 56 | |
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| 57 | #define TAS2562_TDM_CFG0_RAMPRATE_MASK BIT(5) |
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| 58 | #define TAS2562_TDM_CFG0_RAMPRATE_44_1 BIT(5) |
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| 59 | #define TAS2562_TDM_CFG0_SAMPRATE_MASK GENMASK(3, 1) |
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| 60 | #define TAS2562_TDM_CFG0_SAMPRATE_7305_8KHZ (0x0 << 1) |
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| 61 | #define TAS2562_TDM_CFG0_SAMPRATE_14_7_16KHZ (0x1 << 1) |
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| 62 | #define TAS2562_TDM_CFG0_SAMPRATE_22_05_24KHZ (0x2 << 1) |
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| 63 | #define TAS2562_TDM_CFG0_SAMPRATE_29_4_32KHZ (0x3 << 1) |
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| 64 | #define TAS2562_TDM_CFG0_SAMPRATE_44_1_48KHZ (0x4 << 1) |
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| 65 | #define TAS2562_TDM_CFG0_SAMPRATE_88_2_96KHZ (0x5 << 1) |
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| 66 | #define TAS2562_TDM_CFG0_SAMPRATE_176_4_192KHZ (0x6 << 1) |
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| 67 | |
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| 68 | #define TAS2562_TDM_CFG2_RIGHT_JUSTIFY BIT(6) |
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| 69 | |
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| 70 | #define TAS2562_TDM_CFG2_RXLEN_MASK GENMASK(1, 0) |
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| 71 | #define TAS2562_TDM_CFG2_RXLEN_16B 0x0 |
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| 72 | #define TAS2562_TDM_CFG2_RXLEN_24B BIT(0) |
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| 73 | #define TAS2562_TDM_CFG2_RXLEN_32B BIT(1) |
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| 74 | |
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| 75 | #define TAS2562_TDM_CFG2_RXWLEN_MASK GENMASK(3, 2) |
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| 76 | #define TAS2562_TDM_CFG2_RXWLEN_16B 0x0 |
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| 77 | #define TAS2562_TDM_CFG2_RXWLEN_20B BIT(2) |
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| 78 | #define TAS2562_TDM_CFG2_RXWLEN_24B BIT(3) |
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| 79 | #define TAS2562_TDM_CFG2_RXWLEN_32B (BIT(2) | BIT(3)) |
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| 80 | |
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| 81 | #define TAS2562_VSENSE_POWER_EN 2 |
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| 82 | #define TAS2562_ISENSE_POWER_EN 3 |
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| 83 | |
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| 84 | #define TAS2562_TDM_CFG5_VSNS_EN BIT(6) |
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| 85 | #define TAS2562_TDM_CFG5_VSNS_SLOT_MASK GENMASK(5, 0) |
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| 86 | |
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| 87 | #define TAS2562_TDM_CFG6_ISNS_EN BIT(6) |
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| 88 | #define TAS2562_TDM_CFG6_ISNS_SLOT_MASK GENMASK(5, 0) |
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| 89 | |
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| 90 | #endif /* __TAS2562_H__ */ |
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| 91 | |
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