| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * tas2764.h - ALSA SoC Texas Instruments TAS2764 Mono Audio Amplifier |
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| 4 | * |
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| 5 | * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | * |
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| 7 | * Author: Dan Murphy <dmurphy@ti.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __TAS2764__ |
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| 11 | #define __TAS2764__ |
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| 12 | |
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| 13 | /* Book Control Register */ |
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| 14 | #define TAS2764_BOOKCTL_PAGE 0 |
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| 15 | #define TAS2764_BOOKCTL_REG 127 |
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| 16 | #define TAS2764_REG(page, reg) ((page * 128) + reg) |
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| 17 | |
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| 18 | /* Page */ |
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| 19 | #define TAS2764_PAGE TAS2764_REG(0X0, 0x00) |
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| 20 | #define TAS2764_PAGE_PAGE_MASK 255 |
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| 21 | |
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| 22 | /* Software Reset */ |
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| 23 | #define TAS2764_SW_RST TAS2764_REG(0X0, 0x01) |
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| 24 | #define TAS2764_RST BIT(0) |
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| 25 | |
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| 26 | /* Power Control */ |
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| 27 | #define TAS2764_PWR_CTRL TAS2764_REG(0X0, 0x02) |
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| 28 | #define TAS2764_PWR_CTRL_MASK GENMASK(2, 0) |
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| 29 | #define TAS2764_PWR_CTRL_ACTIVE 0x0 |
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| 30 | #define TAS2764_PWR_CTRL_MUTE BIT(0) |
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| 31 | #define TAS2764_PWR_CTRL_SHUTDOWN BIT(1) |
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| 32 | #define TAS2764_PWR_CTRL_BOP_SRC BIT(7) |
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| 33 | |
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| 34 | #define TAS2764_VSENSE_POWER_EN 3 |
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| 35 | #define TAS2764_ISENSE_POWER_EN 4 |
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| 36 | |
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| 37 | /* DC Blocker Control */ |
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| 38 | #define TAS2764_DC_BLK0 TAS2764_REG(0x0, 0x04) |
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| 39 | #define TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT 0 |
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| 40 | |
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| 41 | /* Digital Volume Control */ |
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| 42 | #define TAS2764_DVC TAS2764_REG(0X0, 0x1a) |
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| 43 | #define TAS2764_DVC_MAX 0xc9 |
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| 44 | |
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| 45 | #define TAS2764_CHNL_0 TAS2764_REG(0X0, 0x03) |
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| 46 | |
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| 47 | /* Miscellaneous */ |
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| 48 | #define TAS2764_MISC_CFG1 TAS2764_REG(0x0, 0x06) |
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| 49 | #define TAS2764_MISC_CFG1_OCE_RETRY_SHIFT 5 |
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| 50 | |
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| 51 | /* TDM Configuration Reg0 */ |
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| 52 | #define TAS2764_TDM_CFG0 TAS2764_REG(0X0, 0x08) |
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| 53 | #define TAS2764_TDM_CFG0_SMP_MASK BIT(5) |
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| 54 | #define TAS2764_TDM_CFG0_SMP_48KHZ 0x0 |
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| 55 | #define TAS2764_TDM_CFG0_SMP_44_1KHZ BIT(5) |
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| 56 | #define TAS2764_TDM_CFG0_MASK GENMASK(3, 1) |
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| 57 | #define TAS2764_TDM_CFG0_44_1_48KHZ BIT(3) |
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| 58 | #define TAS2764_TDM_CFG0_88_2_96KHZ (BIT(3) | BIT(1)) |
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| 59 | #define TAS2764_TDM_CFG0_FRAME_START BIT(0) |
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| 60 | |
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| 61 | /* TDM Configuration Reg1 */ |
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| 62 | #define TAS2764_TDM_CFG1 TAS2764_REG(0X0, 0x09) |
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| 63 | #define TAS2764_TDM_CFG1_MASK GENMASK(5, 1) |
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| 64 | #define TAS2764_TDM_CFG1_51_SHIFT 1 |
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| 65 | #define TAS2764_TDM_CFG1_RX_MASK BIT(0) |
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| 66 | #define TAS2764_TDM_CFG1_RX_RISING 0x0 |
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| 67 | #define TAS2764_TDM_CFG1_RX_FALLING BIT(0) |
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| 68 | |
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| 69 | /* TDM Configuration Reg2 */ |
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| 70 | #define TAS2764_TDM_CFG2 TAS2764_REG(0X0, 0x0a) |
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| 71 | #define TAS2764_TDM_CFG2_RXW_MASK GENMASK(3, 2) |
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| 72 | #define TAS2764_TDM_CFG2_RXW_16BITS 0x0 |
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| 73 | #define TAS2764_TDM_CFG2_RXW_24BITS BIT(3) |
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| 74 | #define TAS2764_TDM_CFG2_RXW_32BITS (BIT(3) | BIT(2)) |
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| 75 | #define TAS2764_TDM_CFG2_RXS_MASK GENMASK(1, 0) |
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| 76 | #define TAS2764_TDM_CFG2_RXS_16BITS 0x0 |
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| 77 | #define TAS2764_TDM_CFG2_RXS_24BITS BIT(0) |
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| 78 | #define TAS2764_TDM_CFG2_RXS_32BITS BIT(1) |
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| 79 | #define TAS2764_TDM_CFG2_SCFG_SHIFT 4 |
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| 80 | |
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| 81 | /* TDM Configuration Reg3 */ |
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| 82 | #define TAS2764_TDM_CFG3 TAS2764_REG(0X0, 0x0c) |
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| 83 | #define TAS2764_TDM_CFG3_RXS_MASK GENMASK(7, 4) |
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| 84 | #define TAS2764_TDM_CFG3_RXS_SHIFT 0x4 |
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| 85 | #define TAS2764_TDM_CFG3_MASK GENMASK(3, 0) |
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| 86 | |
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| 87 | /* TDM Configuration Reg4 */ |
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| 88 | #define TAS2764_TDM_CFG4 TAS2764_REG(0X0, 0x0d) |
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| 89 | #define TAS2764_TDM_CFG4_TX_MASK BIT(0) |
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| 90 | #define TAS2764_TDM_CFG4_TX_RISING 0x0 |
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| 91 | #define TAS2764_TDM_CFG4_TX_FALLING BIT(0) |
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| 92 | |
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| 93 | /* TDM Configuration Reg5 */ |
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| 94 | #define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e) |
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| 95 | #define TAS2764_TDM_CFG5_VSNS_MASK BIT(6) |
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| 96 | #define TAS2764_TDM_CFG5_VSNS_ENABLE BIT(6) |
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| 97 | #define TAS2764_TDM_CFG5_50_MASK GENMASK(5, 0) |
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| 98 | |
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| 99 | /* TDM Configuration Reg6 */ |
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| 100 | #define TAS2764_TDM_CFG6 TAS2764_REG(0X0, 0x0f) |
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| 101 | #define TAS2764_TDM_CFG6_ISNS_MASK BIT(6) |
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| 102 | #define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6) |
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| 103 | #define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0) |
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| 104 | |
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| 105 | /* Interrupt Masks */ |
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| 106 | #define TAS2764_INT_MASK0 TAS2764_REG(0x0, 0x3b) |
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| 107 | #define TAS2764_INT_MASK1 TAS2764_REG(0x0, 0x3c) |
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| 108 | #define TAS2764_INT_MASK2 TAS2764_REG(0x0, 0x40) |
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| 109 | #define TAS2764_INT_MASK3 TAS2764_REG(0x0, 0x41) |
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| 110 | #define TAS2764_INT_MASK4 TAS2764_REG(0x0, 0x3d) |
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| 111 | |
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| 112 | /* Latched Fault Registers */ |
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| 113 | #define TAS2764_INT_LTCH0 TAS2764_REG(0x0, 0x49) |
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| 114 | #define TAS2764_INT_LTCH1 TAS2764_REG(0x0, 0x4a) |
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| 115 | #define TAS2764_INT_LTCH1_0 TAS2764_REG(0x0, 0x4b) |
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| 116 | #define TAS2764_INT_LTCH2 TAS2764_REG(0x0, 0x4f) |
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| 117 | #define TAS2764_INT_LTCH3 TAS2764_REG(0x0, 0x50) |
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| 118 | #define TAS2764_INT_LTCH4 TAS2764_REG(0x0, 0x51) |
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| 119 | |
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| 120 | /* Readout Registers */ |
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| 121 | #define TAS2764_TEMP TAS2764_REG(0x0, 0x56) |
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| 122 | |
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| 123 | /* Clock/IRQ Settings */ |
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| 124 | #define TAS2764_INT_CLK_CFG TAS2764_REG(0x0, 0x5c) |
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| 125 | #define TAS2764_INT_CLK_CFG_IRQZ_CLR BIT(2) |
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| 126 | |
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| 127 | #define TAS2764_BOP_CFG0 TAS2764_REG(0X0, 0x1d) |
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| 128 | |
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| 129 | #endif /* __TAS2764__ */ |
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| 130 | |
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