| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
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| 4 | * http://www.samsung.com |
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| 5 | * |
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| 6 | * Samsung I2S driver's register header |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __SND_SOC_SAMSUNG_I2S_REGS_H |
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| 10 | #define __SND_SOC_SAMSUNG_I2S_REGS_H |
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| 11 | |
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| 12 | #define I2SCON 0x0 |
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| 13 | #define I2SMOD 0x4 |
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| 14 | #define I2SFIC 0x8 |
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| 15 | #define I2SPSR 0xc |
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| 16 | #define I2STXD 0x10 |
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| 17 | #define I2SRXD 0x14 |
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| 18 | #define I2SFICS 0x18 |
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| 19 | #define I2STXDS 0x1c |
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| 20 | #define I2SAHB 0x20 |
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| 21 | #define I2SSTR0 0x24 |
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| 22 | #define I2SSIZE 0x28 |
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| 23 | #define I2STRNCNT 0x2c |
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| 24 | #define I2SLVL0ADDR 0x30 |
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| 25 | #define I2SLVL1ADDR 0x34 |
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| 26 | #define I2SLVL2ADDR 0x38 |
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| 27 | #define I2SLVL3ADDR 0x3c |
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| 28 | #define I2SSTR1 0x40 |
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| 29 | #define I2SVER 0x44 |
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| 30 | #define I2SFIC1 0x48 |
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| 31 | #define I2STDM 0x4c |
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| 32 | #define I2SFSTA 0x50 |
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| 33 | |
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| 34 | #define CON_RSTCLR (1 << 31) |
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| 35 | #define CON_FRXOFSTATUS (1 << 26) |
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| 36 | #define CON_FRXORINTEN (1 << 25) |
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| 37 | #define CON_FTXSURSTAT (1 << 24) |
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| 38 | #define CON_FTXSURINTEN (1 << 23) |
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| 39 | #define CON_TXSDMA_PAUSE (1 << 20) |
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| 40 | #define CON_TXSDMA_ACTIVE (1 << 18) |
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| 41 | |
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| 42 | #define CON_FTXURSTATUS (1 << 17) |
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| 43 | #define CON_FTXURINTEN (1 << 16) |
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| 44 | #define CON_TXFIFO2_EMPTY (1 << 15) |
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| 45 | #define CON_TXFIFO1_EMPTY (1 << 14) |
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| 46 | #define CON_TXFIFO2_FULL (1 << 13) |
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| 47 | #define CON_TXFIFO1_FULL (1 << 12) |
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| 48 | |
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| 49 | #define CON_LRINDEX (1 << 11) |
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| 50 | #define CON_TXFIFO_EMPTY (1 << 10) |
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| 51 | #define CON_RXFIFO_EMPTY (1 << 9) |
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| 52 | #define CON_TXFIFO_FULL (1 << 8) |
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| 53 | #define CON_RXFIFO_FULL (1 << 7) |
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| 54 | #define CON_TXDMA_PAUSE (1 << 6) |
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| 55 | #define CON_RXDMA_PAUSE (1 << 5) |
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| 56 | #define CON_TXCH_PAUSE (1 << 4) |
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| 57 | #define CON_RXCH_PAUSE (1 << 3) |
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| 58 | #define CON_TXDMA_ACTIVE (1 << 2) |
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| 59 | #define CON_RXDMA_ACTIVE (1 << 1) |
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| 60 | #define CON_ACTIVE (1 << 0) |
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| 61 | |
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| 62 | #define MOD_OPCLK_SHIFT 30 |
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| 63 | #define MOD_OPCLK_CDCLK_OUT (0 << MOD_OPCLK_SHIFT) |
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| 64 | #define MOD_OPCLK_CDCLK_IN (1 << MOD_OPCLK_SHIFT) |
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| 65 | #define MOD_OPCLK_BCLK_OUT (2 << MOD_OPCLK_SHIFT) |
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| 66 | #define MOD_OPCLK_PCLK (3 << MOD_OPCLK_SHIFT) |
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| 67 | #define MOD_OPCLK_MASK (3 << MOD_OPCLK_SHIFT) |
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| 68 | #define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ |
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| 69 | |
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| 70 | #define MOD_BLCS_SHIFT 26 |
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| 71 | #define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT) |
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| 72 | #define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT) |
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| 73 | #define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT) |
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| 74 | #define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT) |
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| 75 | #define MOD_BLCP_SHIFT 24 |
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| 76 | #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) |
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| 77 | #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) |
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| 78 | #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) |
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| 79 | #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) |
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| 80 | |
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| 81 | #define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ |
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| 82 | #define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ |
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| 83 | #define MOD_C1DD_HHALF (1 << 19) |
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| 84 | #define MOD_C1DD_LHALF (1 << 18) |
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| 85 | #define MOD_DC2_EN (1 << 17) |
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| 86 | #define MOD_DC1_EN (1 << 16) |
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| 87 | #define MOD_BLC_16BIT (0 << 13) |
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| 88 | #define MOD_BLC_8BIT (1 << 13) |
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| 89 | #define MOD_BLC_24BIT (2 << 13) |
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| 90 | #define MOD_BLC_MASK (3 << 13) |
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| 91 | |
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| 92 | #define MOD_TXONLY (0 << 8) |
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| 93 | #define MOD_RXONLY (1 << 8) |
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| 94 | #define MOD_TXRX (2 << 8) |
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| 95 | #define MOD_MASK (3 << 8) |
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| 96 | #define MOD_LRP_SHIFT 7 |
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| 97 | #define MOD_LR_LLOW 0 |
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| 98 | #define MOD_LR_RLOW 1 |
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| 99 | #define MOD_SDF_SHIFT 5 |
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| 100 | #define MOD_SDF_IIS 0 |
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| 101 | #define MOD_SDF_MSB 1 |
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| 102 | #define MOD_SDF_LSB 2 |
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| 103 | #define MOD_SDF_MASK 3 |
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| 104 | #define MOD_RCLK_SHIFT 3 |
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| 105 | #define MOD_RCLK_256FS 0 |
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| 106 | #define MOD_RCLK_512FS 1 |
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| 107 | #define MOD_RCLK_384FS 2 |
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| 108 | #define MOD_RCLK_768FS 3 |
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| 109 | #define MOD_RCLK_MASK 3 |
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| 110 | #define MOD_BCLK_SHIFT 1 |
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| 111 | #define MOD_BCLK_32FS 0 |
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| 112 | #define MOD_BCLK_48FS 1 |
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| 113 | #define MOD_BCLK_16FS 2 |
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| 114 | #define MOD_BCLK_24FS 3 |
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| 115 | #define MOD_BCLK_MASK 3 |
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| 116 | #define MOD_8BIT (1 << 0) |
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| 117 | |
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| 118 | #define EXYNOS5420_MOD_LRP_SHIFT 15 |
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| 119 | #define EXYNOS5420_MOD_SDF_SHIFT 6 |
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| 120 | #define EXYNOS5420_MOD_RCLK_SHIFT 4 |
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| 121 | #define EXYNOS5420_MOD_BCLK_SHIFT 0 |
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| 122 | #define EXYNOS5420_MOD_BCLK_64FS 4 |
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| 123 | #define EXYNOS5420_MOD_BCLK_96FS 5 |
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| 124 | #define EXYNOS5420_MOD_BCLK_128FS 6 |
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| 125 | #define EXYNOS5420_MOD_BCLK_192FS 7 |
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| 126 | #define EXYNOS5420_MOD_BCLK_256FS 8 |
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| 127 | #define EXYNOS5420_MOD_BCLK_MASK 0xf |
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| 128 | |
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| 129 | #define EXYNOS7_MOD_RCLK_64FS 4 |
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| 130 | #define EXYNOS7_MOD_RCLK_128FS 5 |
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| 131 | #define EXYNOS7_MOD_RCLK_96FS 6 |
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| 132 | #define EXYNOS7_MOD_RCLK_192FS 7 |
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| 133 | |
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| 134 | #define PSR_PSREN (1 << 15) |
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| 135 | #define PSR_PSVAL(x) ((((x) - 1) << 8) & 0x3f00) |
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| 136 | |
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| 137 | #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf) |
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| 138 | #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf) |
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| 139 | |
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| 140 | #define FIC_TXFLUSH (1 << 15) |
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| 141 | #define FIC_RXFLUSH (1 << 7) |
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| 142 | |
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| 143 | #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf) |
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| 144 | #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf) |
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| 145 | #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f) |
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| 146 | |
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| 147 | #define AHB_INTENLVL0 (1 << 24) |
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| 148 | #define AHB_LVL0INT (1 << 20) |
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| 149 | #define AHB_CLRLVL0INT (1 << 16) |
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| 150 | #define AHB_DMARLD (1 << 5) |
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| 151 | #define AHB_INTMASK (1 << 3) |
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| 152 | #define AHB_DMAEN (1 << 0) |
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| 153 | #define AHB_LVLINTMASK (0xf << 20) |
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| 154 | |
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| 155 | #define I2SSIZE_TRNMSK (0xffff) |
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| 156 | #define I2SSIZE_SHIFT (16) |
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| 157 | |
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| 158 | #endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */ |
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| 159 | |
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