| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * omap-dmic.h -- OMAP Digital Microphone Controller |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _OMAP_DMIC_H |
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| 7 | #define _OMAP_DMIC_H |
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| 8 | |
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| 9 | #define OMAP_DMIC_REVISION_REG 0x00 |
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| 10 | #define OMAP_DMIC_SYSCONFIG_REG 0x10 |
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| 11 | #define OMAP_DMIC_IRQSTATUS_RAW_REG 0x24 |
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| 12 | #define OMAP_DMIC_IRQSTATUS_REG 0x28 |
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| 13 | #define OMAP_DMIC_IRQENABLE_SET_REG 0x2C |
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| 14 | #define OMAP_DMIC_IRQENABLE_CLR_REG 0x30 |
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| 15 | #define OMAP_DMIC_IRQWAKE_EN_REG 0x34 |
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| 16 | #define OMAP_DMIC_DMAENABLE_SET_REG 0x38 |
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| 17 | #define OMAP_DMIC_DMAENABLE_CLR_REG 0x3C |
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| 18 | #define OMAP_DMIC_DMAWAKEEN_REG 0x40 |
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| 19 | #define OMAP_DMIC_CTRL_REG 0x44 |
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| 20 | #define OMAP_DMIC_DATA_REG 0x48 |
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| 21 | #define OMAP_DMIC_FIFO_CTRL_REG 0x4C |
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| 22 | #define OMAP_DMIC_FIFO_DMIC1R_DATA_REG 0x50 |
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| 23 | #define OMAP_DMIC_FIFO_DMIC1L_DATA_REG 0x54 |
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| 24 | #define OMAP_DMIC_FIFO_DMIC2R_DATA_REG 0x58 |
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| 25 | #define OMAP_DMIC_FIFO_DMIC2L_DATA_REG 0x5C |
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| 26 | #define OMAP_DMIC_FIFO_DMIC3R_DATA_REG 0x60 |
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| 27 | #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64 |
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| 28 | |
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| 29 | /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */ |
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| 30 | #define OMAP_DMIC_IRQ (1 << 0) |
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| 31 | #define OMAP_DMIC_IRQ_FULL (1 << 1) |
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| 32 | #define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2) |
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| 33 | #define OMAP_DMIC_IRQ_EMPTY (1 << 3) |
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| 34 | #define OMAP_DMIC_IRQ_MASK 0x07 |
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| 35 | |
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| 36 | /* DMIC_DMAENABLE bit fields */ |
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| 37 | #define OMAP_DMIC_DMA_ENABLE 0x1 |
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| 38 | |
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| 39 | /* DMIC_CTRL bit fields */ |
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| 40 | #define OMAP_DMIC_UP1_ENABLE (1 << 0) |
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| 41 | #define OMAP_DMIC_UP2_ENABLE (1 << 1) |
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| 42 | #define OMAP_DMIC_UP3_ENABLE (1 << 2) |
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| 43 | #define OMAP_DMIC_UP_ENABLE_MASK 0x7 |
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| 44 | #define OMAP_DMIC_FORMAT (1 << 3) |
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| 45 | #define OMAP_DMIC_POLAR1 (1 << 4) |
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| 46 | #define OMAP_DMIC_POLAR2 (1 << 5) |
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| 47 | #define OMAP_DMIC_POLAR3 (1 << 6) |
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| 48 | #define OMAP_DMIC_POLAR_MASK (0x7 << 4) |
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| 49 | #define OMAP_DMIC_CLK_DIV(x) (((x) & 0x7) << 7) |
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| 50 | #define OMAP_DMIC_CLK_DIV_MASK (0x7 << 7) |
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| 51 | #define OMAP_DMIC_RESET (1 << 10) |
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| 52 | |
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| 53 | #define OMAP_DMICOUTFORMAT_LJUST (0 << 3) |
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| 54 | #define OMAP_DMICOUTFORMAT_RJUST (1 << 3) |
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| 55 | |
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| 56 | /* DMIC_FIFO_CTRL bit fields */ |
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| 57 | #define OMAP_DMIC_THRES_MAX 0xF |
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| 58 | |
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| 59 | enum omap_dmic_clk { |
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| 60 | OMAP_DMIC_SYSCLK_PAD_CLKS, /* PAD_CLKS */ |
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| 61 | OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS, /* SLIMBUS_CLK */ |
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| 62 | OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, /* DMIC_SYNC_MUX_CLK */ |
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| 63 | OMAP_DMIC_ABE_DMIC_CLK, /* abe_dmic_clk */ |
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| 64 | }; |
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| 65 | |
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| 66 | #endif |
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| 67 | |
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