| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * omap-mcpdm.h |
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| 4 | * |
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| 5 | * Copyright (C) 2009 - 2011 Texas Instruments |
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| 6 | * |
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| 7 | * Contact: Misael Lopez Cruz <misael.lopez@ti.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __OMAP_MCPDM_H__ |
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| 11 | #define __OMAP_MCPDM_H__ |
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| 12 | |
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| 13 | #define MCPDM_REG_REVISION 0x00 |
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| 14 | #define MCPDM_REG_SYSCONFIG 0x10 |
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| 15 | #define MCPDM_REG_IRQSTATUS_RAW 0x24 |
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| 16 | #define MCPDM_REG_IRQSTATUS 0x28 |
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| 17 | #define MCPDM_REG_IRQENABLE_SET 0x2C |
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| 18 | #define MCPDM_REG_IRQENABLE_CLR 0x30 |
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| 19 | #define MCPDM_REG_IRQWAKE_EN 0x34 |
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| 20 | #define MCPDM_REG_DMAENABLE_SET 0x38 |
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| 21 | #define MCPDM_REG_DMAENABLE_CLR 0x3C |
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| 22 | #define MCPDM_REG_DMAWAKEEN 0x40 |
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| 23 | #define MCPDM_REG_CTRL 0x44 |
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| 24 | #define MCPDM_REG_DN_DATA 0x48 |
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| 25 | #define MCPDM_REG_UP_DATA 0x4C |
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| 26 | #define MCPDM_REG_FIFO_CTRL_DN 0x50 |
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| 27 | #define MCPDM_REG_FIFO_CTRL_UP 0x54 |
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| 28 | #define MCPDM_REG_DN_OFFSET 0x58 |
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| 29 | |
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| 30 | /* |
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| 31 | * MCPDM_IRQ bit fields |
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| 32 | * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR |
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| 33 | */ |
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| 34 | |
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| 35 | #define MCPDM_DN_IRQ (1 << 0) |
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| 36 | #define MCPDM_DN_IRQ_EMPTY (1 << 1) |
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| 37 | #define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) |
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| 38 | #define MCPDM_DN_IRQ_FULL (1 << 3) |
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| 39 | |
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| 40 | #define MCPDM_UP_IRQ (1 << 8) |
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| 41 | #define MCPDM_UP_IRQ_EMPTY (1 << 9) |
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| 42 | #define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) |
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| 43 | #define MCPDM_UP_IRQ_FULL (1 << 11) |
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| 44 | |
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| 45 | #define MCPDM_DOWNLINK_IRQ_MASK 0x00F |
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| 46 | #define MCPDM_UPLINK_IRQ_MASK 0xF00 |
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| 47 | |
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| 48 | /* |
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| 49 | * MCPDM_DMAENABLE bit fields |
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| 50 | */ |
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| 51 | |
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| 52 | #define MCPDM_DMA_DN_ENABLE (1 << 0) |
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| 53 | #define MCPDM_DMA_UP_ENABLE (1 << 1) |
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| 54 | |
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| 55 | /* |
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| 56 | * MCPDM_CTRL bit fields |
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| 57 | */ |
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| 58 | |
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| 59 | #define MCPDM_PDM_UPLINK_EN(x) (1 << (x - 1)) /* ch1 is at bit 0 */ |
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| 60 | #define MCPDM_PDM_DOWNLINK_EN(x) (1 << (x + 2)) /* ch1 is at bit 3 */ |
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| 61 | #define MCPDM_PDMOUTFORMAT (1 << 8) |
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| 62 | #define MCPDM_CMD_INT (1 << 9) |
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| 63 | #define MCPDM_STATUS_INT (1 << 10) |
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| 64 | #define MCPDM_SW_UP_RST (1 << 11) |
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| 65 | #define MCPDM_SW_DN_RST (1 << 12) |
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| 66 | #define MCPDM_WD_EN (1 << 14) |
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| 67 | #define MCPDM_PDM_UP_MASK 0x7 |
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| 68 | #define MCPDM_PDM_DN_MASK (0x1f << 3) |
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| 69 | |
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| 70 | |
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| 71 | #define MCPDM_PDMOUTFORMAT_LJUST (0 << 8) |
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| 72 | #define MCPDM_PDMOUTFORMAT_RJUST (1 << 8) |
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| 73 | |
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| 74 | /* |
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| 75 | * MCPDM_FIFO_CTRL bit fields |
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| 76 | */ |
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| 77 | |
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| 78 | #define MCPDM_UP_THRES_MAX 0xF |
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| 79 | #define MCPDM_DN_THRES_MAX 0xF |
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| 80 | |
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| 81 | /* |
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| 82 | * MCPDM_DN_OFFSET bit fields |
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| 83 | */ |
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| 84 | |
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| 85 | #define MCPDM_DN_OFST_RX1_EN (1 << 0) |
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| 86 | #define MCPDM_DNOFST_RX1(x) ((x & 0x1f) << 1) |
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| 87 | #define MCPDM_DN_OFST_RX2_EN (1 << 8) |
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| 88 | #define MCPDM_DNOFST_RX2(x) ((x & 0x1f) << 9) |
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| 89 | |
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| 90 | void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd, |
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| 91 | u8 rx1, u8 rx2); |
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| 92 | |
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| 93 | #endif /* End of __OMAP_MCPDM_H__ */ |
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| 94 | |
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