| 1 | // RUN: %check_clang_tidy %s altera-kernel-name-restriction %t -- -- -I%S/Inputs/kernel-name-restriction |
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| 2 | // RUN: %check_clang_tidy -check-suffix=UPPERCASE %s altera-kernel-name-restriction %t -- -- -I%S/Inputs/kernel-name-restriction/uppercase -DUPPERCASE |
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| 3 | |
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| 4 | #ifdef UPPERCASE |
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| 5 | // The warning should be triggered regardless of capitalization |
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| 6 | #include "KERNEL.cl" |
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| 7 | // CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'KERNEL.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 8 | #include "vERILOG.cl" |
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| 9 | // CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'vERILOG.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 10 | #include "VHDL.cl" |
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| 11 | // CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'VHDL.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 12 | #else |
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| 13 | // These are the banned kernel filenames, and should trigger warnings |
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| 14 | #include "kernel.cl" |
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| 15 | // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'kernel.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 16 | #include "Verilog.cl" |
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| 17 | // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'Verilog.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 18 | #include "vhdl.CL" |
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| 19 | // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'vhdl.CL' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 20 | |
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| 21 | |
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| 22 | // The warning should be triggered if the names are within a directory |
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| 23 | #include "some/dir/kernel.cl" |
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| 24 | // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'kernel.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 25 | #include "somedir/verilog.cl" |
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| 26 | // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'verilog.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 27 | #include "otherdir/vhdl.cl" |
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| 28 | // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'vhdl.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction] |
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| 29 | |
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| 30 | // There are no FIX-ITs for the altera-kernel-name-restriction lint check |
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| 31 | |
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| 32 | // The following include directives shouldn't trigger the warning |
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| 33 | #include "otherthing.cl" |
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| 34 | #include "thing.h" |
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| 35 | |
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| 36 | // It doesn't make sense to have kernel.h, verilog.h, or vhdl.h as filenames |
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| 37 | // without the corresponding .cl files, but the Altera Programming Guide doesn't |
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| 38 | // explicitly forbid it. |
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| 39 | #include "kernel.h" |
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| 40 | #include "verilog.h" |
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| 41 | #include "vhdl.h" |
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| 42 | |
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| 43 | // The files can still have the forbidden names in them, so long as they're not |
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| 44 | // the entire file name, and are not the kernel source file name. |
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| 45 | #include "some_kernel.cl" |
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| 46 | #include "other_Verilog.cl" |
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| 47 | #include "vhdl_number_two.cl" |
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| 48 | |
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| 49 | // Naming a directory kernel.cl, verilog.cl, or vhdl.cl is not explicitly |
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| 50 | // forbidden in the Altera Programming Guide either. |
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| 51 | #include "some/kernel.cl/foo.h" |
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| 52 | #include "some/verilog.cl/foo.h" |
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| 53 | #include "some/vhdl.cl/foo.h" |
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| 54 | #endif |
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| 55 | |
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| 56 | |
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