1//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCV.h"
10#include "../Clang.h"
11#include "ToolChains/CommonArgs.h"
12#include "clang/Basic/CharInfo.h"
13#include "clang/Driver/Driver.h"
14#include "clang/Driver/DriverDiagnostic.h"
15#include "clang/Driver/Options.h"
16#include "llvm/Option/ArgList.h"
17#include "llvm/Support/Error.h"
18#include "llvm/Support/raw_ostream.h"
19#include "llvm/TargetParser/Host.h"
20#include "llvm/TargetParser/RISCVISAInfo.h"
21#include "llvm/TargetParser/RISCVTargetParser.h"
22
23using namespace clang::driver;
24using namespace clang::driver::tools;
25using namespace clang;
26using namespace llvm::opt;
27
28// Returns false if an error is diagnosed.
29static bool getArchFeatures(const Driver &D, StringRef Arch,
30 std::vector<StringRef> &Features,
31 const ArgList &Args) {
32 bool EnableExperimentalExtensions =
33 Args.hasArg(options::OPT_menable_experimental_extensions);
34 auto ISAInfo =
35 llvm::RISCVISAInfo::parseArchString(Arch, EnableExperimentalExtension: EnableExperimentalExtensions);
36 if (!ISAInfo) {
37 handleAllErrors(ISAInfo.takeError(), [&](llvm::StringError &ErrMsg) {
38 D.Diag(diag::DiagID: err_drv_invalid_riscv_arch_name)
39 << Arch << ErrMsg.getMessage();
40 });
41
42 return false;
43 }
44
45 for (const std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
46 /*IgnoreUnknown=*/false))
47 Features.push_back(Args.MakeArgString(Str));
48
49 if (EnableExperimentalExtensions)
50 Features.push_back(x: Args.MakeArgString(Str: "+experimental"));
51
52 return true;
53}
54
55// Get features except standard extension feature
56static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
57 const llvm::Triple &Triple,
58 StringRef Mcpu,
59 std::vector<StringRef> &Features) {
60 bool Is64Bit = Triple.isRISCV64();
61 if (!llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: Is64Bit)) {
62 // Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
63 if (llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: !Is64Bit))
64 D.Diag(clang::diag::DiagID: err_drv_invalid_riscv_cpu_name_for_target)
65 << Mcpu << Is64Bit;
66 else
67 D.Diag(clang::diag::DiagID: err_drv_unsupported_option_argument)
68 << A->getSpelling() << Mcpu;
69 }
70
71 if (llvm::RISCV::hasFastUnalignedAccess(CPU: Mcpu)) {
72 Features.push_back(x: "+unaligned-scalar-mem");
73 Features.push_back(x: "+unaligned-vector-mem");
74 }
75}
76
77void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
78 const ArgList &Args,
79 std::vector<StringRef> &Features) {
80 StringRef MArch = getRISCVArch(Args, Triple);
81
82 if (!getArchFeatures(D, Arch: MArch, Features, Args))
83 return;
84
85 // If users give march and mcpu, get std extension feature from MArch
86 // and other features (ex. mirco architecture feature) from mcpu
87 if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
88 StringRef CPU = A->getValue();
89 if (CPU == "native")
90 CPU = llvm::sys::getHostCPUName();
91
92 getRISCFeaturesFromMcpu(D, A, Triple, Mcpu: CPU, Features);
93 }
94
95 // Handle features corresponding to "-ffixed-X" options
96 if (Args.hasArg(options::OPT_ffixed_x1))
97 Features.push_back(x: "+reserve-x1");
98 if (Args.hasArg(options::OPT_ffixed_x2))
99 Features.push_back(x: "+reserve-x2");
100 if (Args.hasArg(options::OPT_ffixed_x3))
101 Features.push_back(x: "+reserve-x3");
102 if (Args.hasArg(options::OPT_ffixed_x4))
103 Features.push_back(x: "+reserve-x4");
104 if (Args.hasArg(options::OPT_ffixed_x5))
105 Features.push_back(x: "+reserve-x5");
106 if (Args.hasArg(options::OPT_ffixed_x6))
107 Features.push_back(x: "+reserve-x6");
108 if (Args.hasArg(options::OPT_ffixed_x7))
109 Features.push_back(x: "+reserve-x7");
110 if (Args.hasArg(options::OPT_ffixed_x8))
111 Features.push_back(x: "+reserve-x8");
112 if (Args.hasArg(options::OPT_ffixed_x9))
113 Features.push_back(x: "+reserve-x9");
114 if (Args.hasArg(options::OPT_ffixed_x10))
115 Features.push_back(x: "+reserve-x10");
116 if (Args.hasArg(options::OPT_ffixed_x11))
117 Features.push_back(x: "+reserve-x11");
118 if (Args.hasArg(options::OPT_ffixed_x12))
119 Features.push_back(x: "+reserve-x12");
120 if (Args.hasArg(options::OPT_ffixed_x13))
121 Features.push_back(x: "+reserve-x13");
122 if (Args.hasArg(options::OPT_ffixed_x14))
123 Features.push_back(x: "+reserve-x14");
124 if (Args.hasArg(options::OPT_ffixed_x15))
125 Features.push_back(x: "+reserve-x15");
126 if (Args.hasArg(options::OPT_ffixed_x16))
127 Features.push_back(x: "+reserve-x16");
128 if (Args.hasArg(options::OPT_ffixed_x17))
129 Features.push_back(x: "+reserve-x17");
130 if (Args.hasArg(options::OPT_ffixed_x18))
131 Features.push_back(x: "+reserve-x18");
132 if (Args.hasArg(options::OPT_ffixed_x19))
133 Features.push_back(x: "+reserve-x19");
134 if (Args.hasArg(options::OPT_ffixed_x20))
135 Features.push_back(x: "+reserve-x20");
136 if (Args.hasArg(options::OPT_ffixed_x21))
137 Features.push_back(x: "+reserve-x21");
138 if (Args.hasArg(options::OPT_ffixed_x22))
139 Features.push_back(x: "+reserve-x22");
140 if (Args.hasArg(options::OPT_ffixed_x23))
141 Features.push_back(x: "+reserve-x23");
142 if (Args.hasArg(options::OPT_ffixed_x24))
143 Features.push_back(x: "+reserve-x24");
144 if (Args.hasArg(options::OPT_ffixed_x25))
145 Features.push_back(x: "+reserve-x25");
146 if (Args.hasArg(options::OPT_ffixed_x26))
147 Features.push_back(x: "+reserve-x26");
148 if (Args.hasArg(options::OPT_ffixed_x27))
149 Features.push_back(x: "+reserve-x27");
150 if (Args.hasArg(options::OPT_ffixed_x28))
151 Features.push_back(x: "+reserve-x28");
152 if (Args.hasArg(options::OPT_ffixed_x29))
153 Features.push_back(x: "+reserve-x29");
154 if (Args.hasArg(options::OPT_ffixed_x30))
155 Features.push_back(x: "+reserve-x30");
156 if (Args.hasArg(options::OPT_ffixed_x31))
157 Features.push_back(x: "+reserve-x31");
158
159 // -mrelax is default, unless -mno-relax is specified.
160 if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) {
161 Features.push_back(x: "+relax");
162 // -gsplit-dwarf -mrelax requires DW_AT_high_pc/DW_AT_ranges/... indexing
163 // into .debug_addr, which is currently not implemented.
164 Arg *A;
165 if (getDebugFissionKind(D, Args, Arg&: A) != DwarfFissionKind::None)
166 D.Diag(clang::diag::DiagID: err_drv_riscv_unsupported_with_linker_relaxation)
167 << A->getAsString(Args);
168 } else {
169 Features.push_back(x: "-relax");
170 }
171
172 // Android requires fast unaligned access on RISCV64.
173 if (Triple.isAndroid()) {
174 Features.push_back(x: "+unaligned-scalar-mem");
175 Features.push_back(x: "+unaligned-vector-mem");
176 }
177
178 // -mstrict-align is default, unless -mno-strict-align is specified.
179 AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
180 options::OPT_mstrict_align, "unaligned-scalar-mem");
181 AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
182 options::OPT_mstrict_align, "unaligned-vector-mem");
183
184 // Now add any that the user explicitly requested on the command line,
185 // which may override the defaults.
186 handleTargetFeaturesGroup(D, Triple, Args, Features,
187 options::OPT_m_riscv_Features_Group);
188}
189
190StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
191 assert(Triple.isRISCV() && "Unexpected triple");
192
193 // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
194 // configured using `--with-abi=`, then the logic for the default choice is
195 // defined in config.gcc. This function is based on the logic in GCC 9.2.0.
196 //
197 // The logic used in GCC 9.2.0 is the following, in order:
198 // 1. Explicit choices using `--with-abi=`
199 // 2. A default based on `--with-arch=`, if provided
200 // 3. A default based on the target triple's arch
201 //
202 // The logic in config.gcc is a little circular but it is not inconsistent.
203 //
204 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
205 // and `-mabi=` respectively instead.
206 //
207 // In order to make chosing logic more clear, Clang uses the following logic,
208 // in order:
209 // 1. Explicit choices using `-mabi=`
210 // 2. A default based on the architecture as determined by getRISCVArch
211 // 3. Choose a default based on the triple
212
213 // 1. If `-mabi=` is specified, use it.
214 if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
215 return A->getValue();
216
217 // 2. Choose a default based on the target architecture.
218 //
219 // rv32g | rv32*d -> ilp32d
220 // rv32e -> ilp32e
221 // rv32* -> ilp32
222 // rv64g | rv64*d -> lp64d
223 // rv64e -> lp64e
224 // rv64* -> lp64
225 StringRef Arch = getRISCVArch(Args, Triple);
226
227 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
228 Arch, /* EnableExperimentalExtension */ true);
229 // Ignore parsing error, just go 3rd step.
230 if (!llvm::errorToBool(Err: ParseResult.takeError()))
231 return (*ParseResult)->computeDefaultABI();
232
233 // 3. Choose a default based on the triple
234 //
235 // We deviate from GCC's defaults here:
236 // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
237 // - On all other OSs we use the double floating point calling convention.
238 if (Triple.isRISCV32()) {
239 if (Triple.getOS() == llvm::Triple::UnknownOS)
240 return "ilp32";
241 else
242 return "ilp32d";
243 } else {
244 if (Triple.getOS() == llvm::Triple::UnknownOS)
245 return "lp64";
246 else
247 return "lp64d";
248 }
249}
250
251StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
252 const llvm::Triple &Triple) {
253 assert(Triple.isRISCV() && "Unexpected triple");
254
255 // GCC's logic around choosing a default `-march=` is complex. If GCC is not
256 // configured using `--with-arch=`, then the logic for the default choice is
257 // defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
258 // deviate from GCC's default on additional `-mcpu` option (GCC does not
259 // support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
260 // nor `-mabi` is specified.
261 //
262 // The logic used in GCC 9.2.0 is the following, in order:
263 // 1. Explicit choices using `--with-arch=`
264 // 2. A default based on `--with-abi=`, if provided
265 // 3. A default based on the target triple's arch
266 //
267 // The logic in config.gcc is a little circular but it is not inconsistent.
268 //
269 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
270 // and `-mabi=` respectively instead.
271 //
272 // Clang uses the following logic, in order:
273 // 1. Explicit choices using `-march=`
274 // 2. Based on `-mcpu` if the target CPU has a default ISA string
275 // 3. A default based on `-mabi`, if provided
276 // 4. A default based on the target triple's arch
277 //
278 // Clang does not yet support MULTILIB_REUSE, so we use `rv{XLEN}imafdc`
279 // instead of `rv{XLEN}gc` though they are (currently) equivalent.
280
281 // 1. If `-march=` is specified, use it.
282 if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
283 return A->getValue();
284
285 // 2. Get march (isa string) based on `-mcpu=`
286 if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
287 StringRef CPU = A->getValue();
288 if (CPU == "native")
289 CPU = llvm::sys::getHostCPUName();
290 StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
291 // Bypass if target cpu's default march is empty.
292 if (MArch != "")
293 return MArch;
294 }
295
296 // 3. Choose a default based on `-mabi=`
297 //
298 // ilp32e -> rv32e
299 // lp64e -> rv64e
300 // ilp32 | ilp32f | ilp32d -> rv32imafdc
301 // lp64 | lp64f | lp64d -> rv64imafdc
302 if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
303 StringRef MABI = A->getValue();
304
305 if (MABI.equals_insensitive(RHS: "ilp32e"))
306 return "rv32e";
307 else if (MABI.equals_insensitive(RHS: "lp64e"))
308 return "rv64e";
309 else if (MABI.starts_with_insensitive(Prefix: "ilp32"))
310 return "rv32imafdc";
311 else if (MABI.starts_with_insensitive(Prefix: "lp64")) {
312 if (Triple.isAndroid())
313 return "rv64imafdcv_zba_zbb_zbs";
314
315 return "rv64imafdc";
316 }
317 }
318
319 // 4. Choose a default based on the triple
320 //
321 // We deviate from GCC's defaults here:
322 // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
323 // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
324 if (Triple.isRISCV32()) {
325 if (Triple.getOS() == llvm::Triple::UnknownOS)
326 return "rv32imac";
327 else
328 return "rv32imafdc";
329 } else {
330 if (Triple.getOS() == llvm::Triple::UnknownOS)
331 return "rv64imac";
332 else if (Triple.isAndroid())
333 return "rv64imafdcv_zba_zbb_zbs";
334 else
335 return "rv64imafdc";
336 }
337}
338
339std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
340 const llvm::Triple &Triple) {
341 std::string CPU;
342 // If we have -mcpu, use that.
343 if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
344 CPU = A->getValue();
345
346 // Handle CPU name is 'native'.
347 if (CPU == "native")
348 CPU = llvm::sys::getHostCPUName();
349
350 if (!CPU.empty())
351 return CPU;
352
353 return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
354}
355

source code of clang/lib/Driver/ToolChains/Arch/RISCV.cpp