| 1 | //===-- aeabi_cdcmp.S - EABI cdcmp* implementation ------------------------===// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | |
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| 9 | #include "../assembly.h" |
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| 10 | |
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| 11 | #define APSR_Z (1 << 30) |
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| 12 | #define APSR_C (1 << 29) |
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| 13 | |
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| 14 | // void __aeabi_cdcmpeq(double a, double b) { |
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| 15 | // if (isnan(a) || isnan(b)) { |
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| 16 | // Z = 0; C = 1; |
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| 17 | // } else { |
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| 18 | // __aeabi_cdcmple(a, b); |
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| 19 | // } |
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| 20 | // } |
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| 21 | |
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| 22 | .syntax unified |
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| 23 | .p2align 2 |
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| 24 | DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq) |
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| 25 | push {r0-r3, lr} |
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| 26 | bl __aeabi_cdcmpeq_check_nan |
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| 27 | cmp r0, #1 |
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| 28 | #if defined(USE_THUMB_1) |
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| 29 | beq 1f |
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| 30 | // NaN has been ruled out, so __aeabi_cdcmple can't trap |
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| 31 | mov r0, sp |
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| 32 | ldm r0, {r0-r3} |
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| 33 | bl __aeabi_cdcmple |
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| 34 | pop {r0-r3, pc} |
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| 35 | 1: |
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| 36 | // Z = 0, C = 1 |
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| 37 | movs r0, #0xF |
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| 38 | lsls r0, r0, #31 |
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| 39 | pop {r0-r3, pc} |
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| 40 | #else |
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| 41 | pop {r0-r3, lr} |
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| 42 | |
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| 43 | // NaN has been ruled out, so __aeabi_cdcmple can't trap |
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| 44 | // Use "it ne" + unconditional branch to guarantee a supported relocation if |
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| 45 | // __aeabi_cdcmple is in a different section for some builds. |
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| 46 | IT(ne) |
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| 47 | bne __aeabi_cdcmple |
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| 48 | |
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| 49 | #if defined(USE_THUMB_2) |
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| 50 | mov ip, #APSR_C |
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| 51 | msr APSR_nzcvq, ip |
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| 52 | #else |
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| 53 | msr APSR_nzcvq, #APSR_C |
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| 54 | #endif |
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| 55 | JMP(lr) |
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| 56 | #endif |
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| 57 | END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq) |
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| 58 | |
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| 59 | |
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| 60 | // void __aeabi_cdcmple(double a, double b) { |
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| 61 | // if (__aeabi_dcmplt(a, b)) { |
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| 62 | // Z = 0; C = 0; |
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| 63 | // } else if (__aeabi_dcmpeq(a, b)) { |
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| 64 | // Z = 1; C = 1; |
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| 65 | // } else { |
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| 66 | // Z = 0; C = 1; |
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| 67 | // } |
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| 68 | // } |
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| 69 | |
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| 70 | .syntax unified |
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| 71 | .p2align 2 |
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| 72 | DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple) |
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| 73 | // Per the RTABI, this function must preserve r0-r11. |
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| 74 | // Save lr in the same instruction for compactness |
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| 75 | push {r0-r3, lr} |
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| 76 | |
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| 77 | bl __aeabi_dcmplt |
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| 78 | cmp r0, #1 |
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| 79 | #if defined(USE_THUMB_1) |
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| 80 | bne 1f |
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| 81 | // Z = 0, C = 0 |
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| 82 | movs r0, #1 |
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| 83 | lsls r0, r0, #1 |
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| 84 | pop {r0-r3, pc} |
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| 85 | 1: |
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| 86 | mov r0, sp |
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| 87 | ldm r0, {r0-r3} |
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| 88 | bl __aeabi_dcmpeq |
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| 89 | cmp r0, #1 |
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| 90 | bne 2f |
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| 91 | // Z = 1, C = 1 |
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| 92 | movs r0, #2 |
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| 93 | lsls r0, r0, #31 |
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| 94 | pop {r0-r3, pc} |
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| 95 | 2: |
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| 96 | // Z = 0, C = 1 |
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| 97 | movs r0, #0xF |
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| 98 | lsls r0, r0, #31 |
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| 99 | pop {r0-r3, pc} |
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| 100 | #else |
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| 101 | ITT(eq) |
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| 102 | moveq ip, #0 |
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| 103 | beq 1f |
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| 104 | |
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| 105 | ldm sp, {r0-r3} |
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| 106 | bl __aeabi_dcmpeq |
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| 107 | cmp r0, #1 |
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| 108 | ITE(eq) |
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| 109 | moveq ip, #(APSR_C | APSR_Z) |
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| 110 | movne ip, #(APSR_C) |
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| 111 | |
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| 112 | 1: |
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| 113 | msr APSR_nzcvq, ip |
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| 114 | pop {r0-r3} |
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| 115 | POP_PC() |
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| 116 | #endif |
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| 117 | END_COMPILERRT_FUNCTION(__aeabi_cdcmple) |
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| 118 | |
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| 119 | // int __aeabi_cdrcmple(double a, double b) { |
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| 120 | // return __aeabi_cdcmple(b, a); |
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| 121 | // } |
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| 122 | |
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| 123 | .syntax unified |
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| 124 | .p2align 2 |
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| 125 | DEFINE_COMPILERRT_FUNCTION(__aeabi_cdrcmple) |
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| 126 | // Swap r0 and r2 |
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| 127 | mov ip, r0 |
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| 128 | mov r0, r2 |
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| 129 | mov r2, ip |
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| 130 | |
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| 131 | // Swap r1 and r3 |
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| 132 | mov ip, r1 |
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| 133 | mov r1, r3 |
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| 134 | mov r3, ip |
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| 135 | |
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| 136 | b __aeabi_cdcmple |
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| 137 | END_COMPILERRT_FUNCTION(__aeabi_cdrcmple) |
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| 138 | |
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| 139 | NO_EXEC_STACK_DIRECTIVE |
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| 140 | |
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| 141 | |
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