1//===-- save.S - save up to 12 callee-saved registers ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Multiple entry points depending on number of registers to save
10//
11//===----------------------------------------------------------------------===//
12
13// The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
14// is the minimum grouping which will maintain the required 16-byte stack
15// alignment.
16
17 .text
18
19#if __riscv_xlen == 32
20
21#ifndef __riscv_abi_rve
22
23 .globl __riscv_save_12
24 .type __riscv_save_12,@function
25__riscv_save_12:
26 addi sp, sp, -64
27 mv t1, zero
28 sw s11, 12(sp)
29 j .Lriscv_save_11_8
30
31 .globl __riscv_save_11
32 .type __riscv_save_11,@function
33 .globl __riscv_save_10
34 .type __riscv_save_10,@function
35 .globl __riscv_save_9
36 .type __riscv_save_9,@function
37 .globl __riscv_save_8
38 .type __riscv_save_8,@function
39__riscv_save_11:
40__riscv_save_10:
41__riscv_save_9:
42__riscv_save_8:
43 addi sp, sp, -64
44 li t1, 16
45.Lriscv_save_11_8:
46 sw s10, 16(sp)
47 sw s9, 20(sp)
48 sw s8, 24(sp)
49 sw s7, 28(sp)
50 j .Lriscv_save_7_4
51
52 .globl __riscv_save_7
53 .type __riscv_save_7,@function
54 .globl __riscv_save_6
55 .type __riscv_save_6,@function
56 .globl __riscv_save_5
57 .type __riscv_save_5,@function
58 .globl __riscv_save_4
59 .type __riscv_save_4,@function
60__riscv_save_7:
61__riscv_save_6:
62__riscv_save_5:
63__riscv_save_4:
64 addi sp, sp, -64
65 li t1, 32
66.Lriscv_save_7_4:
67 sw s6, 32(sp)
68 sw s5, 36(sp)
69 sw s4, 40(sp)
70 sw s3, 44(sp)
71 sw s2, 48(sp)
72 sw s1, 52(sp)
73 sw s0, 56(sp)
74 sw ra, 60(sp)
75 add sp, sp, t1
76 jr t0
77
78 .globl __riscv_save_3
79 .type __riscv_save_3,@function
80 .globl __riscv_save_2
81 .type __riscv_save_2,@function
82 .globl __riscv_save_1
83 .type __riscv_save_1,@function
84 .globl __riscv_save_0
85 .type __riscv_save_0,@function
86__riscv_save_3:
87__riscv_save_2:
88__riscv_save_1:
89__riscv_save_0:
90 addi sp, sp, -16
91 sw s2, 0(sp)
92 sw s1, 4(sp)
93 sw s0, 8(sp)
94 sw ra, 12(sp)
95 jr t0
96
97#else
98
99 .globl __riscv_save_2
100 .type __riscv_save_2,@function
101__riscv_save_2:
102 addi sp, sp, -12
103 sw s1, 0(sp)
104 sw s0, 4(sp)
105 sw ra, 8(sp)
106 jr t0
107
108 .globl __riscv_save_1
109 .type __riscv_save_1,@function
110__riscv_save_1:
111 addi sp, sp, -8
112 sw s0, 0(sp)
113 sw ra, 4(sp)
114 jr t0
115
116 .globl __riscv_save_0
117 .type __riscv_save_0,@function
118__riscv_save_0:
119 addi sp, sp, -4
120 sw ra, 0(sp)
121 jr t0
122
123#endif
124
125#elif __riscv_xlen == 64
126
127#ifndef __riscv_abi_rve
128
129 .globl __riscv_save_12
130 .type __riscv_save_12,@function
131__riscv_save_12:
132 addi sp, sp, -112
133 mv t1, zero
134 sd s11, 8(sp)
135 j .Lriscv_save_11_10
136
137 .globl __riscv_save_11
138 .type __riscv_save_11,@function
139 .globl __riscv_save_10
140 .type __riscv_save_10,@function
141__riscv_save_11:
142__riscv_save_10:
143 addi sp, sp, -112
144 li t1, 16
145.Lriscv_save_11_10:
146 sd s10, 16(sp)
147 sd s9, 24(sp)
148 j .Lriscv_save_9_8
149
150 .globl __riscv_save_9
151 .type __riscv_save_9,@function
152 .globl __riscv_save_8
153 .type __riscv_save_8,@function
154__riscv_save_9:
155__riscv_save_8:
156 addi sp, sp, -112
157 li t1, 32
158.Lriscv_save_9_8:
159 sd s8, 32(sp)
160 sd s7, 40(sp)
161 j .Lriscv_save_7_6
162
163 .globl __riscv_save_7
164 .type __riscv_save_7,@function
165 .globl __riscv_save_6
166 .type __riscv_save_6,@function
167__riscv_save_7:
168__riscv_save_6:
169 addi sp, sp, -112
170 li t1, 48
171.Lriscv_save_7_6:
172 sd s6, 48(sp)
173 sd s5, 56(sp)
174 j .Lriscv_save_5_4
175
176 .globl __riscv_save_5
177 .type __riscv_save_5,@function
178 .globl __riscv_save_4
179 .type __riscv_save_4,@function
180__riscv_save_5:
181__riscv_save_4:
182 addi sp, sp, -112
183 li t1, 64
184.Lriscv_save_5_4:
185 sd s4, 64(sp)
186 sd s3, 72(sp)
187 j .Lriscv_save_3_2
188
189 .globl __riscv_save_3
190 .type __riscv_save_3,@function
191 .globl __riscv_save_2
192 .type __riscv_save_2,@function
193__riscv_save_3:
194__riscv_save_2:
195 addi sp, sp, -112
196 li t1, 80
197.Lriscv_save_3_2:
198 sd s2, 80(sp)
199 sd s1, 88(sp)
200 sd s0, 96(sp)
201 sd ra, 104(sp)
202 add sp, sp, t1
203 jr t0
204
205 .globl __riscv_save_1
206 .type __riscv_save_1,@function
207 .globl __riscv_save_0
208 .type __riscv_save_0,@function
209__riscv_save_1:
210__riscv_save_0:
211 addi sp, sp, -16
212 sd s0, 0(sp)
213 sd ra, 8(sp)
214 jr t0
215
216#else
217
218 .globl __riscv_save_2
219 .type __riscv_save_2,@function
220__riscv_save_2:
221 addi sp, sp, -24
222 sw s1, 0(sp)
223 sw s0, 8(sp)
224 sw ra, 16(sp)
225 jr t0
226
227 .globl __riscv_save_1
228 .type __riscv_save_1,@function
229__riscv_save_1:
230 addi sp, sp, -16
231 sw s0, 0(sp)
232 sw ra, 8(sp)
233 jr t0
234
235 .globl __riscv_save_0
236 .type __riscv_save_0,@function
237__riscv_save_0:
238 addi sp, sp, -8
239 sw ra, 0(sp)
240 jr t0
241
242#endif
243
244#else
245# error "xlen must be 32 or 64 for save-restore implementation
246#endif
247

source code of compiler-rt/lib/builtins/riscv/save.S