1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Performance events:
4 *
5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 *
9 * Data type definitions, declarations, prototypes.
10 *
11 * Started by: Thomas Gleixner and Ingo Molnar
12 *
13 * For licencing details see kernel-base/COPYING
14 */
15#ifndef _LINUX_PERF_EVENT_H
16#define _LINUX_PERF_EVENT_H
17
18#include <linux/types.h>
19#include <linux/ioctl.h>
20#include <asm/byteorder.h>
21
22/*
23 * User-space ABI bits:
24 */
25
26/*
27 * attr.type
28 */
29enum perf_type_id {
30 PERF_TYPE_HARDWARE = 0,
31 PERF_TYPE_SOFTWARE = 1,
32 PERF_TYPE_TRACEPOINT = 2,
33 PERF_TYPE_HW_CACHE = 3,
34 PERF_TYPE_RAW = 4,
35 PERF_TYPE_BREAKPOINT = 5,
36
37 PERF_TYPE_MAX, /* non-ABI */
38};
39
40/*
41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA
43 * AA: hardware event ID
44 * EEEEEEEE: PMU type ID
45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB
46 * BB: hardware cache ID
47 * CC: hardware cache op ID
48 * DD: hardware cache op result ID
49 * EEEEEEEE: PMU type ID
50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied.
51 */
52#define PERF_PMU_TYPE_SHIFT 32
53#define PERF_HW_EVENT_MASK 0xffffffff
54
55/*
56 * Generalized performance event event_id types, used by the
57 * attr.event_id parameter of the sys_perf_event_open()
58 * syscall:
59 */
60enum perf_hw_id {
61 /*
62 * Common hardware events, generalized by the kernel:
63 */
64 PERF_COUNT_HW_CPU_CYCLES = 0,
65 PERF_COUNT_HW_INSTRUCTIONS = 1,
66 PERF_COUNT_HW_CACHE_REFERENCES = 2,
67 PERF_COUNT_HW_CACHE_MISSES = 3,
68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
69 PERF_COUNT_HW_BRANCH_MISSES = 5,
70 PERF_COUNT_HW_BUS_CYCLES = 6,
71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
73 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
74
75 PERF_COUNT_HW_MAX, /* non-ABI */
76};
77
78/*
79 * Generalized hardware cache events:
80 *
81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
82 * { read, write, prefetch } x
83 * { accesses, misses }
84 */
85enum perf_hw_cache_id {
86 PERF_COUNT_HW_CACHE_L1D = 0,
87 PERF_COUNT_HW_CACHE_L1I = 1,
88 PERF_COUNT_HW_CACHE_LL = 2,
89 PERF_COUNT_HW_CACHE_DTLB = 3,
90 PERF_COUNT_HW_CACHE_ITLB = 4,
91 PERF_COUNT_HW_CACHE_BPU = 5,
92 PERF_COUNT_HW_CACHE_NODE = 6,
93
94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
95};
96
97enum perf_hw_cache_op_id {
98 PERF_COUNT_HW_CACHE_OP_READ = 0,
99 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
101
102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
103};
104
105enum perf_hw_cache_op_result_id {
106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
108
109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
110};
111
112/*
113 * Special "software" events provided by the kernel, even if the hardware
114 * does not support performance events. These events measure various
115 * physical and sw events of the kernel (and allow the profiling of them as
116 * well):
117 */
118enum perf_sw_ids {
119 PERF_COUNT_SW_CPU_CLOCK = 0,
120 PERF_COUNT_SW_TASK_CLOCK = 1,
121 PERF_COUNT_SW_PAGE_FAULTS = 2,
122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
123 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
127 PERF_COUNT_SW_EMULATION_FAULTS = 8,
128 PERF_COUNT_SW_DUMMY = 9,
129 PERF_COUNT_SW_BPF_OUTPUT = 10,
130 PERF_COUNT_SW_CGROUP_SWITCHES = 11,
131
132 PERF_COUNT_SW_MAX, /* non-ABI */
133};
134
135/*
136 * Bits that can be set in attr.sample_type to request information
137 * in the overflow packets.
138 */
139enum perf_event_sample_format {
140 PERF_SAMPLE_IP = 1U << 0,
141 PERF_SAMPLE_TID = 1U << 1,
142 PERF_SAMPLE_TIME = 1U << 2,
143 PERF_SAMPLE_ADDR = 1U << 3,
144 PERF_SAMPLE_READ = 1U << 4,
145 PERF_SAMPLE_CALLCHAIN = 1U << 5,
146 PERF_SAMPLE_ID = 1U << 6,
147 PERF_SAMPLE_CPU = 1U << 7,
148 PERF_SAMPLE_PERIOD = 1U << 8,
149 PERF_SAMPLE_STREAM_ID = 1U << 9,
150 PERF_SAMPLE_RAW = 1U << 10,
151 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
152 PERF_SAMPLE_REGS_USER = 1U << 12,
153 PERF_SAMPLE_STACK_USER = 1U << 13,
154 PERF_SAMPLE_WEIGHT = 1U << 14,
155 PERF_SAMPLE_DATA_SRC = 1U << 15,
156 PERF_SAMPLE_IDENTIFIER = 1U << 16,
157 PERF_SAMPLE_TRANSACTION = 1U << 17,
158 PERF_SAMPLE_REGS_INTR = 1U << 18,
159 PERF_SAMPLE_PHYS_ADDR = 1U << 19,
160 PERF_SAMPLE_AUX = 1U << 20,
161 PERF_SAMPLE_CGROUP = 1U << 21,
162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22,
163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23,
164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24,
165
166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */
167
168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */
169};
170
171#define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT)
172/*
173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
174 *
175 * If the user does not pass priv level information via branch_sample_type,
176 * the kernel uses the event's priv level. Branch and event priv levels do
177 * not have to match. Branch priv level is checked for permissions.
178 *
179 * The branch types can be combined, however BRANCH_ANY covers all types
180 * of branches and therefore it supersedes all the other types.
181 */
182enum perf_branch_sample_type_shift {
183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
186
187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
195
196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
199
200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
202
203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */
204
205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */
206
207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
208};
209
210enum perf_branch_sample_type {
211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
214
215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
223
224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
227
228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
230
231 PERF_SAMPLE_BRANCH_TYPE_SAVE =
232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
233
234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT,
235
236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
237};
238
239/*
240 * Common flow change classification
241 */
242enum {
243 PERF_BR_UNKNOWN = 0, /* unknown */
244 PERF_BR_COND = 1, /* conditional */
245 PERF_BR_UNCOND = 2, /* unconditional */
246 PERF_BR_IND = 3, /* indirect */
247 PERF_BR_CALL = 4, /* function call */
248 PERF_BR_IND_CALL = 5, /* indirect function call */
249 PERF_BR_RET = 6, /* function return */
250 PERF_BR_SYSCALL = 7, /* syscall */
251 PERF_BR_SYSRET = 8, /* syscall return */
252 PERF_BR_COND_CALL = 9, /* conditional function call */
253 PERF_BR_COND_RET = 10, /* conditional function return */
254 PERF_BR_MAX,
255};
256
257#define PERF_SAMPLE_BRANCH_PLM_ALL \
258 (PERF_SAMPLE_BRANCH_USER|\
259 PERF_SAMPLE_BRANCH_KERNEL|\
260 PERF_SAMPLE_BRANCH_HV)
261
262/*
263 * Values to determine ABI of the registers dump.
264 */
265enum perf_sample_regs_abi {
266 PERF_SAMPLE_REGS_ABI_NONE = 0,
267 PERF_SAMPLE_REGS_ABI_32 = 1,
268 PERF_SAMPLE_REGS_ABI_64 = 2,
269};
270
271/*
272 * Values for the memory transaction event qualifier, mostly for
273 * abort events. Multiple bits can be set.
274 */
275enum {
276 PERF_TXN_ELISION = (1 << 0), /* From elision */
277 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
278 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
279 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
280 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
281 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
282 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
283 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
284
285 PERF_TXN_MAX = (1 << 8), /* non-ABI */
286
287 /* bits 32..63 are reserved for the abort code */
288
289 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
290 PERF_TXN_ABORT_SHIFT = 32,
291};
292
293/*
294 * The format of the data returned by read() on a perf event fd,
295 * as specified by attr.read_format:
296 *
297 * struct read_format {
298 * { u64 value;
299 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
300 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
301 * { u64 id; } && PERF_FORMAT_ID
302 * { u64 lost; } && PERF_FORMAT_LOST
303 * } && !PERF_FORMAT_GROUP
304 *
305 * { u64 nr;
306 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
307 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
308 * { u64 value;
309 * { u64 id; } && PERF_FORMAT_ID
310 * { u64 lost; } && PERF_FORMAT_LOST
311 * } cntr[nr];
312 * } && PERF_FORMAT_GROUP
313 * };
314 */
315enum perf_event_read_format {
316 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
317 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
318 PERF_FORMAT_ID = 1U << 2,
319 PERF_FORMAT_GROUP = 1U << 3,
320 PERF_FORMAT_LOST = 1U << 4,
321
322 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */
323};
324
325#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
326#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
327#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
328#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
329 /* add: sample_stack_user */
330#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
331#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
332#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */
333#define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */
334
335/*
336 * Hardware event_id to monitor via a performance monitoring event:
337 *
338 * @sample_max_stack: Max number of frame pointers in a callchain,
339 * should be < /proc/sys/kernel/perf_event_max_stack
340 */
341struct perf_event_attr {
342
343 /*
344 * Major type: hardware/software/tracepoint/etc.
345 */
346 __u32 type;
347
348 /*
349 * Size of the attr structure, for fwd/bwd compat.
350 */
351 __u32 size;
352
353 /*
354 * Type specific configuration information.
355 */
356 __u64 config;
357
358 union {
359 __u64 sample_period;
360 __u64 sample_freq;
361 };
362
363 __u64 sample_type;
364 __u64 read_format;
365
366 __u64 disabled : 1, /* off by default */
367 inherit : 1, /* children inherit it */
368 pinned : 1, /* must always be on PMU */
369 exclusive : 1, /* only group on PMU */
370 exclude_user : 1, /* don't count user */
371 exclude_kernel : 1, /* ditto kernel */
372 exclude_hv : 1, /* ditto hypervisor */
373 exclude_idle : 1, /* don't count when idle */
374 mmap : 1, /* include mmap data */
375 comm : 1, /* include comm data */
376 freq : 1, /* use freq, not period */
377 inherit_stat : 1, /* per task counts */
378 enable_on_exec : 1, /* next exec enables */
379 task : 1, /* trace fork/exit */
380 watermark : 1, /* wakeup_watermark */
381 /*
382 * precise_ip:
383 *
384 * 0 - SAMPLE_IP can have arbitrary skid
385 * 1 - SAMPLE_IP must have constant skid
386 * 2 - SAMPLE_IP requested to have 0 skid
387 * 3 - SAMPLE_IP must have 0 skid
388 *
389 * See also PERF_RECORD_MISC_EXACT_IP
390 */
391 precise_ip : 2, /* skid constraint */
392 mmap_data : 1, /* non-exec mmap data */
393 sample_id_all : 1, /* sample_type all events */
394
395 exclude_host : 1, /* don't count in host */
396 exclude_guest : 1, /* don't count in guest */
397
398 exclude_callchain_kernel : 1, /* exclude kernel callchains */
399 exclude_callchain_user : 1, /* exclude user callchains */
400 mmap2 : 1, /* include mmap with inode data */
401 comm_exec : 1, /* flag comm events that are due to an exec */
402 use_clockid : 1, /* use @clockid for time fields */
403 context_switch : 1, /* context switch data */
404 write_backward : 1, /* Write ring buffer from end to beginning */
405 namespaces : 1, /* include namespaces data */
406 ksymbol : 1, /* include ksymbol events */
407 bpf_event : 1, /* include bpf events */
408 aux_output : 1, /* generate AUX records instead of events */
409 cgroup : 1, /* include cgroup events */
410 text_poke : 1, /* include text poke events */
411 build_id : 1, /* use build id in mmap2 events */
412 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */
413 remove_on_exec : 1, /* event is removed from task on exec */
414 sigtrap : 1, /* send synchronous SIGTRAP on event */
415 __reserved_1 : 26;
416
417 union {
418 __u32 wakeup_events; /* wakeup every n events */
419 __u32 wakeup_watermark; /* bytes before wakeup */
420 };
421
422 __u32 bp_type;
423 union {
424 __u64 bp_addr;
425 __u64 kprobe_func; /* for perf_kprobe */
426 __u64 uprobe_path; /* for perf_uprobe */
427 __u64 config1; /* extension of config */
428 };
429 union {
430 __u64 bp_len;
431 __u64 kprobe_addr; /* when kprobe_func == NULL */
432 __u64 probe_offset; /* for perf_[k,u]probe */
433 __u64 config2; /* extension of config1 */
434 };
435 __u64 branch_sample_type; /* enum perf_branch_sample_type */
436
437 /*
438 * Defines set of user regs to dump on samples.
439 * See asm/perf_regs.h for details.
440 */
441 __u64 sample_regs_user;
442
443 /*
444 * Defines size of the user stack to dump on samples.
445 */
446 __u32 sample_stack_user;
447
448 __s32 clockid;
449 /*
450 * Defines set of regs to dump for each sample
451 * state captured on:
452 * - precise = 0: PMU interrupt
453 * - precise > 0: sampled instruction
454 *
455 * See asm/perf_regs.h for details.
456 */
457 __u64 sample_regs_intr;
458
459 /*
460 * Wakeup watermark for AUX area
461 */
462 __u32 aux_watermark;
463 __u16 sample_max_stack;
464 __u16 __reserved_2;
465 __u32 aux_sample_size;
466 __u32 __reserved_3;
467
468 /*
469 * User provided data if sigtrap=1, passed back to user via
470 * siginfo_t::si_perf_data, e.g. to permit user to identify the event.
471 */
472 __u64 sig_data;
473};
474
475/*
476 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command
477 * to query bpf programs attached to the same perf tracepoint
478 * as the given perf event.
479 */
480struct perf_event_query_bpf {
481 /*
482 * The below ids array length
483 */
484 __u32 ids_len;
485 /*
486 * Set by the kernel to indicate the number of
487 * available programs
488 */
489 __u32 prog_cnt;
490 /*
491 * User provided buffer to store program ids
492 */
493 __u32 ids[0];
494};
495
496/*
497 * Ioctls that can be done on a perf event fd:
498 */
499#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
500#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
501#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
502#define PERF_EVENT_IOC_RESET _IO ('$', 3)
503#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
504#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
505#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
506#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
507#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
508#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
509#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *)
510#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *)
511
512enum perf_event_ioc_flags {
513 PERF_IOC_FLAG_GROUP = 1U << 0,
514};
515
516/*
517 * Structure of the page that can be mapped via mmap
518 */
519struct perf_event_mmap_page {
520 __u32 version; /* version number of this structure */
521 __u32 compat_version; /* lowest version this is compat with */
522
523 /*
524 * Bits needed to read the hw events in user-space.
525 *
526 * u32 seq, time_mult, time_shift, index, width;
527 * u64 count, enabled, running;
528 * u64 cyc, time_offset;
529 * s64 pmc = 0;
530 *
531 * do {
532 * seq = pc->lock;
533 * barrier()
534 *
535 * enabled = pc->time_enabled;
536 * running = pc->time_running;
537 *
538 * if (pc->cap_usr_time && enabled != running) {
539 * cyc = rdtsc();
540 * time_offset = pc->time_offset;
541 * time_mult = pc->time_mult;
542 * time_shift = pc->time_shift;
543 * }
544 *
545 * index = pc->index;
546 * count = pc->offset;
547 * if (pc->cap_user_rdpmc && index) {
548 * width = pc->pmc_width;
549 * pmc = rdpmc(index - 1);
550 * }
551 *
552 * barrier();
553 * } while (pc->lock != seq);
554 *
555 * NOTE: for obvious reason this only works on self-monitoring
556 * processes.
557 */
558 __u32 lock; /* seqlock for synchronization */
559 __u32 index; /* hardware event identifier */
560 __s64 offset; /* add to hardware event value */
561 __u64 time_enabled; /* time event active */
562 __u64 time_running; /* time event on cpu */
563 union {
564 __u64 capabilities;
565 struct {
566 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
567 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
568
569 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
570 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */
571 cap_user_time_zero : 1, /* The time_zero field is used */
572 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */
573 cap_____res : 58;
574 };
575 };
576
577 /*
578 * If cap_user_rdpmc this field provides the bit-width of the value
579 * read using the rdpmc() or equivalent instruction. This can be used
580 * to sign extend the result like:
581 *
582 * pmc <<= 64 - width;
583 * pmc >>= 64 - width; // signed shift right
584 * count += pmc;
585 */
586 __u16 pmc_width;
587
588 /*
589 * If cap_usr_time the below fields can be used to compute the time
590 * delta since time_enabled (in ns) using rdtsc or similar.
591 *
592 * u64 quot, rem;
593 * u64 delta;
594 *
595 * quot = (cyc >> time_shift);
596 * rem = cyc & (((u64)1 << time_shift) - 1);
597 * delta = time_offset + quot * time_mult +
598 * ((rem * time_mult) >> time_shift);
599 *
600 * Where time_offset,time_mult,time_shift and cyc are read in the
601 * seqcount loop described above. This delta can then be added to
602 * enabled and possible running (if index), improving the scaling:
603 *
604 * enabled += delta;
605 * if (index)
606 * running += delta;
607 *
608 * quot = count / running;
609 * rem = count % running;
610 * count = quot * enabled + (rem * enabled) / running;
611 */
612 __u16 time_shift;
613 __u32 time_mult;
614 __u64 time_offset;
615 /*
616 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
617 * from sample timestamps.
618 *
619 * time = timestamp - time_zero;
620 * quot = time / time_mult;
621 * rem = time % time_mult;
622 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
623 *
624 * And vice versa:
625 *
626 * quot = cyc >> time_shift;
627 * rem = cyc & (((u64)1 << time_shift) - 1);
628 * timestamp = time_zero + quot * time_mult +
629 * ((rem * time_mult) >> time_shift);
630 */
631 __u64 time_zero;
632
633 __u32 size; /* Header size up to __reserved[] fields. */
634 __u32 __reserved_1;
635
636 /*
637 * If cap_usr_time_short, the hardware clock is less than 64bit wide
638 * and we must compute the 'cyc' value, as used by cap_usr_time, as:
639 *
640 * cyc = time_cycles + ((cyc - time_cycles) & time_mask)
641 *
642 * NOTE: this form is explicitly chosen such that cap_usr_time_short
643 * is a correction on top of cap_usr_time, and code that doesn't
644 * know about cap_usr_time_short still works under the assumption
645 * the counter doesn't wrap.
646 */
647 __u64 time_cycles;
648 __u64 time_mask;
649
650 /*
651 * Hole for extension of the self monitor capabilities
652 */
653
654 __u8 __reserved[116*8]; /* align to 1k. */
655
656 /*
657 * Control data for the mmap() data buffer.
658 *
659 * User-space reading the @data_head value should issue an smp_rmb(),
660 * after reading this value.
661 *
662 * When the mapping is PROT_WRITE the @data_tail value should be
663 * written by userspace to reflect the last read data, after issueing
664 * an smp_mb() to separate the data read from the ->data_tail store.
665 * In this case the kernel will not over-write unread data.
666 *
667 * See perf_output_put_handle() for the data ordering.
668 *
669 * data_{offset,size} indicate the location and size of the perf record
670 * buffer within the mmapped area.
671 */
672 __u64 data_head; /* head in the data section */
673 __u64 data_tail; /* user-space written tail */
674 __u64 data_offset; /* where the buffer starts */
675 __u64 data_size; /* data buffer size */
676
677 /*
678 * AUX area is defined by aux_{offset,size} fields that should be set
679 * by the userspace, so that
680 *
681 * aux_offset >= data_offset + data_size
682 *
683 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
684 *
685 * Ring buffer pointers aux_{head,tail} have the same semantics as
686 * data_{head,tail} and same ordering rules apply.
687 */
688 __u64 aux_head;
689 __u64 aux_tail;
690 __u64 aux_offset;
691 __u64 aux_size;
692};
693
694/*
695 * The current state of perf_event_header::misc bits usage:
696 * ('|' used bit, '-' unused bit)
697 *
698 * 012 CDEF
699 * |||---------||||
700 *
701 * Where:
702 * 0-2 CPUMODE_MASK
703 *
704 * C PROC_MAP_PARSE_TIMEOUT
705 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT
706 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT
707 * F (reserved)
708 */
709
710#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
711#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
712#define PERF_RECORD_MISC_KERNEL (1 << 0)
713#define PERF_RECORD_MISC_USER (2 << 0)
714#define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
715#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
716#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
717
718/*
719 * Indicates that /proc/PID/maps parsing are truncated by time out.
720 */
721#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
722/*
723 * Following PERF_RECORD_MISC_* are used on different
724 * events, so can reuse the same bit position:
725 *
726 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events
727 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event
728 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal)
729 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events
730 */
731#define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
732#define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
733#define PERF_RECORD_MISC_FORK_EXEC (1 << 13)
734#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
735/*
736 * These PERF_RECORD_MISC_* flags below are safely reused
737 * for the following events:
738 *
739 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events
740 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events
741 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event
742 *
743 *
744 * PERF_RECORD_MISC_EXACT_IP:
745 * Indicates that the content of PERF_SAMPLE_IP points to
746 * the actual instruction that triggered the event. See also
747 * perf_event_attr::precise_ip.
748 *
749 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT:
750 * Indicates that thread was preempted in TASK_RUNNING state.
751 *
752 * PERF_RECORD_MISC_MMAP_BUILD_ID:
753 * Indicates that mmap2 event carries build id data.
754 */
755#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
756#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14)
757#define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14)
758/*
759 * Reserve the last bit to indicate some extended misc field
760 */
761#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
762
763struct perf_event_header {
764 __u32 type;
765 __u16 misc;
766 __u16 size;
767};
768
769struct perf_ns_link_info {
770 __u64 dev;
771 __u64 ino;
772};
773
774enum {
775 NET_NS_INDEX = 0,
776 UTS_NS_INDEX = 1,
777 IPC_NS_INDEX = 2,
778 PID_NS_INDEX = 3,
779 USER_NS_INDEX = 4,
780 MNT_NS_INDEX = 5,
781 CGROUP_NS_INDEX = 6,
782
783 NR_NAMESPACES, /* number of available namespaces */
784};
785
786enum perf_event_type {
787
788 /*
789 * If perf_event_attr.sample_id_all is set then all event types will
790 * have the sample_type selected fields related to where/when
791 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
792 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
793 * just after the perf_event_header and the fields already present for
794 * the existing fields, i.e. at the end of the payload. That way a newer
795 * perf.data file will be supported by older perf tools, with these new
796 * optional fields being ignored.
797 *
798 * struct sample_id {
799 * { u32 pid, tid; } && PERF_SAMPLE_TID
800 * { u64 time; } && PERF_SAMPLE_TIME
801 * { u64 id; } && PERF_SAMPLE_ID
802 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
803 * { u32 cpu, res; } && PERF_SAMPLE_CPU
804 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
805 * } && perf_event_attr::sample_id_all
806 *
807 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
808 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
809 * relative to header.size.
810 */
811
812 /*
813 * The MMAP events record the PROT_EXEC mappings so that we can
814 * correlate userspace IPs to code. They have the following structure:
815 *
816 * struct {
817 * struct perf_event_header header;
818 *
819 * u32 pid, tid;
820 * u64 addr;
821 * u64 len;
822 * u64 pgoff;
823 * char filename[];
824 * struct sample_id sample_id;
825 * };
826 */
827 PERF_RECORD_MMAP = 1,
828
829 /*
830 * struct {
831 * struct perf_event_header header;
832 * u64 id;
833 * u64 lost;
834 * struct sample_id sample_id;
835 * };
836 */
837 PERF_RECORD_LOST = 2,
838
839 /*
840 * struct {
841 * struct perf_event_header header;
842 *
843 * u32 pid, tid;
844 * char comm[];
845 * struct sample_id sample_id;
846 * };
847 */
848 PERF_RECORD_COMM = 3,
849
850 /*
851 * struct {
852 * struct perf_event_header header;
853 * u32 pid, ppid;
854 * u32 tid, ptid;
855 * u64 time;
856 * struct sample_id sample_id;
857 * };
858 */
859 PERF_RECORD_EXIT = 4,
860
861 /*
862 * struct {
863 * struct perf_event_header header;
864 * u64 time;
865 * u64 id;
866 * u64 stream_id;
867 * struct sample_id sample_id;
868 * };
869 */
870 PERF_RECORD_THROTTLE = 5,
871 PERF_RECORD_UNTHROTTLE = 6,
872
873 /*
874 * struct {
875 * struct perf_event_header header;
876 * u32 pid, ppid;
877 * u32 tid, ptid;
878 * u64 time;
879 * struct sample_id sample_id;
880 * };
881 */
882 PERF_RECORD_FORK = 7,
883
884 /*
885 * struct {
886 * struct perf_event_header header;
887 * u32 pid, tid;
888 *
889 * struct read_format values;
890 * struct sample_id sample_id;
891 * };
892 */
893 PERF_RECORD_READ = 8,
894
895 /*
896 * struct {
897 * struct perf_event_header header;
898 *
899 * #
900 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
901 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
902 * # is fixed relative to header.
903 * #
904 *
905 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
906 * { u64 ip; } && PERF_SAMPLE_IP
907 * { u32 pid, tid; } && PERF_SAMPLE_TID
908 * { u64 time; } && PERF_SAMPLE_TIME
909 * { u64 addr; } && PERF_SAMPLE_ADDR
910 * { u64 id; } && PERF_SAMPLE_ID
911 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
912 * { u32 cpu, res; } && PERF_SAMPLE_CPU
913 * { u64 period; } && PERF_SAMPLE_PERIOD
914 *
915 * { struct read_format values; } && PERF_SAMPLE_READ
916 *
917 * { u64 nr,
918 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
919 *
920 * #
921 * # The RAW record below is opaque data wrt the ABI
922 * #
923 * # That is, the ABI doesn't make any promises wrt to
924 * # the stability of its content, it may vary depending
925 * # on event, hardware, kernel version and phase of
926 * # the moon.
927 * #
928 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
929 * #
930 *
931 * { u32 size;
932 * char data[size];}&& PERF_SAMPLE_RAW
933 *
934 * { u64 nr;
935 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
936 * { u64 from, to, flags } lbr[nr];
937 * } && PERF_SAMPLE_BRANCH_STACK
938 *
939 * { u64 abi; # enum perf_sample_regs_abi
940 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
941 *
942 * { u64 size;
943 * char data[size];
944 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
945 *
946 * { union perf_sample_weight
947 * {
948 * u64 full; && PERF_SAMPLE_WEIGHT
949 * #if defined(__LITTLE_ENDIAN_BITFIELD)
950 * struct {
951 * u32 var1_dw;
952 * u16 var2_w;
953 * u16 var3_w;
954 * } && PERF_SAMPLE_WEIGHT_STRUCT
955 * #elif defined(__BIG_ENDIAN_BITFIELD)
956 * struct {
957 * u16 var3_w;
958 * u16 var2_w;
959 * u32 var1_dw;
960 * } && PERF_SAMPLE_WEIGHT_STRUCT
961 * #endif
962 * }
963 * }
964 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
965 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
966 * { u64 abi; # enum perf_sample_regs_abi
967 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
968 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
969 * { u64 size;
970 * char data[size]; } && PERF_SAMPLE_AUX
971 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE
972 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE
973 * };
974 */
975 PERF_RECORD_SAMPLE = 9,
976
977 /*
978 * The MMAP2 records are an augmented version of MMAP, they add
979 * maj, min, ino numbers to be used to uniquely identify each mapping
980 *
981 * struct {
982 * struct perf_event_header header;
983 *
984 * u32 pid, tid;
985 * u64 addr;
986 * u64 len;
987 * u64 pgoff;
988 * union {
989 * struct {
990 * u32 maj;
991 * u32 min;
992 * u64 ino;
993 * u64 ino_generation;
994 * };
995 * struct {
996 * u8 build_id_size;
997 * u8 __reserved_1;
998 * u16 __reserved_2;
999 * u8 build_id[20];
1000 * };
1001 * };
1002 * u32 prot, flags;
1003 * char filename[];
1004 * struct sample_id sample_id;
1005 * };
1006 */
1007 PERF_RECORD_MMAP2 = 10,
1008
1009 /*
1010 * Records that new data landed in the AUX buffer part.
1011 *
1012 * struct {
1013 * struct perf_event_header header;
1014 *
1015 * u64 aux_offset;
1016 * u64 aux_size;
1017 * u64 flags;
1018 * struct sample_id sample_id;
1019 * };
1020 */
1021 PERF_RECORD_AUX = 11,
1022
1023 /*
1024 * Indicates that instruction trace has started
1025 *
1026 * struct {
1027 * struct perf_event_header header;
1028 * u32 pid;
1029 * u32 tid;
1030 * struct sample_id sample_id;
1031 * };
1032 */
1033 PERF_RECORD_ITRACE_START = 12,
1034
1035 /*
1036 * Records the dropped/lost sample number.
1037 *
1038 * struct {
1039 * struct perf_event_header header;
1040 *
1041 * u64 lost;
1042 * struct sample_id sample_id;
1043 * };
1044 */
1045 PERF_RECORD_LOST_SAMPLES = 13,
1046
1047 /*
1048 * Records a context switch in or out (flagged by
1049 * PERF_RECORD_MISC_SWITCH_OUT). See also
1050 * PERF_RECORD_SWITCH_CPU_WIDE.
1051 *
1052 * struct {
1053 * struct perf_event_header header;
1054 * struct sample_id sample_id;
1055 * };
1056 */
1057 PERF_RECORD_SWITCH = 14,
1058
1059 /*
1060 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
1061 * next_prev_tid that are the next (switching out) or previous
1062 * (switching in) pid/tid.
1063 *
1064 * struct {
1065 * struct perf_event_header header;
1066 * u32 next_prev_pid;
1067 * u32 next_prev_tid;
1068 * struct sample_id sample_id;
1069 * };
1070 */
1071 PERF_RECORD_SWITCH_CPU_WIDE = 15,
1072
1073 /*
1074 * struct {
1075 * struct perf_event_header header;
1076 * u32 pid;
1077 * u32 tid;
1078 * u64 nr_namespaces;
1079 * { u64 dev, inode; } [nr_namespaces];
1080 * struct sample_id sample_id;
1081 * };
1082 */
1083 PERF_RECORD_NAMESPACES = 16,
1084
1085 /*
1086 * Record ksymbol register/unregister events:
1087 *
1088 * struct {
1089 * struct perf_event_header header;
1090 * u64 addr;
1091 * u32 len;
1092 * u16 ksym_type;
1093 * u16 flags;
1094 * char name[];
1095 * struct sample_id sample_id;
1096 * };
1097 */
1098 PERF_RECORD_KSYMBOL = 17,
1099
1100 /*
1101 * Record bpf events:
1102 * enum perf_bpf_event_type {
1103 * PERF_BPF_EVENT_UNKNOWN = 0,
1104 * PERF_BPF_EVENT_PROG_LOAD = 1,
1105 * PERF_BPF_EVENT_PROG_UNLOAD = 2,
1106 * };
1107 *
1108 * struct {
1109 * struct perf_event_header header;
1110 * u16 type;
1111 * u16 flags;
1112 * u32 id;
1113 * u8 tag[BPF_TAG_SIZE];
1114 * struct sample_id sample_id;
1115 * };
1116 */
1117 PERF_RECORD_BPF_EVENT = 18,
1118
1119 /*
1120 * struct {
1121 * struct perf_event_header header;
1122 * u64 id;
1123 * char path[];
1124 * struct sample_id sample_id;
1125 * };
1126 */
1127 PERF_RECORD_CGROUP = 19,
1128
1129 /*
1130 * Records changes to kernel text i.e. self-modified code. 'old_len' is
1131 * the number of old bytes, 'new_len' is the number of new bytes. Either
1132 * 'old_len' or 'new_len' may be zero to indicate, for example, the
1133 * addition or removal of a trampoline. 'bytes' contains the old bytes
1134 * followed immediately by the new bytes.
1135 *
1136 * struct {
1137 * struct perf_event_header header;
1138 * u64 addr;
1139 * u16 old_len;
1140 * u16 new_len;
1141 * u8 bytes[];
1142 * struct sample_id sample_id;
1143 * };
1144 */
1145 PERF_RECORD_TEXT_POKE = 20,
1146
1147 PERF_RECORD_MAX, /* non-ABI */
1148};
1149
1150enum perf_record_ksymbol_type {
1151 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,
1152 PERF_RECORD_KSYMBOL_TYPE_BPF = 1,
1153 /*
1154 * Out of line code such as kprobe-replaced instructions or optimized
1155 * kprobes or ftrace trampolines.
1156 */
1157 PERF_RECORD_KSYMBOL_TYPE_OOL = 2,
1158 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */
1159};
1160
1161#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0)
1162
1163enum perf_bpf_event_type {
1164 PERF_BPF_EVENT_UNKNOWN = 0,
1165 PERF_BPF_EVENT_PROG_LOAD = 1,
1166 PERF_BPF_EVENT_PROG_UNLOAD = 2,
1167 PERF_BPF_EVENT_MAX, /* non-ABI */
1168};
1169
1170#define PERF_MAX_STACK_DEPTH 127
1171#define PERF_MAX_CONTEXTS_PER_STACK 8
1172
1173enum perf_callchain_context {
1174 PERF_CONTEXT_HV = (__u64)-32,
1175 PERF_CONTEXT_KERNEL = (__u64)-128,
1176 PERF_CONTEXT_USER = (__u64)-512,
1177
1178 PERF_CONTEXT_GUEST = (__u64)-2048,
1179 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
1180 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
1181
1182 PERF_CONTEXT_MAX = (__u64)-4095,
1183};
1184
1185/**
1186 * PERF_RECORD_AUX::flags bits
1187 */
1188#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
1189#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
1190#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
1191#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
1192#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */
1193
1194/* CoreSight PMU AUX buffer formats */
1195#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
1196#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */
1197
1198#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
1199#define PERF_FLAG_FD_OUTPUT (1UL << 1)
1200#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
1201#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
1202
1203#if defined(__LITTLE_ENDIAN_BITFIELD)
1204union perf_mem_data_src {
1205 __u64 val;
1206 struct {
1207 __u64 mem_op:5, /* type of opcode */
1208 mem_lvl:14, /* memory hierarchy level */
1209 mem_snoop:5, /* snoop mode */
1210 mem_lock:2, /* lock instr */
1211 mem_dtlb:7, /* tlb access */
1212 mem_lvl_num:4, /* memory hierarchy level number */
1213 mem_remote:1, /* remote */
1214 mem_snoopx:2, /* snoop mode, ext */
1215 mem_blk:3, /* access blocked */
1216 mem_rsvd:21;
1217 };
1218};
1219#elif defined(__BIG_ENDIAN_BITFIELD)
1220union perf_mem_data_src {
1221 __u64 val;
1222 struct {
1223 __u64 mem_rsvd:21,
1224 mem_blk:3, /* access blocked */
1225 mem_snoopx:2, /* snoop mode, ext */
1226 mem_remote:1, /* remote */
1227 mem_lvl_num:4, /* memory hierarchy level number */
1228 mem_dtlb:7, /* tlb access */
1229 mem_lock:2, /* lock instr */
1230 mem_snoop:5, /* snoop mode */
1231 mem_lvl:14, /* memory hierarchy level */
1232 mem_op:5; /* type of opcode */
1233 };
1234};
1235#else
1236#error "Unknown endianness"
1237#endif
1238
1239/* type of opcode (load/store/prefetch,code) */
1240#define PERF_MEM_OP_NA 0x01 /* not available */
1241#define PERF_MEM_OP_LOAD 0x02 /* load instruction */
1242#define PERF_MEM_OP_STORE 0x04 /* store instruction */
1243#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
1244#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
1245#define PERF_MEM_OP_SHIFT 0
1246
1247/* memory hierarchy (memory level, hit or miss) */
1248#define PERF_MEM_LVL_NA 0x01 /* not available */
1249#define PERF_MEM_LVL_HIT 0x02 /* hit level */
1250#define PERF_MEM_LVL_MISS 0x04 /* miss level */
1251#define PERF_MEM_LVL_L1 0x08 /* L1 */
1252#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
1253#define PERF_MEM_LVL_L2 0x20 /* L2 */
1254#define PERF_MEM_LVL_L3 0x40 /* L3 */
1255#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
1256#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
1257#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
1258#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
1259#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
1260#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1261#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1262#define PERF_MEM_LVL_SHIFT 5
1263
1264#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */
1265#define PERF_MEM_REMOTE_SHIFT 37
1266
1267#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */
1268#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
1269#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1270#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1271/* 5-0xa available */
1272#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1273#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
1274#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
1275#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */
1276#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */
1277
1278#define PERF_MEM_LVLNUM_SHIFT 33
1279
1280/* snoop mode */
1281#define PERF_MEM_SNOOP_NA 0x01 /* not available */
1282#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
1283#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
1284#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
1285#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
1286#define PERF_MEM_SNOOP_SHIFT 19
1287
1288#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */
1289/* 1 free */
1290#define PERF_MEM_SNOOPX_SHIFT 38
1291
1292/* locked instruction */
1293#define PERF_MEM_LOCK_NA 0x01 /* not available */
1294#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
1295#define PERF_MEM_LOCK_SHIFT 24
1296
1297/* TLB access */
1298#define PERF_MEM_TLB_NA 0x01 /* not available */
1299#define PERF_MEM_TLB_HIT 0x02 /* hit level */
1300#define PERF_MEM_TLB_MISS 0x04 /* miss level */
1301#define PERF_MEM_TLB_L1 0x08 /* L1 */
1302#define PERF_MEM_TLB_L2 0x10 /* L2 */
1303#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
1304#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
1305#define PERF_MEM_TLB_SHIFT 26
1306
1307/* Access blocked */
1308#define PERF_MEM_BLK_NA 0x01 /* not available */
1309#define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */
1310#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */
1311#define PERF_MEM_BLK_SHIFT 40
1312
1313#define PERF_MEM_S(a, s) \
1314 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1315
1316/*
1317 * single taken branch record layout:
1318 *
1319 * from: source instruction (may not always be a branch insn)
1320 * to: branch target
1321 * mispred: branch target was mispredicted
1322 * predicted: branch target was predicted
1323 *
1324 * support for mispred, predicted is optional. In case it
1325 * is not supported mispred = predicted = 0.
1326 *
1327 * in_tx: running in a hardware transaction
1328 * abort: aborting a hardware transaction
1329 * cycles: cycles from last branch (or 0 if not supported)
1330 * type: branch type
1331 */
1332struct perf_branch_entry {
1333 __u64 from;
1334 __u64 to;
1335 __u64 mispred:1, /* target mispredicted */
1336 predicted:1,/* target predicted */
1337 in_tx:1, /* in transaction */
1338 abort:1, /* transaction abort */
1339 cycles:16, /* cycle count to last branch */
1340 type:4, /* branch type */
1341 reserved:40;
1342};
1343
1344union perf_sample_weight {
1345 __u64 full;
1346#if defined(__LITTLE_ENDIAN_BITFIELD)
1347 struct {
1348 __u32 var1_dw;
1349 __u16 var2_w;
1350 __u16 var3_w;
1351 };
1352#elif defined(__BIG_ENDIAN_BITFIELD)
1353 struct {
1354 __u16 var3_w;
1355 __u16 var2_w;
1356 __u32 var1_dw;
1357 };
1358#else
1359#error "Unknown endianness"
1360#endif
1361};
1362
1363#endif /* _LINUX_PERF_EVENT_H */
1364

source code of include/linux/perf_event.h