1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Performance events:
4 *
5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 *
9 * Data type definitions, declarations, prototypes.
10 *
11 * Started by: Thomas Gleixner and Ingo Molnar
12 *
13 * For licencing details see kernel-base/COPYING
14 */
15#ifndef _LINUX_PERF_EVENT_H
16#define _LINUX_PERF_EVENT_H
17
18#include <linux/types.h>
19#include <linux/ioctl.h>
20#include <asm/byteorder.h>
21
22/*
23 * User-space ABI bits:
24 */
25
26/*
27 * attr.type
28 */
29enum perf_type_id {
30 PERF_TYPE_HARDWARE = 0,
31 PERF_TYPE_SOFTWARE = 1,
32 PERF_TYPE_TRACEPOINT = 2,
33 PERF_TYPE_HW_CACHE = 3,
34 PERF_TYPE_RAW = 4,
35 PERF_TYPE_BREAKPOINT = 5,
36
37 PERF_TYPE_MAX, /* non-ABI */
38};
39
40/*
41 * Generalized performance event event_id types, used by the
42 * attr.event_id parameter of the sys_perf_event_open()
43 * syscall:
44 */
45enum perf_hw_id {
46 /*
47 * Common hardware events, generalized by the kernel:
48 */
49 PERF_COUNT_HW_CPU_CYCLES = 0,
50 PERF_COUNT_HW_INSTRUCTIONS = 1,
51 PERF_COUNT_HW_CACHE_REFERENCES = 2,
52 PERF_COUNT_HW_CACHE_MISSES = 3,
53 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
54 PERF_COUNT_HW_BRANCH_MISSES = 5,
55 PERF_COUNT_HW_BUS_CYCLES = 6,
56 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
57 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
58 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
59
60 PERF_COUNT_HW_MAX, /* non-ABI */
61};
62
63/*
64 * Generalized hardware cache events:
65 *
66 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
67 * { read, write, prefetch } x
68 * { accesses, misses }
69 */
70enum perf_hw_cache_id {
71 PERF_COUNT_HW_CACHE_L1D = 0,
72 PERF_COUNT_HW_CACHE_L1I = 1,
73 PERF_COUNT_HW_CACHE_LL = 2,
74 PERF_COUNT_HW_CACHE_DTLB = 3,
75 PERF_COUNT_HW_CACHE_ITLB = 4,
76 PERF_COUNT_HW_CACHE_BPU = 5,
77 PERF_COUNT_HW_CACHE_NODE = 6,
78
79 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
80};
81
82enum perf_hw_cache_op_id {
83 PERF_COUNT_HW_CACHE_OP_READ = 0,
84 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
85 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
86
87 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
88};
89
90enum perf_hw_cache_op_result_id {
91 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
92 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
93
94 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
95};
96
97/*
98 * Special "software" events provided by the kernel, even if the hardware
99 * does not support performance events. These events measure various
100 * physical and sw events of the kernel (and allow the profiling of them as
101 * well):
102 */
103enum perf_sw_ids {
104 PERF_COUNT_SW_CPU_CLOCK = 0,
105 PERF_COUNT_SW_TASK_CLOCK = 1,
106 PERF_COUNT_SW_PAGE_FAULTS = 2,
107 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
108 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
109 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
110 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
111 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
112 PERF_COUNT_SW_EMULATION_FAULTS = 8,
113 PERF_COUNT_SW_DUMMY = 9,
114 PERF_COUNT_SW_BPF_OUTPUT = 10,
115
116 PERF_COUNT_SW_MAX, /* non-ABI */
117};
118
119/*
120 * Bits that can be set in attr.sample_type to request information
121 * in the overflow packets.
122 */
123enum perf_event_sample_format {
124 PERF_SAMPLE_IP = 1U << 0,
125 PERF_SAMPLE_TID = 1U << 1,
126 PERF_SAMPLE_TIME = 1U << 2,
127 PERF_SAMPLE_ADDR = 1U << 3,
128 PERF_SAMPLE_READ = 1U << 4,
129 PERF_SAMPLE_CALLCHAIN = 1U << 5,
130 PERF_SAMPLE_ID = 1U << 6,
131 PERF_SAMPLE_CPU = 1U << 7,
132 PERF_SAMPLE_PERIOD = 1U << 8,
133 PERF_SAMPLE_STREAM_ID = 1U << 9,
134 PERF_SAMPLE_RAW = 1U << 10,
135 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
136 PERF_SAMPLE_REGS_USER = 1U << 12,
137 PERF_SAMPLE_STACK_USER = 1U << 13,
138 PERF_SAMPLE_WEIGHT = 1U << 14,
139 PERF_SAMPLE_DATA_SRC = 1U << 15,
140 PERF_SAMPLE_IDENTIFIER = 1U << 16,
141 PERF_SAMPLE_TRANSACTION = 1U << 17,
142 PERF_SAMPLE_REGS_INTR = 1U << 18,
143 PERF_SAMPLE_PHYS_ADDR = 1U << 19,
144
145 PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */
146
147 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */
148};
149
150/*
151 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
152 *
153 * If the user does not pass priv level information via branch_sample_type,
154 * the kernel uses the event's priv level. Branch and event priv levels do
155 * not have to match. Branch priv level is checked for permissions.
156 *
157 * The branch types can be combined, however BRANCH_ANY covers all types
158 * of branches and therefore it supersedes all the other types.
159 */
160enum perf_branch_sample_type_shift {
161 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
162 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
163 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
164
165 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
166 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
167 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
168 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
169 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
170 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
171 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
172 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
173
174 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
175 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
176 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
177
178 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
179 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
180
181 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */
182
183 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
184};
185
186enum perf_branch_sample_type {
187 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
188 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
189 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
190
191 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
192 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
193 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
194 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
195 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
196 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
197 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
198 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
199
200 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
201 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
202 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
203
204 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
205 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
206
207 PERF_SAMPLE_BRANCH_TYPE_SAVE =
208 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
209
210 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
211};
212
213/*
214 * Common flow change classification
215 */
216enum {
217 PERF_BR_UNKNOWN = 0, /* unknown */
218 PERF_BR_COND = 1, /* conditional */
219 PERF_BR_UNCOND = 2, /* unconditional */
220 PERF_BR_IND = 3, /* indirect */
221 PERF_BR_CALL = 4, /* function call */
222 PERF_BR_IND_CALL = 5, /* indirect function call */
223 PERF_BR_RET = 6, /* function return */
224 PERF_BR_SYSCALL = 7, /* syscall */
225 PERF_BR_SYSRET = 8, /* syscall return */
226 PERF_BR_COND_CALL = 9, /* conditional function call */
227 PERF_BR_COND_RET = 10, /* conditional function return */
228 PERF_BR_MAX,
229};
230
231#define PERF_SAMPLE_BRANCH_PLM_ALL \
232 (PERF_SAMPLE_BRANCH_USER|\
233 PERF_SAMPLE_BRANCH_KERNEL|\
234 PERF_SAMPLE_BRANCH_HV)
235
236/*
237 * Values to determine ABI of the registers dump.
238 */
239enum perf_sample_regs_abi {
240 PERF_SAMPLE_REGS_ABI_NONE = 0,
241 PERF_SAMPLE_REGS_ABI_32 = 1,
242 PERF_SAMPLE_REGS_ABI_64 = 2,
243};
244
245/*
246 * Values for the memory transaction event qualifier, mostly for
247 * abort events. Multiple bits can be set.
248 */
249enum {
250 PERF_TXN_ELISION = (1 << 0), /* From elision */
251 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
252 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
253 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
254 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
255 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
256 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
257 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
258
259 PERF_TXN_MAX = (1 << 8), /* non-ABI */
260
261 /* bits 32..63 are reserved for the abort code */
262
263 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
264 PERF_TXN_ABORT_SHIFT = 32,
265};
266
267/*
268 * The format of the data returned by read() on a perf event fd,
269 * as specified by attr.read_format:
270 *
271 * struct read_format {
272 * { u64 value;
273 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
274 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
275 * { u64 id; } && PERF_FORMAT_ID
276 * } && !PERF_FORMAT_GROUP
277 *
278 * { u64 nr;
279 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
280 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
281 * { u64 value;
282 * { u64 id; } && PERF_FORMAT_ID
283 * } cntr[nr];
284 * } && PERF_FORMAT_GROUP
285 * };
286 */
287enum perf_event_read_format {
288 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
289 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
290 PERF_FORMAT_ID = 1U << 2,
291 PERF_FORMAT_GROUP = 1U << 3,
292
293 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
294};
295
296#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
297#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
298#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
299#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
300 /* add: sample_stack_user */
301#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
302#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
303
304/*
305 * Hardware event_id to monitor via a performance monitoring event:
306 *
307 * @sample_max_stack: Max number of frame pointers in a callchain,
308 * should be < /proc/sys/kernel/perf_event_max_stack
309 */
310struct perf_event_attr {
311
312 /*
313 * Major type: hardware/software/tracepoint/etc.
314 */
315 __u32 type;
316
317 /*
318 * Size of the attr structure, for fwd/bwd compat.
319 */
320 __u32 size;
321
322 /*
323 * Type specific configuration information.
324 */
325 __u64 config;
326
327 union {
328 __u64 sample_period;
329 __u64 sample_freq;
330 };
331
332 __u64 sample_type;
333 __u64 read_format;
334
335 __u64 disabled : 1, /* off by default */
336 inherit : 1, /* children inherit it */
337 pinned : 1, /* must always be on PMU */
338 exclusive : 1, /* only group on PMU */
339 exclude_user : 1, /* don't count user */
340 exclude_kernel : 1, /* ditto kernel */
341 exclude_hv : 1, /* ditto hypervisor */
342 exclude_idle : 1, /* don't count when idle */
343 mmap : 1, /* include mmap data */
344 comm : 1, /* include comm data */
345 freq : 1, /* use freq, not period */
346 inherit_stat : 1, /* per task counts */
347 enable_on_exec : 1, /* next exec enables */
348 task : 1, /* trace fork/exit */
349 watermark : 1, /* wakeup_watermark */
350 /*
351 * precise_ip:
352 *
353 * 0 - SAMPLE_IP can have arbitrary skid
354 * 1 - SAMPLE_IP must have constant skid
355 * 2 - SAMPLE_IP requested to have 0 skid
356 * 3 - SAMPLE_IP must have 0 skid
357 *
358 * See also PERF_RECORD_MISC_EXACT_IP
359 */
360 precise_ip : 2, /* skid constraint */
361 mmap_data : 1, /* non-exec mmap data */
362 sample_id_all : 1, /* sample_type all events */
363
364 exclude_host : 1, /* don't count in host */
365 exclude_guest : 1, /* don't count in guest */
366
367 exclude_callchain_kernel : 1, /* exclude kernel callchains */
368 exclude_callchain_user : 1, /* exclude user callchains */
369 mmap2 : 1, /* include mmap with inode data */
370 comm_exec : 1, /* flag comm events that are due to an exec */
371 use_clockid : 1, /* use @clockid for time fields */
372 context_switch : 1, /* context switch data */
373 write_backward : 1, /* Write ring buffer from end to beginning */
374 namespaces : 1, /* include namespaces data */
375 ksymbol : 1, /* include ksymbol events */
376 bpf_event : 1, /* include bpf events */
377 aux_output : 1, /* generate AUX records instead of events */
378 __reserved_1 : 32;
379
380 union {
381 __u32 wakeup_events; /* wakeup every n events */
382 __u32 wakeup_watermark; /* bytes before wakeup */
383 };
384
385 __u32 bp_type;
386 union {
387 __u64 bp_addr;
388 __u64 kprobe_func; /* for perf_kprobe */
389 __u64 uprobe_path; /* for perf_uprobe */
390 __u64 config1; /* extension of config */
391 };
392 union {
393 __u64 bp_len;
394 __u64 kprobe_addr; /* when kprobe_func == NULL */
395 __u64 probe_offset; /* for perf_[k,u]probe */
396 __u64 config2; /* extension of config1 */
397 };
398 __u64 branch_sample_type; /* enum perf_branch_sample_type */
399
400 /*
401 * Defines set of user regs to dump on samples.
402 * See asm/perf_regs.h for details.
403 */
404 __u64 sample_regs_user;
405
406 /*
407 * Defines size of the user stack to dump on samples.
408 */
409 __u32 sample_stack_user;
410
411 __s32 clockid;
412 /*
413 * Defines set of regs to dump for each sample
414 * state captured on:
415 * - precise = 0: PMU interrupt
416 * - precise > 0: sampled instruction
417 *
418 * See asm/perf_regs.h for details.
419 */
420 __u64 sample_regs_intr;
421
422 /*
423 * Wakeup watermark for AUX area
424 */
425 __u32 aux_watermark;
426 __u16 sample_max_stack;
427 __u16 __reserved_2; /* align to __u64 */
428};
429
430/*
431 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command
432 * to query bpf programs attached to the same perf tracepoint
433 * as the given perf event.
434 */
435struct perf_event_query_bpf {
436 /*
437 * The below ids array length
438 */
439 __u32 ids_len;
440 /*
441 * Set by the kernel to indicate the number of
442 * available programs
443 */
444 __u32 prog_cnt;
445 /*
446 * User provided buffer to store program ids
447 */
448 __u32 ids[0];
449};
450
451/*
452 * Ioctls that can be done on a perf event fd:
453 */
454#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
455#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
456#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
457#define PERF_EVENT_IOC_RESET _IO ('$', 3)
458#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
459#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
460#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
461#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
462#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
463#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
464#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *)
465#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *)
466
467enum perf_event_ioc_flags {
468 PERF_IOC_FLAG_GROUP = 1U << 0,
469};
470
471/*
472 * Structure of the page that can be mapped via mmap
473 */
474struct perf_event_mmap_page {
475 __u32 version; /* version number of this structure */
476 __u32 compat_version; /* lowest version this is compat with */
477
478 /*
479 * Bits needed to read the hw events in user-space.
480 *
481 * u32 seq, time_mult, time_shift, index, width;
482 * u64 count, enabled, running;
483 * u64 cyc, time_offset;
484 * s64 pmc = 0;
485 *
486 * do {
487 * seq = pc->lock;
488 * barrier()
489 *
490 * enabled = pc->time_enabled;
491 * running = pc->time_running;
492 *
493 * if (pc->cap_usr_time && enabled != running) {
494 * cyc = rdtsc();
495 * time_offset = pc->time_offset;
496 * time_mult = pc->time_mult;
497 * time_shift = pc->time_shift;
498 * }
499 *
500 * index = pc->index;
501 * count = pc->offset;
502 * if (pc->cap_user_rdpmc && index) {
503 * width = pc->pmc_width;
504 * pmc = rdpmc(index - 1);
505 * }
506 *
507 * barrier();
508 * } while (pc->lock != seq);
509 *
510 * NOTE: for obvious reason this only works on self-monitoring
511 * processes.
512 */
513 __u32 lock; /* seqlock for synchronization */
514 __u32 index; /* hardware event identifier */
515 __s64 offset; /* add to hardware event value */
516 __u64 time_enabled; /* time event active */
517 __u64 time_running; /* time event on cpu */
518 union {
519 __u64 capabilities;
520 struct {
521 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
522 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
523
524 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
525 cap_user_time : 1, /* The time_* fields are used */
526 cap_user_time_zero : 1, /* The time_zero field is used */
527 cap_____res : 59;
528 };
529 };
530
531 /*
532 * If cap_user_rdpmc this field provides the bit-width of the value
533 * read using the rdpmc() or equivalent instruction. This can be used
534 * to sign extend the result like:
535 *
536 * pmc <<= 64 - width;
537 * pmc >>= 64 - width; // signed shift right
538 * count += pmc;
539 */
540 __u16 pmc_width;
541
542 /*
543 * If cap_usr_time the below fields can be used to compute the time
544 * delta since time_enabled (in ns) using rdtsc or similar.
545 *
546 * u64 quot, rem;
547 * u64 delta;
548 *
549 * quot = (cyc >> time_shift);
550 * rem = cyc & (((u64)1 << time_shift) - 1);
551 * delta = time_offset + quot * time_mult +
552 * ((rem * time_mult) >> time_shift);
553 *
554 * Where time_offset,time_mult,time_shift and cyc are read in the
555 * seqcount loop described above. This delta can then be added to
556 * enabled and possible running (if index), improving the scaling:
557 *
558 * enabled += delta;
559 * if (index)
560 * running += delta;
561 *
562 * quot = count / running;
563 * rem = count % running;
564 * count = quot * enabled + (rem * enabled) / running;
565 */
566 __u16 time_shift;
567 __u32 time_mult;
568 __u64 time_offset;
569 /*
570 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
571 * from sample timestamps.
572 *
573 * time = timestamp - time_zero;
574 * quot = time / time_mult;
575 * rem = time % time_mult;
576 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
577 *
578 * And vice versa:
579 *
580 * quot = cyc >> time_shift;
581 * rem = cyc & (((u64)1 << time_shift) - 1);
582 * timestamp = time_zero + quot * time_mult +
583 * ((rem * time_mult) >> time_shift);
584 */
585 __u64 time_zero;
586 __u32 size; /* Header size up to __reserved[] fields. */
587
588 /*
589 * Hole for extension of the self monitor capabilities
590 */
591
592 __u8 __reserved[118*8+4]; /* align to 1k. */
593
594 /*
595 * Control data for the mmap() data buffer.
596 *
597 * User-space reading the @data_head value should issue an smp_rmb(),
598 * after reading this value.
599 *
600 * When the mapping is PROT_WRITE the @data_tail value should be
601 * written by userspace to reflect the last read data, after issueing
602 * an smp_mb() to separate the data read from the ->data_tail store.
603 * In this case the kernel will not over-write unread data.
604 *
605 * See perf_output_put_handle() for the data ordering.
606 *
607 * data_{offset,size} indicate the location and size of the perf record
608 * buffer within the mmapped area.
609 */
610 __u64 data_head; /* head in the data section */
611 __u64 data_tail; /* user-space written tail */
612 __u64 data_offset; /* where the buffer starts */
613 __u64 data_size; /* data buffer size */
614
615 /*
616 * AUX area is defined by aux_{offset,size} fields that should be set
617 * by the userspace, so that
618 *
619 * aux_offset >= data_offset + data_size
620 *
621 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
622 *
623 * Ring buffer pointers aux_{head,tail} have the same semantics as
624 * data_{head,tail} and same ordering rules apply.
625 */
626 __u64 aux_head;
627 __u64 aux_tail;
628 __u64 aux_offset;
629 __u64 aux_size;
630};
631
632#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
633#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
634#define PERF_RECORD_MISC_KERNEL (1 << 0)
635#define PERF_RECORD_MISC_USER (2 << 0)
636#define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
637#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
638#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
639
640/*
641 * Indicates that /proc/PID/maps parsing are truncated by time out.
642 */
643#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
644/*
645 * Following PERF_RECORD_MISC_* are used on different
646 * events, so can reuse the same bit position:
647 *
648 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events
649 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event
650 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal)
651 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events
652 */
653#define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
654#define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
655#define PERF_RECORD_MISC_FORK_EXEC (1 << 13)
656#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
657/*
658 * These PERF_RECORD_MISC_* flags below are safely reused
659 * for the following events:
660 *
661 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events
662 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events
663 *
664 *
665 * PERF_RECORD_MISC_EXACT_IP:
666 * Indicates that the content of PERF_SAMPLE_IP points to
667 * the actual instruction that triggered the event. See also
668 * perf_event_attr::precise_ip.
669 *
670 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT:
671 * Indicates that thread was preempted in TASK_RUNNING state.
672 */
673#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
674#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14)
675/*
676 * Reserve the last bit to indicate some extended misc field
677 */
678#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
679
680struct perf_event_header {
681 __u32 type;
682 __u16 misc;
683 __u16 size;
684};
685
686struct perf_ns_link_info {
687 __u64 dev;
688 __u64 ino;
689};
690
691enum {
692 NET_NS_INDEX = 0,
693 UTS_NS_INDEX = 1,
694 IPC_NS_INDEX = 2,
695 PID_NS_INDEX = 3,
696 USER_NS_INDEX = 4,
697 MNT_NS_INDEX = 5,
698 CGROUP_NS_INDEX = 6,
699
700 NR_NAMESPACES, /* number of available namespaces */
701};
702
703enum perf_event_type {
704
705 /*
706 * If perf_event_attr.sample_id_all is set then all event types will
707 * have the sample_type selected fields related to where/when
708 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
709 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
710 * just after the perf_event_header and the fields already present for
711 * the existing fields, i.e. at the end of the payload. That way a newer
712 * perf.data file will be supported by older perf tools, with these new
713 * optional fields being ignored.
714 *
715 * struct sample_id {
716 * { u32 pid, tid; } && PERF_SAMPLE_TID
717 * { u64 time; } && PERF_SAMPLE_TIME
718 * { u64 id; } && PERF_SAMPLE_ID
719 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
720 * { u32 cpu, res; } && PERF_SAMPLE_CPU
721 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
722 * } && perf_event_attr::sample_id_all
723 *
724 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
725 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
726 * relative to header.size.
727 */
728
729 /*
730 * The MMAP events record the PROT_EXEC mappings so that we can
731 * correlate userspace IPs to code. They have the following structure:
732 *
733 * struct {
734 * struct perf_event_header header;
735 *
736 * u32 pid, tid;
737 * u64 addr;
738 * u64 len;
739 * u64 pgoff;
740 * char filename[];
741 * struct sample_id sample_id;
742 * };
743 */
744 PERF_RECORD_MMAP = 1,
745
746 /*
747 * struct {
748 * struct perf_event_header header;
749 * u64 id;
750 * u64 lost;
751 * struct sample_id sample_id;
752 * };
753 */
754 PERF_RECORD_LOST = 2,
755
756 /*
757 * struct {
758 * struct perf_event_header header;
759 *
760 * u32 pid, tid;
761 * char comm[];
762 * struct sample_id sample_id;
763 * };
764 */
765 PERF_RECORD_COMM = 3,
766
767 /*
768 * struct {
769 * struct perf_event_header header;
770 * u32 pid, ppid;
771 * u32 tid, ptid;
772 * u64 time;
773 * struct sample_id sample_id;
774 * };
775 */
776 PERF_RECORD_EXIT = 4,
777
778 /*
779 * struct {
780 * struct perf_event_header header;
781 * u64 time;
782 * u64 id;
783 * u64 stream_id;
784 * struct sample_id sample_id;
785 * };
786 */
787 PERF_RECORD_THROTTLE = 5,
788 PERF_RECORD_UNTHROTTLE = 6,
789
790 /*
791 * struct {
792 * struct perf_event_header header;
793 * u32 pid, ppid;
794 * u32 tid, ptid;
795 * u64 time;
796 * struct sample_id sample_id;
797 * };
798 */
799 PERF_RECORD_FORK = 7,
800
801 /*
802 * struct {
803 * struct perf_event_header header;
804 * u32 pid, tid;
805 *
806 * struct read_format values;
807 * struct sample_id sample_id;
808 * };
809 */
810 PERF_RECORD_READ = 8,
811
812 /*
813 * struct {
814 * struct perf_event_header header;
815 *
816 * #
817 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
818 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
819 * # is fixed relative to header.
820 * #
821 *
822 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
823 * { u64 ip; } && PERF_SAMPLE_IP
824 * { u32 pid, tid; } && PERF_SAMPLE_TID
825 * { u64 time; } && PERF_SAMPLE_TIME
826 * { u64 addr; } && PERF_SAMPLE_ADDR
827 * { u64 id; } && PERF_SAMPLE_ID
828 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
829 * { u32 cpu, res; } && PERF_SAMPLE_CPU
830 * { u64 period; } && PERF_SAMPLE_PERIOD
831 *
832 * { struct read_format values; } && PERF_SAMPLE_READ
833 *
834 * { u64 nr,
835 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
836 *
837 * #
838 * # The RAW record below is opaque data wrt the ABI
839 * #
840 * # That is, the ABI doesn't make any promises wrt to
841 * # the stability of its content, it may vary depending
842 * # on event, hardware, kernel version and phase of
843 * # the moon.
844 * #
845 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
846 * #
847 *
848 * { u32 size;
849 * char data[size];}&& PERF_SAMPLE_RAW
850 *
851 * { u64 nr;
852 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
853 *
854 * { u64 abi; # enum perf_sample_regs_abi
855 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
856 *
857 * { u64 size;
858 * char data[size];
859 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
860 *
861 * { u64 weight; } && PERF_SAMPLE_WEIGHT
862 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
863 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
864 * { u64 abi; # enum perf_sample_regs_abi
865 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
866 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
867 * };
868 */
869 PERF_RECORD_SAMPLE = 9,
870
871 /*
872 * The MMAP2 records are an augmented version of MMAP, they add
873 * maj, min, ino numbers to be used to uniquely identify each mapping
874 *
875 * struct {
876 * struct perf_event_header header;
877 *
878 * u32 pid, tid;
879 * u64 addr;
880 * u64 len;
881 * u64 pgoff;
882 * u32 maj;
883 * u32 min;
884 * u64 ino;
885 * u64 ino_generation;
886 * u32 prot, flags;
887 * char filename[];
888 * struct sample_id sample_id;
889 * };
890 */
891 PERF_RECORD_MMAP2 = 10,
892
893 /*
894 * Records that new data landed in the AUX buffer part.
895 *
896 * struct {
897 * struct perf_event_header header;
898 *
899 * u64 aux_offset;
900 * u64 aux_size;
901 * u64 flags;
902 * struct sample_id sample_id;
903 * };
904 */
905 PERF_RECORD_AUX = 11,
906
907 /*
908 * Indicates that instruction trace has started
909 *
910 * struct {
911 * struct perf_event_header header;
912 * u32 pid;
913 * u32 tid;
914 * struct sample_id sample_id;
915 * };
916 */
917 PERF_RECORD_ITRACE_START = 12,
918
919 /*
920 * Records the dropped/lost sample number.
921 *
922 * struct {
923 * struct perf_event_header header;
924 *
925 * u64 lost;
926 * struct sample_id sample_id;
927 * };
928 */
929 PERF_RECORD_LOST_SAMPLES = 13,
930
931 /*
932 * Records a context switch in or out (flagged by
933 * PERF_RECORD_MISC_SWITCH_OUT). See also
934 * PERF_RECORD_SWITCH_CPU_WIDE.
935 *
936 * struct {
937 * struct perf_event_header header;
938 * struct sample_id sample_id;
939 * };
940 */
941 PERF_RECORD_SWITCH = 14,
942
943 /*
944 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
945 * next_prev_tid that are the next (switching out) or previous
946 * (switching in) pid/tid.
947 *
948 * struct {
949 * struct perf_event_header header;
950 * u32 next_prev_pid;
951 * u32 next_prev_tid;
952 * struct sample_id sample_id;
953 * };
954 */
955 PERF_RECORD_SWITCH_CPU_WIDE = 15,
956
957 /*
958 * struct {
959 * struct perf_event_header header;
960 * u32 pid;
961 * u32 tid;
962 * u64 nr_namespaces;
963 * { u64 dev, inode; } [nr_namespaces];
964 * struct sample_id sample_id;
965 * };
966 */
967 PERF_RECORD_NAMESPACES = 16,
968
969 /*
970 * Record ksymbol register/unregister events:
971 *
972 * struct {
973 * struct perf_event_header header;
974 * u64 addr;
975 * u32 len;
976 * u16 ksym_type;
977 * u16 flags;
978 * char name[];
979 * struct sample_id sample_id;
980 * };
981 */
982 PERF_RECORD_KSYMBOL = 17,
983
984 /*
985 * Record bpf events:
986 * enum perf_bpf_event_type {
987 * PERF_BPF_EVENT_UNKNOWN = 0,
988 * PERF_BPF_EVENT_PROG_LOAD = 1,
989 * PERF_BPF_EVENT_PROG_UNLOAD = 2,
990 * };
991 *
992 * struct {
993 * struct perf_event_header header;
994 * u16 type;
995 * u16 flags;
996 * u32 id;
997 * u8 tag[BPF_TAG_SIZE];
998 * struct sample_id sample_id;
999 * };
1000 */
1001 PERF_RECORD_BPF_EVENT = 18,
1002
1003 PERF_RECORD_MAX, /* non-ABI */
1004};
1005
1006enum perf_record_ksymbol_type {
1007 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,
1008 PERF_RECORD_KSYMBOL_TYPE_BPF = 1,
1009 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */
1010};
1011
1012#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0)
1013
1014enum perf_bpf_event_type {
1015 PERF_BPF_EVENT_UNKNOWN = 0,
1016 PERF_BPF_EVENT_PROG_LOAD = 1,
1017 PERF_BPF_EVENT_PROG_UNLOAD = 2,
1018 PERF_BPF_EVENT_MAX, /* non-ABI */
1019};
1020
1021#define PERF_MAX_STACK_DEPTH 127
1022#define PERF_MAX_CONTEXTS_PER_STACK 8
1023
1024enum perf_callchain_context {
1025 PERF_CONTEXT_HV = (__u64)-32,
1026 PERF_CONTEXT_KERNEL = (__u64)-128,
1027 PERF_CONTEXT_USER = (__u64)-512,
1028
1029 PERF_CONTEXT_GUEST = (__u64)-2048,
1030 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
1031 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
1032
1033 PERF_CONTEXT_MAX = (__u64)-4095,
1034};
1035
1036/**
1037 * PERF_RECORD_AUX::flags bits
1038 */
1039#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
1040#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
1041#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
1042#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
1043
1044#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
1045#define PERF_FLAG_FD_OUTPUT (1UL << 1)
1046#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
1047#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
1048
1049#if defined(__LITTLE_ENDIAN_BITFIELD)
1050union perf_mem_data_src {
1051 __u64 val;
1052 struct {
1053 __u64 mem_op:5, /* type of opcode */
1054 mem_lvl:14, /* memory hierarchy level */
1055 mem_snoop:5, /* snoop mode */
1056 mem_lock:2, /* lock instr */
1057 mem_dtlb:7, /* tlb access */
1058 mem_lvl_num:4, /* memory hierarchy level number */
1059 mem_remote:1, /* remote */
1060 mem_snoopx:2, /* snoop mode, ext */
1061 mem_rsvd:24;
1062 };
1063};
1064#elif defined(__BIG_ENDIAN_BITFIELD)
1065union perf_mem_data_src {
1066 __u64 val;
1067 struct {
1068 __u64 mem_rsvd:24,
1069 mem_snoopx:2, /* snoop mode, ext */
1070 mem_remote:1, /* remote */
1071 mem_lvl_num:4, /* memory hierarchy level number */
1072 mem_dtlb:7, /* tlb access */
1073 mem_lock:2, /* lock instr */
1074 mem_snoop:5, /* snoop mode */
1075 mem_lvl:14, /* memory hierarchy level */
1076 mem_op:5; /* type of opcode */
1077 };
1078};
1079#else
1080#error "Unknown endianness"
1081#endif
1082
1083/* type of opcode (load/store/prefetch,code) */
1084#define PERF_MEM_OP_NA 0x01 /* not available */
1085#define PERF_MEM_OP_LOAD 0x02 /* load instruction */
1086#define PERF_MEM_OP_STORE 0x04 /* store instruction */
1087#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
1088#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
1089#define PERF_MEM_OP_SHIFT 0
1090
1091/* memory hierarchy (memory level, hit or miss) */
1092#define PERF_MEM_LVL_NA 0x01 /* not available */
1093#define PERF_MEM_LVL_HIT 0x02 /* hit level */
1094#define PERF_MEM_LVL_MISS 0x04 /* miss level */
1095#define PERF_MEM_LVL_L1 0x08 /* L1 */
1096#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
1097#define PERF_MEM_LVL_L2 0x20 /* L2 */
1098#define PERF_MEM_LVL_L3 0x40 /* L3 */
1099#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
1100#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
1101#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
1102#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
1103#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
1104#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1105#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1106#define PERF_MEM_LVL_SHIFT 5
1107
1108#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */
1109#define PERF_MEM_REMOTE_SHIFT 37
1110
1111#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */
1112#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
1113#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1114#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1115/* 5-0xa available */
1116#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1117#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
1118#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
1119#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */
1120#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */
1121
1122#define PERF_MEM_LVLNUM_SHIFT 33
1123
1124/* snoop mode */
1125#define PERF_MEM_SNOOP_NA 0x01 /* not available */
1126#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
1127#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
1128#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
1129#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
1130#define PERF_MEM_SNOOP_SHIFT 19
1131
1132#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */
1133/* 1 free */
1134#define PERF_MEM_SNOOPX_SHIFT 38
1135
1136/* locked instruction */
1137#define PERF_MEM_LOCK_NA 0x01 /* not available */
1138#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
1139#define PERF_MEM_LOCK_SHIFT 24
1140
1141/* TLB access */
1142#define PERF_MEM_TLB_NA 0x01 /* not available */
1143#define PERF_MEM_TLB_HIT 0x02 /* hit level */
1144#define PERF_MEM_TLB_MISS 0x04 /* miss level */
1145#define PERF_MEM_TLB_L1 0x08 /* L1 */
1146#define PERF_MEM_TLB_L2 0x10 /* L2 */
1147#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
1148#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
1149#define PERF_MEM_TLB_SHIFT 26
1150
1151#define PERF_MEM_S(a, s) \
1152 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1153
1154/*
1155 * single taken branch record layout:
1156 *
1157 * from: source instruction (may not always be a branch insn)
1158 * to: branch target
1159 * mispred: branch target was mispredicted
1160 * predicted: branch target was predicted
1161 *
1162 * support for mispred, predicted is optional. In case it
1163 * is not supported mispred = predicted = 0.
1164 *
1165 * in_tx: running in a hardware transaction
1166 * abort: aborting a hardware transaction
1167 * cycles: cycles from last branch (or 0 if not supported)
1168 * type: branch type
1169 */
1170struct perf_branch_entry {
1171 __u64 from;
1172 __u64 to;
1173 __u64 mispred:1, /* target mispredicted */
1174 predicted:1,/* target predicted */
1175 in_tx:1, /* in transaction */
1176 abort:1, /* transaction abort */
1177 cycles:16, /* cycle count to last branch */
1178 type:4, /* branch type */
1179 reserved:40;
1180};
1181
1182#endif /* _LINUX_PERF_EVENT_H */
1183

source code of include/linux/perf_event.h