1//===-- x86_64 floating point env manipulation functions --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H
10#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H
11
12#include "src/__support/macros/attributes.h" // LIBC_INLINE
13#include "src/__support/macros/properties/architectures.h"
14
15#if !defined(LIBC_TARGET_ARCH_IS_X86)
16#error "Invalid include"
17#endif
18
19#include <stdint.h>
20
21#include "hdr/types/fenv_t.h"
22#include "src/__support/macros/sanitizer.h"
23
24namespace LIBC_NAMESPACE {
25namespace fputil {
26
27namespace internal {
28
29// Normally, one should be able to define FE_* macros to the exact rounding mode
30// encodings. However, since we want LLVM libc to be compiled against headers
31// from other libcs, we cannot assume that FE_* macros are always defined in
32// such a manner. So, we will define enums corresponding to the x86_64 bit
33// encodings. The implementations can map from FE_* to the corresponding enum
34// values.
35
36// The rounding control values in the x87 control register and the MXCSR
37// register have the same 2-bit enoding but have different bit positions.
38// See below for the bit positions.
39struct RoundingControlValue {
40 static constexpr uint16_t TO_NEAREST = 0x0;
41 static constexpr uint16_t DOWNWARD = 0x1;
42 static constexpr uint16_t UPWARD = 0x2;
43 static constexpr uint16_t TOWARD_ZERO = 0x3;
44};
45
46static constexpr uint16_t X87_ROUNDING_CONTROL_BIT_POSITION = 10;
47static constexpr uint16_t MXCSR_ROUNDING_CONTROL_BIT_POSITION = 13;
48
49// The exception flags in the x87 status register and the MXCSR have the same
50// encoding as well as the same bit positions.
51struct ExceptionFlags {
52 static constexpr uint16_t INVALID_F = 0x1;
53 // Some libcs define __FE_DENORM corresponding to the denormal input
54 // exception and include it in FE_ALL_EXCEPTS. We define and use it to
55 // support compiling against headers provided by such libcs.
56 static constexpr uint16_t DENORMAL_F = 0x2;
57 static constexpr uint16_t DIV_BY_ZERO_F = 0x4;
58 static constexpr uint16_t OVERFLOW_F = 0x8;
59 static constexpr uint16_t UNDERFLOW_F = 0x10;
60 static constexpr uint16_t INEXACT_F = 0x20;
61};
62
63// The exception control bits occupy six bits, one bit for each exception.
64// In the x87 control word, they occupy the first 6 bits. In the MXCSR
65// register, they occupy bits 7 to 12.
66static constexpr uint16_t X87_EXCEPTION_CONTROL_BIT_POSITION = 0;
67static constexpr uint16_t X87_EXCEPTION_CONTROL_BIT_POSITION_HIGH = 24;
68static constexpr uint16_t MXCSR_EXCEPTION_CONTOL_BIT_POISTION = 7;
69
70// Exception flags are individual bits in the corresponding registers.
71// So, we just OR the bit values to get the full set of exceptions.
72LIBC_INLINE uint16_t get_status_value_for_except(int excepts) {
73 // We will make use of the fact that exception control bits are single
74 // bit flags in the control registers.
75 return (excepts & FE_INVALID ? ExceptionFlags::INVALID_F : 0) |
76#ifdef __FE_DENORM
77 (excepts & __FE_DENORM ? ExceptionFlags::DENORMAL_F : 0) |
78#endif // __FE_DENORM
79 (excepts & FE_DIVBYZERO ? ExceptionFlags::DIV_BY_ZERO_F : 0) |
80 (excepts & FE_OVERFLOW ? ExceptionFlags::OVERFLOW_F : 0) |
81 (excepts & FE_UNDERFLOW ? ExceptionFlags::UNDERFLOW_F : 0) |
82 (excepts & FE_INEXACT ? ExceptionFlags::INEXACT_F : 0);
83}
84
85LIBC_INLINE int exception_status_to_macro(uint16_t status) {
86 return (status & ExceptionFlags::INVALID_F ? FE_INVALID : 0) |
87#ifdef __FE_DENORM
88 (status & ExceptionFlags::DENORMAL_F ? __FE_DENORM : 0) |
89#endif // __FE_DENORM
90 (status & ExceptionFlags::DIV_BY_ZERO_F ? FE_DIVBYZERO : 0) |
91 (status & ExceptionFlags::OVERFLOW_F ? FE_OVERFLOW : 0) |
92 (status & ExceptionFlags::UNDERFLOW_F ? FE_UNDERFLOW : 0) |
93 (status & ExceptionFlags::INEXACT_F ? FE_INEXACT : 0);
94}
95
96struct X87StateDescriptor {
97 uint16_t control_word;
98 uint16_t unused1;
99 uint16_t status_word;
100 uint16_t unused2;
101 // TODO: Elaborate the remaining 20 bytes as required.
102 uint32_t _[5];
103};
104
105LIBC_INLINE uint16_t get_x87_control_word() {
106 uint16_t w;
107 __asm__ __volatile__("fnstcw %0" : "=m"(w)::);
108 MSAN_UNPOISON(&w, sizeof(w));
109 return w;
110}
111
112LIBC_INLINE void write_x87_control_word(uint16_t w) {
113 __asm__ __volatile__("fldcw %0" : : "m"(w) :);
114}
115
116LIBC_INLINE uint16_t get_x87_status_word() {
117 uint16_t w;
118 __asm__ __volatile__("fnstsw %0" : "=m"(w)::);
119 MSAN_UNPOISON(&w, sizeof(w));
120 return w;
121}
122
123LIBC_INLINE void clear_x87_exceptions() {
124 __asm__ __volatile__("fnclex" : : :);
125}
126
127LIBC_INLINE uint32_t get_mxcsr() {
128 uint32_t w;
129 __asm__ __volatile__("stmxcsr %0" : "=m"(w)::);
130 MSAN_UNPOISON(&w, sizeof(w));
131 return w;
132}
133
134LIBC_INLINE void write_mxcsr(uint32_t w) {
135 __asm__ __volatile__("ldmxcsr %0" : : "m"(w) :);
136}
137
138LIBC_INLINE void get_x87_state_descriptor(X87StateDescriptor &s) {
139 __asm__ __volatile__("fnstenv %0" : "=m"(s));
140 MSAN_UNPOISON(&s, sizeof(s));
141}
142
143LIBC_INLINE void write_x87_state_descriptor(const X87StateDescriptor &s) {
144 __asm__ __volatile__("fldenv %0" : : "m"(s) :);
145}
146
147LIBC_INLINE void fwait() { __asm__ __volatile__("fwait"); }
148
149} // namespace internal
150
151LIBC_INLINE int enable_except(int excepts) {
152 // In the x87 control word and in MXCSR, an exception is blocked
153 // if the corresponding bit is set. That is the reason for all the
154 // bit-flip operations below as we need to turn the bits to zero
155 // to enable them.
156
157 uint16_t bit_mask = internal::get_status_value_for_except(excepts);
158
159 uint16_t x87_cw = internal::get_x87_control_word();
160 uint16_t old_excepts = ~x87_cw & 0x3F; // Save previously enabled exceptions.
161 x87_cw &= ~bit_mask;
162 internal::write_x87_control_word(w: x87_cw);
163
164 // Enabling SSE exceptions via MXCSR is a nice thing to do but
165 // might not be of much use practically as SSE exceptions and the x87
166 // exceptions are independent of each other.
167 uint32_t mxcsr = internal::get_mxcsr();
168 mxcsr &= ~(bit_mask << internal::MXCSR_EXCEPTION_CONTOL_BIT_POISTION);
169 internal::write_mxcsr(w: mxcsr);
170
171 // Since the x87 exceptions and SSE exceptions are independent of each,
172 // it doesn't make much sence to report both in the return value. Most
173 // often, the standard floating point functions deal with FPU operations
174 // so we will retrun only the old x87 exceptions.
175 return internal::exception_status_to_macro(status: old_excepts);
176}
177
178LIBC_INLINE int disable_except(int excepts) {
179 // In the x87 control word and in MXCSR, an exception is blocked
180 // if the corresponding bit is set.
181
182 uint16_t bit_mask = internal::get_status_value_for_except(excepts);
183
184 uint16_t x87_cw = internal::get_x87_control_word();
185 uint16_t old_excepts = ~x87_cw & 0x3F; // Save previously enabled exceptions.
186 x87_cw |= bit_mask;
187 internal::write_x87_control_word(w: x87_cw);
188
189 // Just like in enable_except, it is not clear if disabling SSE exceptions
190 // is required. But, we will still do it only as a "nice thing to do".
191 uint32_t mxcsr = internal::get_mxcsr();
192 mxcsr |= (bit_mask << internal::MXCSR_EXCEPTION_CONTOL_BIT_POISTION);
193 internal::write_mxcsr(w: mxcsr);
194
195 return internal::exception_status_to_macro(status: old_excepts);
196}
197
198LIBC_INLINE int get_except() {
199 uint16_t mxcsr = static_cast<uint16_t>(internal::get_mxcsr());
200 uint16_t enabled_excepts = ~(mxcsr >> 7) & 0x3F;
201 return internal::exception_status_to_macro(status: enabled_excepts);
202}
203
204LIBC_INLINE int clear_except(int excepts) {
205 internal::X87StateDescriptor state;
206 internal::get_x87_state_descriptor(s&: state);
207 state.status_word &=
208 static_cast<uint16_t>(~internal::get_status_value_for_except(excepts));
209 internal::write_x87_state_descriptor(s: state);
210
211 uint32_t mxcsr = internal::get_mxcsr();
212 mxcsr &= ~internal::get_status_value_for_except(excepts);
213 internal::write_mxcsr(w: mxcsr);
214 return 0;
215}
216
217LIBC_INLINE int test_except(int excepts) {
218 uint16_t status_word = internal::get_x87_status_word();
219 uint32_t mxcsr = internal::get_mxcsr();
220 // Check both x87 status word and MXCSR.
221 uint16_t status_value = internal::get_status_value_for_except(excepts);
222 return internal::exception_status_to_macro(
223 status: static_cast<uint16_t>(status_value & (status_word | mxcsr)));
224}
225
226// Sets the exception flags but does not trigger the exception handler.
227LIBC_INLINE int set_except(int excepts) {
228 uint16_t status_value = internal::get_status_value_for_except(excepts);
229 internal::X87StateDescriptor state;
230 internal::get_x87_state_descriptor(s&: state);
231 state.status_word |= status_value;
232 internal::write_x87_state_descriptor(s: state);
233
234 uint32_t mxcsr = internal::get_mxcsr();
235 mxcsr |= status_value;
236 internal::write_mxcsr(w: mxcsr);
237
238 return 0;
239}
240
241LIBC_INLINE int raise_except(int excepts) {
242 uint16_t status_value = internal::get_status_value_for_except(excepts);
243
244 // We set the status flag for exception one at a time and call the
245 // fwait instruction to actually get the processor to raise the
246 // exception by calling the exception handler. This scheme is per
247 // the description in "8.6 X87 FPU EXCEPTION SYNCHRONIZATION"
248 // of the "Intel 64 and IA-32 Architectures Software Developer's
249 // Manual, Vol 1".
250
251 // FPU status word is read for each exception seperately as the
252 // exception handler can potentially write to it (typically to clear
253 // the corresponding exception flag). By reading it separately, we
254 // ensure that the writes by the exception handler are maintained
255 // when raising the next exception.
256
257 auto raise_helper = [](uint16_t singleExceptFlag) {
258 internal::X87StateDescriptor state;
259 uint32_t mxcsr = 0;
260 internal::get_x87_state_descriptor(s&: state);
261 mxcsr = internal::get_mxcsr();
262 state.status_word |= singleExceptFlag;
263 mxcsr |= singleExceptFlag;
264 internal::write_x87_state_descriptor(s: state);
265 internal::write_mxcsr(w: mxcsr);
266 internal::fwait();
267 };
268
269 if (status_value & internal::ExceptionFlags::INVALID_F)
270 raise_helper(internal::ExceptionFlags::INVALID_F);
271 if (status_value & internal::ExceptionFlags::DIV_BY_ZERO_F)
272 raise_helper(internal::ExceptionFlags::DIV_BY_ZERO_F);
273 if (status_value & internal::ExceptionFlags::OVERFLOW_F)
274 raise_helper(internal::ExceptionFlags::OVERFLOW_F);
275 if (status_value & internal::ExceptionFlags::UNDERFLOW_F)
276 raise_helper(internal::ExceptionFlags::UNDERFLOW_F);
277 if (status_value & internal::ExceptionFlags::INEXACT_F)
278 raise_helper(internal::ExceptionFlags::INEXACT_F);
279#ifdef __FE_DENORM
280 if (status_value & internal::ExceptionFlags::DENORMAL_F) {
281 raise_helper(internal::ExceptionFlags::DENORMAL_F);
282 }
283#endif // __FE_DENORM
284
285 // There is no special synchronization scheme available to
286 // raise SEE exceptions. So, we will ignore that for now.
287 // Just plain writing to the MXCSR register does not guarantee
288 // the exception handler will be called.
289
290 return 0;
291}
292
293LIBC_INLINE int get_round() {
294 uint16_t bit_value =
295 (internal::get_mxcsr() >> internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION) &
296 0x3;
297 switch (bit_value) {
298 case internal::RoundingControlValue::TO_NEAREST:
299 return FE_TONEAREST;
300 case internal::RoundingControlValue::DOWNWARD:
301 return FE_DOWNWARD;
302 case internal::RoundingControlValue::UPWARD:
303 return FE_UPWARD;
304 case internal::RoundingControlValue::TOWARD_ZERO:
305 return FE_TOWARDZERO;
306 default:
307 return -1; // Error value.
308 }
309}
310
311LIBC_INLINE int set_round(int mode) {
312 uint16_t bit_value;
313 switch (mode) {
314 case FE_TONEAREST:
315 bit_value = internal::RoundingControlValue::TO_NEAREST;
316 break;
317 case FE_DOWNWARD:
318 bit_value = internal::RoundingControlValue::DOWNWARD;
319 break;
320 case FE_UPWARD:
321 bit_value = internal::RoundingControlValue::UPWARD;
322 break;
323 case FE_TOWARDZERO:
324 bit_value = internal::RoundingControlValue::TOWARD_ZERO;
325 break;
326 default:
327 return 1; // To indicate failure
328 }
329
330 uint16_t x87_value = static_cast<uint16_t>(
331 bit_value << internal::X87_ROUNDING_CONTROL_BIT_POSITION);
332 uint16_t x87_control = internal::get_x87_control_word();
333 x87_control = static_cast<uint16_t>(
334 (x87_control &
335 ~(uint16_t(0x3) << internal::X87_ROUNDING_CONTROL_BIT_POSITION)) |
336 x87_value);
337 internal::write_x87_control_word(w: x87_control);
338
339 uint32_t mxcsr_value = bit_value
340 << internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION;
341 uint32_t mxcsr_control = internal::get_mxcsr();
342 mxcsr_control = (mxcsr_control &
343 ~(0x3 << internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION)) |
344 mxcsr_value;
345 internal::write_mxcsr(w: mxcsr_control);
346
347 return 0;
348}
349
350namespace internal {
351
352#if defined(_WIN32)
353// MSVC fenv.h defines a very simple representation of the floating point state
354// which just consists of control and status words of the x87 unit.
355struct FPState {
356 uint32_t control_word;
357 uint32_t status_word;
358};
359#elif defined(__APPLE__)
360struct FPState {
361 uint16_t control_word;
362 uint16_t status_word;
363 uint32_t mxcsr;
364 uint8_t reserved[8];
365};
366#else
367struct FPState {
368 X87StateDescriptor x87_status;
369 uint32_t mxcsr;
370};
371#endif // _WIN32
372
373} // namespace internal
374
375static_assert(
376 sizeof(fenv_t) == sizeof(internal::FPState),
377 "Internal floating point state does not match the public fenv_t type.");
378
379#ifdef _WIN32
380
381// The exception flags in the Windows FEnv struct and the MXCSR have almost
382// reversed bit positions.
383struct WinExceptionFlags {
384 static constexpr uint32_t INEXACT_WIN = 0x01;
385 static constexpr uint32_t UNDERFLOW_WIN = 0x02;
386 static constexpr uint32_t OVERFLOW_WIN = 0x04;
387 static constexpr uint32_t DIV_BY_ZERO_WIN = 0x08;
388 static constexpr uint32_t INVALID_WIN = 0x10;
389 static constexpr uint32_t DENORMAL_WIN = 0x20;
390
391 // The Windows FEnv struct has a second copy of all of these bits in the high
392 // byte of the 32 bit control word. These are used as the source of truth when
393 // calling fesetenv.
394 static constexpr uint32_t HIGH_OFFSET = 24;
395
396 static constexpr uint32_t HIGH_INEXACT = INEXACT_WIN << HIGH_OFFSET;
397 static constexpr uint32_t HIGH_UNDERFLOW = UNDERFLOW_WIN << HIGH_OFFSET;
398 static constexpr uint32_t HIGH_OVERFLOW = OVERFLOW_WIN << HIGH_OFFSET;
399 static constexpr uint32_t HIGH_DIV_BY_ZERO = DIV_BY_ZERO_WIN << HIGH_OFFSET;
400 static constexpr uint32_t HIGH_INVALID = INVALID_WIN << HIGH_OFFSET;
401 static constexpr uint32_t HIGH_DENORMAL = DENORMAL_WIN << HIGH_OFFSET;
402};
403
404/*
405 fenv_t control word format:
406
407 Windows (at least for x64) uses a 4 byte control fenv control word stored in
408 a 32 bit integer. The first byte contains just the rounding mode and the
409 exception masks, while the last two bytes contain that same information as
410 well as the flush-to-zero and denormals-are-zero flags. The flags are
411 represented with a truth table:
412
413 00 - No flags set
414 01 - Flush-to-zero and Denormals-are-zero set
415 11 - Flush-to-zero set
416 10 - Denormals-are-zero set
417
418 U represents unused.
419
420 +-----Rounding Mode-----+
421 | |
422 ++ ++
423 || ||
424 RRMMMMMM UUUUUUUU UUUUFFRR UUMMMMMM
425 | | || | |
426 +----+ flags---++ +----+
427 | |
428 +------Exception Masks-----+
429
430
431 fenv_t status word format:
432
433 The status word is a lot simpler for this conversion, since only the
434 exception flags are used in the MXCSR.
435
436 +----+---Exception Flags---+----+
437 | | | |
438 UUEEEEEE UUUUUUUU UUUUUUUU UUEEEEEE
439
440
441
442 MXCSR Format:
443
444 The MXCSR format is the same information, just organized differently. Since
445 the fenv_t struct for windows doesn't include the mxcsr bits, they must be
446 generated from the control word bits.
447
448 Exception Masks---+ +---Exception Flags
449 | |
450 Flush-to-zero---+ +----+ +----+
451 | | | | |
452 FRRMMMMMMDEEEEEE
453 || |
454 ++ +---Denormals-are-zero
455 |
456 +---Rounding Mode
457
458
459 The mask and flag order is as follows:
460
461 fenv_t mxcsr
462
463 denormal inexact
464 invalid underflow
465 div by 0 overflow
466 overflow div by 0
467 underflow denormal
468 inexact invalid
469
470 This is almost reverse, except for denormal and invalid which are in the
471 same order in both.
472 */
473
474LIBC_INLINE int get_env(fenv_t *envp) {
475 internal::FPState *state = reinterpret_cast<internal::FPState *>(envp);
476
477 uint32_t status_word = 0;
478 uint32_t control_word = 0;
479
480 uint32_t mxcsr = internal::get_mxcsr();
481
482 // Set exception flags in the status word
483 status_word |= (mxcsr & (internal::ExceptionFlags::INVALID_F |
484 internal::ExceptionFlags::DENORMAL_F))
485 << 4;
486 status_word |= (mxcsr & internal::ExceptionFlags::DIV_BY_ZERO_F) << 1;
487 status_word |= (mxcsr & internal::ExceptionFlags::OVERFLOW_F) >> 1;
488 status_word |= (mxcsr & internal::ExceptionFlags::UNDERFLOW_F) >> 3;
489 status_word |= (mxcsr & internal::ExceptionFlags::INEXACT_F) >> 5;
490 status_word |= status_word << WinExceptionFlags::HIGH_OFFSET;
491
492 // Set exception masks in bits 0-5 and 24-29
493 control_word |= (mxcsr & ((internal::ExceptionFlags::INVALID_F |
494 internal::ExceptionFlags::DENORMAL_F)
495 << 7)) >>
496 3;
497 control_word |= (mxcsr & (internal::ExceptionFlags::DIV_BY_ZERO_F << 7)) >> 6;
498 control_word |= (mxcsr & (internal::ExceptionFlags::OVERFLOW_F << 7)) >> 8;
499 control_word |= (mxcsr & (internal::ExceptionFlags::UNDERFLOW_F << 7)) >> 10;
500 control_word |= (mxcsr & (internal::ExceptionFlags::INEXACT_F << 7)) >> 12;
501 control_word |= control_word << WinExceptionFlags::HIGH_OFFSET;
502
503 // Set rounding in bits 8-9 and 30-31
504 control_word |= (mxcsr & 0x6000) >> 5;
505 control_word |= (mxcsr & 0x6000) << 17;
506
507 // Set flush-to-zero in bit 10
508 control_word |= (mxcsr & 0x8000) >> 5;
509
510 // Set denormals-are-zero xor flush-to-zero in bit 11
511 control_word |= (((mxcsr & 0x8000) >> 9) ^ (mxcsr & 0x0040)) << 5;
512
513 state->control_word = control_word;
514 state->status_word = status_word;
515 return 0;
516}
517
518LIBC_INLINE int set_env(const fenv_t *envp) {
519 const internal::FPState *state =
520 reinterpret_cast<const internal::FPState *>(envp);
521
522 uint32_t mxcsr = 0;
523
524 // Set exception flags from the status word
525 mxcsr |= static_cast<uint16_t>(
526 (state->status_word &
527 (WinExceptionFlags::HIGH_DENORMAL | WinExceptionFlags::HIGH_INVALID)) >>
528 28);
529 mxcsr |= static_cast<uint16_t>(
530 (state->status_word & WinExceptionFlags::HIGH_DIV_BY_ZERO) >> 25);
531 mxcsr |= static_cast<uint16_t>(
532 (state->status_word & WinExceptionFlags::HIGH_OVERFLOW) >> 23);
533 mxcsr |= static_cast<uint16_t>(
534 (state->status_word & WinExceptionFlags::HIGH_UNDERFLOW) >> 21);
535 mxcsr |= static_cast<uint16_t>(
536 (state->status_word & WinExceptionFlags::HIGH_INEXACT) >> 19);
537
538 // Set denormals-are-zero from bit 10 xor bit 11
539 mxcsr |= static_cast<uint16_t>(
540 (((state->control_word & 0x800) >> 1) ^ (state->control_word & 0x400)) >>
541 4);
542
543 // Set exception masks from bits 24-29
544 mxcsr |= static_cast<uint16_t>(
545 (state->control_word &
546 (WinExceptionFlags::HIGH_DENORMAL | WinExceptionFlags::HIGH_INVALID)) >>
547 21);
548 mxcsr |= static_cast<uint16_t>(
549 (state->control_word & WinExceptionFlags::HIGH_DIV_BY_ZERO) >> 18);
550 mxcsr |= static_cast<uint16_t>(
551 (state->control_word & WinExceptionFlags::HIGH_OVERFLOW) >> 16);
552 mxcsr |= static_cast<uint16_t>(
553 (state->control_word & WinExceptionFlags::HIGH_UNDERFLOW) >> 14);
554 mxcsr |= static_cast<uint16_t>(
555 (state->control_word & WinExceptionFlags::HIGH_INEXACT) >> 12);
556
557 // Set rounding from bits 30-31
558 mxcsr |= static_cast<uint16_t>((state->control_word & 0xc0000000) >> 17);
559
560 // Set flush-to-zero from bit 10
561 mxcsr |= static_cast<uint16_t>((state->control_word & 0x400) << 5);
562
563 internal::write_mxcsr(mxcsr);
564 return 0;
565}
566#else
567LIBC_INLINE int get_env(fenv_t *envp) {
568 internal::FPState *state = reinterpret_cast<internal::FPState *>(envp);
569#ifdef __APPLE__
570 internal::X87StateDescriptor x87_status;
571 internal::get_x87_state_descriptor(x87_status);
572 state->control_word = x87_status.control_word;
573 state->status_word = x87_status.status_word;
574#else
575 internal::get_x87_state_descriptor(s&: state->x87_status);
576#endif // __APPLE__
577 state->mxcsr = internal::get_mxcsr();
578 return 0;
579}
580
581LIBC_INLINE int set_env(const fenv_t *envp) {
582 // envp contains everything including pieces like the current
583 // top of FPU stack. We cannot arbitrarily change them. So, we first
584 // read the current status and update only those pieces which are
585 // not disruptive.
586 internal::X87StateDescriptor x87_status;
587 internal::get_x87_state_descriptor(s&: x87_status);
588
589 if (envp == FE_DFL_ENV) {
590 // Reset the exception flags in the status word.
591 x87_status.status_word &= ~uint16_t(0x3F);
592 // Reset other non-sensitive parts of the status word.
593 for (int i = 0; i < 5; i++)
594 x87_status._[i] = 0;
595 // In the control word, we do the following:
596 // 1. Mask all exceptions
597 // 2. Set rounding mode to round-to-nearest
598 // 3. Set the internal precision to double extended precision.
599 x87_status.control_word |= uint16_t(0x3F); // Mask all exceptions.
600 x87_status.control_word &= ~(uint16_t(0x3) << 10); // Round to nearest.
601 x87_status.control_word |= (uint16_t(0x3) << 8); // Extended precision.
602 internal::write_x87_state_descriptor(s: x87_status);
603
604 // We take the exact same approach MXCSR register as well.
605 // MXCSR has two additional fields, "flush-to-zero" and
606 // "denormals-are-zero". We reset those bits. Also, MXCSR does not
607 // have a field which controls the precision of internal operations.
608 uint32_t mxcsr = internal::get_mxcsr();
609 mxcsr &= ~uint16_t(0x3F); // Clear exception flags.
610 mxcsr &= ~(uint16_t(0x1) << 6); // Reset denormals-are-zero
611 mxcsr |= (uint16_t(0x3F) << 7); // Mask exceptions
612 mxcsr &= ~(uint16_t(0x3) << 13); // Round to nearest.
613 mxcsr &= ~(uint16_t(0x1) << 15); // Reset flush-to-zero
614 internal::write_mxcsr(w: mxcsr);
615
616 return 0;
617 }
618
619 const internal::FPState *fpstate =
620 reinterpret_cast<const internal::FPState *>(envp);
621
622 // Copy the exception status flags from envp.
623 x87_status.status_word &= ~uint16_t(0x3F);
624#ifdef __APPLE__
625 x87_status.status_word |= (fpstate->status_word & 0x3F);
626 // We can set the x87 control word as is as there no sensitive bits.
627 x87_status.control_word = fpstate->control_word;
628#else
629 x87_status.status_word |= (fpstate->x87_status.status_word & 0x3F);
630 // Copy other non-sensitive parts of the status word.
631 for (int i = 0; i < 5; i++)
632 x87_status._[i] = fpstate->x87_status._[i];
633 // We can set the x87 control word as is as there no sensitive bits.
634 x87_status.control_word = fpstate->x87_status.control_word;
635#endif // __APPLE__
636 internal::write_x87_state_descriptor(s: x87_status);
637
638 // We can write the MXCSR state as is as there are no sensitive bits.
639 internal::write_mxcsr(w: fpstate->mxcsr);
640 return 0;
641}
642#endif
643
644} // namespace fputil
645} // namespace LIBC_NAMESPACE
646
647#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H
648

source code of libc/src/__support/FPUtil/x86_64/FEnvImpl.h