1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// Check that the PowerPC vector registers are restored properly during
10// unwinding. Option -mabi=vec-extabi is required to compile the test case.
11
12// REQUIRES: target={{.+}}-aix{{.*}}
13// ADDITIONAL_COMPILE_FLAGS: -mabi=vec-extabi
14// UNSUPPORTED: no-exceptions
15
16// AIX does not support the eh_frame section. Instead, the traceback table
17// located at the end of each function provides the information for stack
18// unwinding. Non-volatile GRs, FRs, and VRs clobbered by the function are
19// saved on the stack and the numbers of saved registers are available in the
20// traceback table. Registers are saved from high number to low consecutively,
21// e.g., if n VRs are saved, the order on the stack will be VR31, VR30, ...,
22// VR31-n+1. This test cases checks the unwinder gets to the location of saved
23// VRs which should be 16-byte aligned and restores them correctly based on
24// the number specified in the traceback table. To simplify, only the 2 high
25// numbered VRs are checked. Because PowerPC CPUs do not have instructions to
26// assign a literal value to a VR directly until Power10, and the instructions
27// to assign to a VR from a GR and vice versa are not available until Power8,
28// vector instructions available on Power7 are used to facilitate the test
29// so that it can run on all supported PowerPC architectures. In the code
30// below, VR31 is equivalent to VS63, VR30 is equivalent to VS62 (see PowerPC
31// documents for details).
32//
33
34#include <cstdlib>
35#include <cassert>
36
37int __attribute__((noinline)) test2(int i)
38{
39 if (i > 3)
40 throw i;
41 srand(seed: i);
42 return rand();
43}
44
45int __attribute__((noinline)) test(int i) {
46 // Clobber VS63 and VS62 in the function body.
47 // Set VS63 to 16 bytes each with value 9
48 asm volatile("vspltisb 31, 9" : : : "v31");
49
50 // Set VS62 to 16 bytes each with value 12
51 asm volatile("vspltisb 30, 12" : : : "v30");
52 return test2(i);
53}
54#define cmpVS63(vec, result) \
55 { \
56 vector unsigned char gbg; \
57 asm volatile("vcmpequb. %[gbg], 31, %[veca];" \
58 "mfocrf %[res], 2;" \
59 "rlwinm %[res], %[res], 25, 31, 31" \
60 : [res] "=r"(result), [gbg] "=v"(gbg) \
61 : [veca] "v"(vec) \
62 : "cr6"); \
63 }
64
65#define cmpVS62(vec, result) \
66 { \
67 vector unsigned char gbg; \
68 asm volatile("vcmpequb. %[gbg], 30, %[veca];" \
69 "mfocrf %[res], 2;" \
70 "rlwinm %[res], %[res], 25, 31, 31" \
71 : [res] "=r"(result), [gbg] "=v"(gbg) \
72 : [veca] "v"(vec) \
73 : "cr6"); \
74 }
75int main(int, char**) {
76 // Set VS63 to 16 bytes each with value 1
77 asm volatile("vspltisb 31, 1" : : : "v31");
78
79 // Set VS62 to 16 bytes each with value 2
80 asm volatile("vspltisb 30, 2" : : : "v30");
81 vector unsigned long long expectedVS63Value = {0x101010101010101, 0x101010101010101};
82 vector unsigned long long expectedVS62Value = {0x202020202020202, 0x202020202020202};
83 try {
84 test(i: 4);
85 } catch (int num) {
86 // If the unwinder restores VS63 and VS62 correctly, they should contain
87 // 0x01's and 0x02's respectively instead of 0x09's and 0x12's.
88 bool isEqualVS63, isEqualVS62;
89 cmpVS63(expectedVS63Value, isEqualVS63);
90 cmpVS62(expectedVS62Value, isEqualVS62);
91 assert(isEqualVS63 && isEqualVS62);
92 }
93 return 0;
94}
95

source code of libcxxabi/test/vendor/ibm/vec_reg_restore.pass.cpp