1//===- Chunks.cpp ---------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "Chunks.h"
10#include "COFFLinkerContext.h"
11#include "InputFiles.h"
12#include "SymbolTable.h"
13#include "Symbols.h"
14#include "Writer.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/Twine.h"
18#include "llvm/BinaryFormat/COFF.h"
19#include "llvm/Object/COFF.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/Endian.h"
22#include "llvm/Support/raw_ostream.h"
23#include <algorithm>
24#include <iterator>
25
26using namespace llvm;
27using namespace llvm::object;
28using namespace llvm::support::endian;
29using namespace llvm::COFF;
30using llvm::support::ulittle32_t;
31
32namespace lld::coff {
33
34SectionChunk::SectionChunk(ObjFile *f, const coff_section *h)
35 : Chunk(SectionKind), file(f), header(h), repl(this) {
36 // Initialize relocs.
37 if (file)
38 setRelocs(file->getCOFFObj()->getRelocations(Sec: header));
39
40 // Initialize sectionName.
41 StringRef sectionName;
42 if (file) {
43 if (Expected<StringRef> e = file->getCOFFObj()->getSectionName(Sec: header))
44 sectionName = *e;
45 }
46 sectionNameData = sectionName.data();
47 sectionNameSize = sectionName.size();
48
49 setAlignment(header->getAlignment());
50
51 hasData = !(header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
52
53 // If linker GC is disabled, every chunk starts out alive. If linker GC is
54 // enabled, treat non-comdat sections as roots. Generally optimized object
55 // files will be built with -ffunction-sections or /Gy, so most things worth
56 // stripping will be in a comdat.
57 if (file)
58 live = !file->ctx.config.doGC || !isCOMDAT();
59 else
60 live = true;
61}
62
63// SectionChunk is one of the most frequently allocated classes, so it is
64// important to keep it as compact as possible. As of this writing, the number
65// below is the size of this class on x64 platforms.
66static_assert(sizeof(SectionChunk) <= 88, "SectionChunk grew unexpectedly");
67
68static void add16(uint8_t *p, int16_t v) { write16le(P: p, V: read16le(P: p) + v); }
69static void add32(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) + v); }
70static void add64(uint8_t *p, int64_t v) { write64le(P: p, V: read64le(P: p) + v); }
71static void or16(uint8_t *p, uint16_t v) { write16le(P: p, V: read16le(P: p) | v); }
72static void or32(uint8_t *p, uint32_t v) { write32le(P: p, V: read32le(P: p) | v); }
73
74// Verify that given sections are appropriate targets for SECREL
75// relocations. This check is relaxed because unfortunately debug
76// sections have section-relative relocations against absolute symbols.
77static bool checkSecRel(const SectionChunk *sec, OutputSection *os) {
78 if (os)
79 return true;
80 if (sec->isCodeView())
81 return false;
82 error(msg: "SECREL relocation cannot be applied to absolute symbols");
83 return false;
84}
85
86static void applySecRel(const SectionChunk *sec, uint8_t *off,
87 OutputSection *os, uint64_t s) {
88 if (!checkSecRel(sec, os))
89 return;
90 uint64_t secRel = s - os->getRVA();
91 if (secRel > UINT32_MAX) {
92 error(msg: "overflow in SECREL relocation in section: " + sec->getSectionName());
93 return;
94 }
95 add32(p: off, v: secRel);
96}
97
98static void applySecIdx(uint8_t *off, OutputSection *os,
99 unsigned numOutputSections) {
100 // numOutputSections is the largest valid section index. Make sure that
101 // it fits in 16 bits.
102 assert(numOutputSections <= 0xffff && "size of outputSections is too big");
103
104 // Absolute symbol doesn't have section index, but section index relocation
105 // against absolute symbol should be resolved to one plus the last output
106 // section index. This is required for compatibility with MSVC.
107 if (os)
108 add16(p: off, v: os->sectionIndex);
109 else
110 add16(p: off, v: numOutputSections + 1);
111}
112
113void SectionChunk::applyRelX64(uint8_t *off, uint16_t type, OutputSection *os,
114 uint64_t s, uint64_t p,
115 uint64_t imageBase) const {
116 switch (type) {
117 case IMAGE_REL_AMD64_ADDR32:
118 add32(p: off, v: s + imageBase);
119 break;
120 case IMAGE_REL_AMD64_ADDR64:
121 add64(p: off, v: s + imageBase);
122 break;
123 case IMAGE_REL_AMD64_ADDR32NB: add32(p: off, v: s); break;
124 case IMAGE_REL_AMD64_REL32: add32(p: off, v: s - p - 4); break;
125 case IMAGE_REL_AMD64_REL32_1: add32(p: off, v: s - p - 5); break;
126 case IMAGE_REL_AMD64_REL32_2: add32(p: off, v: s - p - 6); break;
127 case IMAGE_REL_AMD64_REL32_3: add32(p: off, v: s - p - 7); break;
128 case IMAGE_REL_AMD64_REL32_4: add32(p: off, v: s - p - 8); break;
129 case IMAGE_REL_AMD64_REL32_5: add32(p: off, v: s - p - 9); break;
130 case IMAGE_REL_AMD64_SECTION:
131 applySecIdx(off, os, numOutputSections: file->ctx.outputSections.size());
132 break;
133 case IMAGE_REL_AMD64_SECREL: applySecRel(sec: this, off, os, s); break;
134 default:
135 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
136 toString(file));
137 }
138}
139
140void SectionChunk::applyRelX86(uint8_t *off, uint16_t type, OutputSection *os,
141 uint64_t s, uint64_t p,
142 uint64_t imageBase) const {
143 switch (type) {
144 case IMAGE_REL_I386_ABSOLUTE: break;
145 case IMAGE_REL_I386_DIR32:
146 add32(p: off, v: s + imageBase);
147 break;
148 case IMAGE_REL_I386_DIR32NB: add32(p: off, v: s); break;
149 case IMAGE_REL_I386_REL32: add32(p: off, v: s - p - 4); break;
150 case IMAGE_REL_I386_SECTION:
151 applySecIdx(off, os, numOutputSections: file->ctx.outputSections.size());
152 break;
153 case IMAGE_REL_I386_SECREL: applySecRel(sec: this, off, os, s); break;
154 default:
155 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
156 toString(file));
157 }
158}
159
160static void applyMOV(uint8_t *off, uint16_t v) {
161 write16le(P: off, V: (read16le(P: off) & 0xfbf0) | ((v & 0x800) >> 1) | ((v >> 12) & 0xf));
162 write16le(P: off + 2, V: (read16le(P: off + 2) & 0x8f00) | ((v & 0x700) << 4) | (v & 0xff));
163}
164
165static uint16_t readMOV(uint8_t *off, bool movt) {
166 uint16_t op1 = read16le(P: off);
167 if ((op1 & 0xfbf0) != (movt ? 0xf2c0 : 0xf240))
168 error(msg: "unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
169 " instruction in MOV32T relocation");
170 uint16_t op2 = read16le(P: off + 2);
171 if ((op2 & 0x8000) != 0)
172 error(msg: "unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
173 " instruction in MOV32T relocation");
174 return (op2 & 0x00ff) | ((op2 >> 4) & 0x0700) | ((op1 << 1) & 0x0800) |
175 ((op1 & 0x000f) << 12);
176}
177
178void applyMOV32T(uint8_t *off, uint32_t v) {
179 uint16_t immW = readMOV(off, movt: false); // read MOVW operand
180 uint16_t immT = readMOV(off: off + 4, movt: true); // read MOVT operand
181 uint32_t imm = immW | (immT << 16);
182 v += imm; // add the immediate offset
183 applyMOV(off, v); // set MOVW operand
184 applyMOV(off: off + 4, v: v >> 16); // set MOVT operand
185}
186
187static void applyBranch20T(uint8_t *off, int32_t v) {
188 if (!isInt<21>(x: v))
189 error(msg: "relocation out of range");
190 uint32_t s = v < 0 ? 1 : 0;
191 uint32_t j1 = (v >> 19) & 1;
192 uint32_t j2 = (v >> 18) & 1;
193 or16(p: off, v: (s << 10) | ((v >> 12) & 0x3f));
194 or16(p: off + 2, v: (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
195}
196
197void applyBranch24T(uint8_t *off, int32_t v) {
198 if (!isInt<25>(x: v))
199 error(msg: "relocation out of range");
200 uint32_t s = v < 0 ? 1 : 0;
201 uint32_t j1 = ((~v >> 23) & 1) ^ s;
202 uint32_t j2 = ((~v >> 22) & 1) ^ s;
203 or16(p: off, v: (s << 10) | ((v >> 12) & 0x3ff));
204 // Clear out the J1 and J2 bits which may be set.
205 write16le(P: off + 2, V: (read16le(P: off + 2) & 0xd000) | (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
206}
207
208void SectionChunk::applyRelARM(uint8_t *off, uint16_t type, OutputSection *os,
209 uint64_t s, uint64_t p,
210 uint64_t imageBase) const {
211 // Pointer to thumb code must have the LSB set.
212 uint64_t sx = s;
213 if (os && (os->header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
214 sx |= 1;
215 switch (type) {
216 case IMAGE_REL_ARM_ADDR32:
217 add32(p: off, v: sx + imageBase);
218 break;
219 case IMAGE_REL_ARM_ADDR32NB: add32(p: off, v: sx); break;
220 case IMAGE_REL_ARM_MOV32T:
221 applyMOV32T(off, v: sx + imageBase);
222 break;
223 case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(off, v: sx - p - 4); break;
224 case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(off, v: sx - p - 4); break;
225 case IMAGE_REL_ARM_BLX23T: applyBranch24T(off, v: sx - p - 4); break;
226 case IMAGE_REL_ARM_SECTION:
227 applySecIdx(off, os, numOutputSections: file->ctx.outputSections.size());
228 break;
229 case IMAGE_REL_ARM_SECREL: applySecRel(sec: this, off, os, s); break;
230 case IMAGE_REL_ARM_REL32: add32(p: off, v: sx - p - 4); break;
231 default:
232 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
233 toString(file));
234 }
235}
236
237// Interpret the existing immediate value as a byte offset to the
238// target symbol, then update the instruction with the immediate as
239// the page offset from the current instruction to the target.
240void applyArm64Addr(uint8_t *off, uint64_t s, uint64_t p, int shift) {
241 uint32_t orig = read32le(P: off);
242 int64_t imm =
243 SignExtend64<21>(x: ((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC));
244 s += imm;
245 imm = (s >> shift) - (p >> shift);
246 uint32_t immLo = (imm & 0x3) << 29;
247 uint32_t immHi = (imm & 0x1FFFFC) << 3;
248 uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3);
249 write32le(P: off, V: (orig & ~mask) | immLo | immHi);
250}
251
252// Update the immediate field in a AARCH64 ldr, str, and add instruction.
253// Optionally limit the range of the written immediate by one or more bits
254// (rangeLimit).
255void applyArm64Imm(uint8_t *off, uint64_t imm, uint32_t rangeLimit) {
256 uint32_t orig = read32le(P: off);
257 imm += (orig >> 10) & 0xFFF;
258 orig &= ~(0xFFF << 10);
259 write32le(P: off, V: orig | ((imm & (0xFFF >> rangeLimit)) << 10));
260}
261
262// Add the 12 bit page offset to the existing immediate.
263// Ldr/str instructions store the opcode immediate scaled
264// by the load/store size (giving a larger range for larger
265// loads/stores). The immediate is always (both before and after
266// fixing up the relocation) stored scaled similarly.
267// Even if larger loads/stores have a larger range, limit the
268// effective offset to 12 bit, since it is intended to be a
269// page offset.
270static void applyArm64Ldr(uint8_t *off, uint64_t imm) {
271 uint32_t orig = read32le(P: off);
272 uint32_t size = orig >> 30;
273 // 0x04000000 indicates SIMD/FP registers
274 // 0x00800000 indicates 128 bit
275 if ((orig & 0x4800000) == 0x4800000)
276 size += 4;
277 if ((imm & ((1 << size) - 1)) != 0)
278 error(msg: "misaligned ldr/str offset");
279 applyArm64Imm(off, imm: imm >> size, rangeLimit: size);
280}
281
282static void applySecRelLow12A(const SectionChunk *sec, uint8_t *off,
283 OutputSection *os, uint64_t s) {
284 if (checkSecRel(sec, os))
285 applyArm64Imm(off, imm: (s - os->getRVA()) & 0xfff, rangeLimit: 0);
286}
287
288static void applySecRelHigh12A(const SectionChunk *sec, uint8_t *off,
289 OutputSection *os, uint64_t s) {
290 if (!checkSecRel(sec, os))
291 return;
292 uint64_t secRel = (s - os->getRVA()) >> 12;
293 if (0xfff < secRel) {
294 error(msg: "overflow in SECREL_HIGH12A relocation in section: " +
295 sec->getSectionName());
296 return;
297 }
298 applyArm64Imm(off, imm: secRel & 0xfff, rangeLimit: 0);
299}
300
301static void applySecRelLdr(const SectionChunk *sec, uint8_t *off,
302 OutputSection *os, uint64_t s) {
303 if (checkSecRel(sec, os))
304 applyArm64Ldr(off, imm: (s - os->getRVA()) & 0xfff);
305}
306
307void applyArm64Branch26(uint8_t *off, int64_t v) {
308 if (!isInt<28>(x: v))
309 error(msg: "relocation out of range");
310 or32(p: off, v: (v & 0x0FFFFFFC) >> 2);
311}
312
313static void applyArm64Branch19(uint8_t *off, int64_t v) {
314 if (!isInt<21>(x: v))
315 error(msg: "relocation out of range");
316 or32(p: off, v: (v & 0x001FFFFC) << 3);
317}
318
319static void applyArm64Branch14(uint8_t *off, int64_t v) {
320 if (!isInt<16>(x: v))
321 error(msg: "relocation out of range");
322 or32(p: off, v: (v & 0x0000FFFC) << 3);
323}
324
325void SectionChunk::applyRelARM64(uint8_t *off, uint16_t type, OutputSection *os,
326 uint64_t s, uint64_t p,
327 uint64_t imageBase) const {
328 switch (type) {
329 case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(off, s, p, shift: 12); break;
330 case IMAGE_REL_ARM64_REL21: applyArm64Addr(off, s, p, shift: 0); break;
331 case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(off, imm: s & 0xfff, rangeLimit: 0); break;
332 case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(off, imm: s & 0xfff); break;
333 case IMAGE_REL_ARM64_BRANCH26: applyArm64Branch26(off, v: s - p); break;
334 case IMAGE_REL_ARM64_BRANCH19: applyArm64Branch19(off, v: s - p); break;
335 case IMAGE_REL_ARM64_BRANCH14: applyArm64Branch14(off, v: s - p); break;
336 case IMAGE_REL_ARM64_ADDR32:
337 add32(p: off, v: s + imageBase);
338 break;
339 case IMAGE_REL_ARM64_ADDR32NB: add32(p: off, v: s); break;
340 case IMAGE_REL_ARM64_ADDR64:
341 add64(p: off, v: s + imageBase);
342 break;
343 case IMAGE_REL_ARM64_SECREL: applySecRel(sec: this, off, os, s); break;
344 case IMAGE_REL_ARM64_SECREL_LOW12A: applySecRelLow12A(sec: this, off, os, s); break;
345 case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(sec: this, off, os, s); break;
346 case IMAGE_REL_ARM64_SECREL_LOW12L: applySecRelLdr(sec: this, off, os, s); break;
347 case IMAGE_REL_ARM64_SECTION:
348 applySecIdx(off, os, numOutputSections: file->ctx.outputSections.size());
349 break;
350 case IMAGE_REL_ARM64_REL32: add32(p: off, v: s - p - 4); break;
351 default:
352 error(msg: "unsupported relocation type 0x" + Twine::utohexstr(Val: type) + " in " +
353 toString(file));
354 }
355}
356
357static void maybeReportRelocationToDiscarded(const SectionChunk *fromChunk,
358 Defined *sym,
359 const coff_relocation &rel,
360 bool isMinGW) {
361 // Don't report these errors when the relocation comes from a debug info
362 // section or in mingw mode. MinGW mode object files (built by GCC) can
363 // have leftover sections with relocations against discarded comdat
364 // sections. Such sections are left as is, with relocations untouched.
365 if (fromChunk->isCodeView() || fromChunk->isDWARF() || isMinGW)
366 return;
367
368 // Get the name of the symbol. If it's null, it was discarded early, so we
369 // have to go back to the object file.
370 ObjFile *file = fromChunk->file;
371 StringRef name;
372 if (sym) {
373 name = sym->getName();
374 } else {
375 COFFSymbolRef coffSym =
376 check(e: file->getCOFFObj()->getSymbol(index: rel.SymbolTableIndex));
377 name = check(e: file->getCOFFObj()->getSymbolName(Symbol: coffSym));
378 }
379
380 std::vector<std::string> symbolLocations =
381 getSymbolLocations(file, symIndex: rel.SymbolTableIndex);
382
383 std::string out;
384 llvm::raw_string_ostream os(out);
385 os << "relocation against symbol in discarded section: " + name;
386 for (const std::string &s : symbolLocations)
387 os << s;
388 error(msg: os.str());
389}
390
391void SectionChunk::writeTo(uint8_t *buf) const {
392 if (!hasData)
393 return;
394 // Copy section contents from source object file to output file.
395 ArrayRef<uint8_t> a = getContents();
396 if (!a.empty())
397 memcpy(dest: buf, src: a.data(), n: a.size());
398
399 // Apply relocations.
400 size_t inputSize = getSize();
401 for (const coff_relocation &rel : getRelocs()) {
402 // Check for an invalid relocation offset. This check isn't perfect, because
403 // we don't have the relocation size, which is only known after checking the
404 // machine and relocation type. As a result, a relocation may overwrite the
405 // beginning of the following input section.
406 if (rel.VirtualAddress >= inputSize) {
407 error(msg: "relocation points beyond the end of its parent section");
408 continue;
409 }
410
411 applyRelocation(off: buf + rel.VirtualAddress, rel);
412 }
413}
414
415void SectionChunk::applyRelocation(uint8_t *off,
416 const coff_relocation &rel) const {
417 auto *sym = dyn_cast_or_null<Defined>(Val: file->getSymbol(symbolIndex: rel.SymbolTableIndex));
418
419 // Get the output section of the symbol for this relocation. The output
420 // section is needed to compute SECREL and SECTION relocations used in debug
421 // info.
422 Chunk *c = sym ? sym->getChunk() : nullptr;
423 OutputSection *os = c ? file->ctx.getOutputSection(c) : nullptr;
424
425 // Skip the relocation if it refers to a discarded section, and diagnose it
426 // as an error if appropriate. If a symbol was discarded early, it may be
427 // null. If it was discarded late, the output section will be null, unless
428 // it was an absolute or synthetic symbol.
429 if (!sym ||
430 (!os && !isa<DefinedAbsolute>(Val: sym) && !isa<DefinedSynthetic>(Val: sym))) {
431 maybeReportRelocationToDiscarded(fromChunk: this, sym, rel, isMinGW: file->ctx.config.mingw);
432 return;
433 }
434
435 uint64_t s = sym->getRVA();
436
437 // Compute the RVA of the relocation for relative relocations.
438 uint64_t p = rva + rel.VirtualAddress;
439 uint64_t imageBase = file->ctx.config.imageBase;
440 switch (getArch()) {
441 case Triple::x86_64:
442 applyRelX64(off, type: rel.Type, os, s, p, imageBase);
443 break;
444 case Triple::x86:
445 applyRelX86(off, type: rel.Type, os, s, p, imageBase);
446 break;
447 case Triple::thumb:
448 applyRelARM(off, type: rel.Type, os, s, p, imageBase);
449 break;
450 case Triple::aarch64:
451 applyRelARM64(off, type: rel.Type, os, s, p, imageBase);
452 break;
453 default:
454 llvm_unreachable("unknown machine type");
455 }
456}
457
458// Defend against unsorted relocations. This may be overly conservative.
459void SectionChunk::sortRelocations() {
460 auto cmpByVa = [](const coff_relocation &l, const coff_relocation &r) {
461 return l.VirtualAddress < r.VirtualAddress;
462 };
463 if (llvm::is_sorted(Range: getRelocs(), C: cmpByVa))
464 return;
465 warn(msg: "some relocations in " + file->getName() + " are not sorted");
466 MutableArrayRef<coff_relocation> newRelocs(
467 bAlloc().Allocate<coff_relocation>(Num: relocsSize), relocsSize);
468 memcpy(dest: newRelocs.data(), src: relocsData, n: relocsSize * sizeof(coff_relocation));
469 llvm::sort(C&: newRelocs, Comp: cmpByVa);
470 setRelocs(newRelocs);
471}
472
473// Similar to writeTo, but suitable for relocating a subsection of the overall
474// section.
475void SectionChunk::writeAndRelocateSubsection(ArrayRef<uint8_t> sec,
476 ArrayRef<uint8_t> subsec,
477 uint32_t &nextRelocIndex,
478 uint8_t *buf) const {
479 assert(!subsec.empty() && !sec.empty());
480 assert(sec.begin() <= subsec.begin() && subsec.end() <= sec.end() &&
481 "subsection is not part of this section");
482 size_t vaBegin = std::distance(first: sec.begin(), last: subsec.begin());
483 size_t vaEnd = std::distance(first: sec.begin(), last: subsec.end());
484 memcpy(dest: buf, src: subsec.data(), n: subsec.size());
485 for (; nextRelocIndex < relocsSize; ++nextRelocIndex) {
486 const coff_relocation &rel = relocsData[nextRelocIndex];
487 // Only apply relocations that apply to this subsection. These checks
488 // assume that all subsections completely contain their relocations.
489 // Relocations must not straddle the beginning or end of a subsection.
490 if (rel.VirtualAddress < vaBegin)
491 continue;
492 if (rel.VirtualAddress + 1 >= vaEnd)
493 break;
494 applyRelocation(off: &buf[rel.VirtualAddress - vaBegin], rel);
495 }
496}
497
498void SectionChunk::addAssociative(SectionChunk *child) {
499 // Insert the child section into the list of associated children. Keep the
500 // list ordered by section name so that ICF does not depend on section order.
501 assert(child->assocChildren == nullptr &&
502 "associated sections cannot have their own associated children");
503 SectionChunk *prev = this;
504 SectionChunk *next = assocChildren;
505 for (; next != nullptr; prev = next, next = next->assocChildren) {
506 if (next->getSectionName() <= child->getSectionName())
507 break;
508 }
509
510 // Insert child between prev and next.
511 assert(prev->assocChildren == next);
512 prev->assocChildren = child;
513 child->assocChildren = next;
514}
515
516static uint8_t getBaserelType(const coff_relocation &rel,
517 Triple::ArchType arch) {
518 switch (arch) {
519 case Triple::x86_64:
520 if (rel.Type == IMAGE_REL_AMD64_ADDR64)
521 return IMAGE_REL_BASED_DIR64;
522 if (rel.Type == IMAGE_REL_AMD64_ADDR32)
523 return IMAGE_REL_BASED_HIGHLOW;
524 return IMAGE_REL_BASED_ABSOLUTE;
525 case Triple::x86:
526 if (rel.Type == IMAGE_REL_I386_DIR32)
527 return IMAGE_REL_BASED_HIGHLOW;
528 return IMAGE_REL_BASED_ABSOLUTE;
529 case Triple::thumb:
530 if (rel.Type == IMAGE_REL_ARM_ADDR32)
531 return IMAGE_REL_BASED_HIGHLOW;
532 if (rel.Type == IMAGE_REL_ARM_MOV32T)
533 return IMAGE_REL_BASED_ARM_MOV32T;
534 return IMAGE_REL_BASED_ABSOLUTE;
535 case Triple::aarch64:
536 if (rel.Type == IMAGE_REL_ARM64_ADDR64)
537 return IMAGE_REL_BASED_DIR64;
538 return IMAGE_REL_BASED_ABSOLUTE;
539 default:
540 llvm_unreachable("unknown machine type");
541 }
542}
543
544// Windows-specific.
545// Collect all locations that contain absolute addresses, which need to be
546// fixed by the loader if load-time relocation is needed.
547// Only called when base relocation is enabled.
548void SectionChunk::getBaserels(std::vector<Baserel> *res) {
549 for (const coff_relocation &rel : getRelocs()) {
550 uint8_t ty = getBaserelType(rel, arch: getArch());
551 if (ty == IMAGE_REL_BASED_ABSOLUTE)
552 continue;
553 Symbol *target = file->getSymbol(symbolIndex: rel.SymbolTableIndex);
554 if (!target || isa<DefinedAbsolute>(Val: target))
555 continue;
556 res->emplace_back(args: rva + rel.VirtualAddress, args&: ty);
557 }
558}
559
560// MinGW specific.
561// Check whether a static relocation of type Type can be deferred and
562// handled at runtime as a pseudo relocation (for references to a module
563// local variable, which turned out to actually need to be imported from
564// another DLL) This returns the size the relocation is supposed to update,
565// in bits, or 0 if the relocation cannot be handled as a runtime pseudo
566// relocation.
567static int getRuntimePseudoRelocSize(uint16_t type,
568 llvm::COFF::MachineTypes machine) {
569 // Relocations that either contain an absolute address, or a plain
570 // relative offset, since the runtime pseudo reloc implementation
571 // adds 8/16/32/64 bit values to a memory address.
572 //
573 // Given a pseudo relocation entry,
574 //
575 // typedef struct {
576 // DWORD sym;
577 // DWORD target;
578 // DWORD flags;
579 // } runtime_pseudo_reloc_item_v2;
580 //
581 // the runtime relocation performs this adjustment:
582 // *(base + .target) += *(base + .sym) - (base + .sym)
583 //
584 // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64,
585 // IMAGE_REL_I386_DIR32, where the memory location initially contains
586 // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32),
587 // where the memory location originally contains the relative offset to the
588 // IAT slot.
589 //
590 // This requires the target address to be writable, either directly out of
591 // the image, or temporarily changed at runtime with VirtualProtect.
592 // Since this only operates on direct address values, it doesn't work for
593 // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations.
594 switch (machine) {
595 case AMD64:
596 switch (type) {
597 case IMAGE_REL_AMD64_ADDR64:
598 return 64;
599 case IMAGE_REL_AMD64_ADDR32:
600 case IMAGE_REL_AMD64_REL32:
601 case IMAGE_REL_AMD64_REL32_1:
602 case IMAGE_REL_AMD64_REL32_2:
603 case IMAGE_REL_AMD64_REL32_3:
604 case IMAGE_REL_AMD64_REL32_4:
605 case IMAGE_REL_AMD64_REL32_5:
606 return 32;
607 default:
608 return 0;
609 }
610 case I386:
611 switch (type) {
612 case IMAGE_REL_I386_DIR32:
613 case IMAGE_REL_I386_REL32:
614 return 32;
615 default:
616 return 0;
617 }
618 case ARMNT:
619 switch (type) {
620 case IMAGE_REL_ARM_ADDR32:
621 return 32;
622 default:
623 return 0;
624 }
625 case ARM64:
626 switch (type) {
627 case IMAGE_REL_ARM64_ADDR64:
628 return 64;
629 case IMAGE_REL_ARM64_ADDR32:
630 return 32;
631 default:
632 return 0;
633 }
634 default:
635 llvm_unreachable("unknown machine type");
636 }
637}
638
639// MinGW specific.
640// Append information to the provided vector about all relocations that
641// need to be handled at runtime as runtime pseudo relocations (references
642// to a module local variable, which turned out to actually need to be
643// imported from another DLL).
644void SectionChunk::getRuntimePseudoRelocs(
645 std::vector<RuntimePseudoReloc> &res) {
646 for (const coff_relocation &rel : getRelocs()) {
647 auto *target =
648 dyn_cast_or_null<Defined>(Val: file->getSymbol(symbolIndex: rel.SymbolTableIndex));
649 if (!target || !target->isRuntimePseudoReloc)
650 continue;
651 // If the target doesn't have a chunk allocated, it may be a
652 // DefinedImportData symbol which ended up unnecessary after GC.
653 // Normally we wouldn't eliminate section chunks that are referenced, but
654 // references within DWARF sections don't count for keeping section chunks
655 // alive. Thus such dangling references in DWARF sections are expected.
656 if (!target->getChunk())
657 continue;
658 int sizeInBits =
659 getRuntimePseudoRelocSize(type: rel.Type, machine: file->ctx.config.machine);
660 if (sizeInBits == 0) {
661 error(msg: "unable to automatically import from " + target->getName() +
662 " with relocation type " +
663 file->getCOFFObj()->getRelocationTypeName(Type: rel.Type) + " in " +
664 toString(file));
665 continue;
666 }
667 int addressSizeInBits = file->ctx.config.is64() ? 64 : 32;
668 if (sizeInBits < addressSizeInBits) {
669 warn(msg: "runtime pseudo relocation in " + toString(file) + " against " +
670 "symbol " + target->getName() + " is too narrow (only " +
671 Twine(sizeInBits) + " bits wide); this can fail at runtime " +
672 "depending on memory layout");
673 }
674 // sizeInBits is used to initialize the Flags field; currently no
675 // other flags are defined.
676 res.emplace_back(args&: target, args: this, args: rel.VirtualAddress, args&: sizeInBits);
677 }
678}
679
680bool SectionChunk::isCOMDAT() const {
681 return header->Characteristics & IMAGE_SCN_LNK_COMDAT;
682}
683
684void SectionChunk::printDiscardedMessage() const {
685 // Removed by dead-stripping. If it's removed by ICF, ICF already
686 // printed out the name, so don't repeat that here.
687 if (sym && this == repl)
688 log(msg: "Discarded " + sym->getName());
689}
690
691StringRef SectionChunk::getDebugName() const {
692 if (sym)
693 return sym->getName();
694 return "";
695}
696
697ArrayRef<uint8_t> SectionChunk::getContents() const {
698 ArrayRef<uint8_t> a;
699 cantFail(Err: file->getCOFFObj()->getSectionContents(Sec: header, Res&: a));
700 return a;
701}
702
703ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() {
704 assert(isCodeView());
705 return consumeDebugMagic(data: getContents(), sectionName: getSectionName());
706}
707
708ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> data,
709 StringRef sectionName) {
710 if (data.empty())
711 return {};
712
713 // First 4 bytes are section magic.
714 if (data.size() < 4)
715 fatal(msg: "the section is too short: " + sectionName);
716
717 if (!sectionName.starts_with(Prefix: ".debug$"))
718 fatal(msg: "invalid section: " + sectionName);
719
720 uint32_t magic = support::endian::read32le(P: data.data());
721 uint32_t expectedMagic = sectionName == ".debug$H"
722 ? DEBUG_HASHES_SECTION_MAGIC
723 : DEBUG_SECTION_MAGIC;
724 if (magic != expectedMagic) {
725 warn(msg: "ignoring section " + sectionName + " with unrecognized magic 0x" +
726 utohexstr(X: magic));
727 return {};
728 }
729 return data.slice(N: 4);
730}
731
732SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> sections,
733 StringRef name) {
734 for (SectionChunk *c : sections)
735 if (c->getSectionName() == name)
736 return c;
737 return nullptr;
738}
739
740void SectionChunk::replace(SectionChunk *other) {
741 p2Align = std::max(a: p2Align, b: other->p2Align);
742 other->repl = repl;
743 other->live = false;
744}
745
746uint32_t SectionChunk::getSectionNumber() const {
747 DataRefImpl r;
748 r.p = reinterpret_cast<uintptr_t>(header);
749 SectionRef s(r, file->getCOFFObj());
750 return s.getIndex() + 1;
751}
752
753CommonChunk::CommonChunk(const COFFSymbolRef s) : sym(s) {
754 // The value of a common symbol is its size. Align all common symbols smaller
755 // than 32 bytes naturally, i.e. round the size up to the next power of two.
756 // This is what MSVC link.exe does.
757 setAlignment(std::min(a: 32U, b: uint32_t(PowerOf2Ceil(A: sym.getValue()))));
758 hasData = false;
759}
760
761uint32_t CommonChunk::getOutputCharacteristics() const {
762 return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
763 IMAGE_SCN_MEM_WRITE;
764}
765
766void StringChunk::writeTo(uint8_t *buf) const {
767 memcpy(dest: buf, src: str.data(), n: str.size());
768 buf[str.size()] = '\0';
769}
770
771ImportThunkChunkX64::ImportThunkChunkX64(COFFLinkerContext &ctx, Defined *s)
772 : ImportThunkChunk(ctx, s) {
773 // Intel Optimization Manual says that all branch targets
774 // should be 16-byte aligned. MSVC linker does this too.
775 setAlignment(16);
776}
777
778void ImportThunkChunkX64::writeTo(uint8_t *buf) const {
779 memcpy(dest: buf, src: importThunkX86, n: sizeof(importThunkX86));
780 // The first two bytes is a JMP instruction. Fill its operand.
781 write32le(P: buf + 2, V: impSymbol->getRVA() - rva - getSize());
782}
783
784void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *res) {
785 res->emplace_back(args: getRVA() + 2, args&: ctx.config.machine);
786}
787
788void ImportThunkChunkX86::writeTo(uint8_t *buf) const {
789 memcpy(dest: buf, src: importThunkX86, n: sizeof(importThunkX86));
790 // The first two bytes is a JMP instruction. Fill its operand.
791 write32le(P: buf + 2, V: impSymbol->getRVA() + ctx.config.imageBase);
792}
793
794void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *res) {
795 res->emplace_back(args: getRVA(), args: IMAGE_REL_BASED_ARM_MOV32T);
796}
797
798void ImportThunkChunkARM::writeTo(uint8_t *buf) const {
799 memcpy(dest: buf, src: importThunkARM, n: sizeof(importThunkARM));
800 // Fix mov.w and mov.t operands.
801 applyMOV32T(off: buf, v: impSymbol->getRVA() + ctx.config.imageBase);
802}
803
804void ImportThunkChunkARM64::writeTo(uint8_t *buf) const {
805 int64_t off = impSymbol->getRVA() & 0xfff;
806 memcpy(dest: buf, src: importThunkARM64, n: sizeof(importThunkARM64));
807 applyArm64Addr(off: buf, s: impSymbol->getRVA(), p: rva, shift: 12);
808 applyArm64Ldr(off: buf + 4, imm: off);
809}
810
811// A Thumb2, PIC, non-interworking range extension thunk.
812const uint8_t armThunk[] = {
813 0x40, 0xf2, 0x00, 0x0c, // P: movw ip,:lower16:S - (P + (L1-P) + 4)
814 0xc0, 0xf2, 0x00, 0x0c, // movt ip,:upper16:S - (P + (L1-P) + 4)
815 0xe7, 0x44, // L1: add pc, ip
816};
817
818size_t RangeExtensionThunkARM::getSize() const {
819 assert(ctx.config.machine == ARMNT);
820 (void)&ctx;
821 return sizeof(armThunk);
822}
823
824void RangeExtensionThunkARM::writeTo(uint8_t *buf) const {
825 assert(ctx.config.machine == ARMNT);
826 uint64_t offset = target->getRVA() - rva - 12;
827 memcpy(dest: buf, src: armThunk, n: sizeof(armThunk));
828 applyMOV32T(off: buf, v: uint32_t(offset));
829}
830
831// A position independent ARM64 adrp+add thunk, with a maximum range of
832// +/- 4 GB, which is enough for any PE-COFF.
833const uint8_t arm64Thunk[] = {
834 0x10, 0x00, 0x00, 0x90, // adrp x16, Dest
835 0x10, 0x02, 0x00, 0x91, // add x16, x16, :lo12:Dest
836 0x00, 0x02, 0x1f, 0xd6, // br x16
837};
838
839size_t RangeExtensionThunkARM64::getSize() const {
840 assert(ctx.config.machine == ARM64);
841 (void)&ctx;
842 return sizeof(arm64Thunk);
843}
844
845void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const {
846 assert(ctx.config.machine == ARM64);
847 memcpy(dest: buf, src: arm64Thunk, n: sizeof(arm64Thunk));
848 applyArm64Addr(off: buf + 0, s: target->getRVA(), p: rva, shift: 12);
849 applyArm64Imm(off: buf + 4, imm: target->getRVA() & 0xfff, rangeLimit: 0);
850}
851
852LocalImportChunk::LocalImportChunk(COFFLinkerContext &c, Defined *s)
853 : sym(s), ctx(c) {
854 setAlignment(ctx.config.wordsize);
855}
856
857void LocalImportChunk::getBaserels(std::vector<Baserel> *res) {
858 res->emplace_back(args: getRVA(), args&: ctx.config.machine);
859}
860
861size_t LocalImportChunk::getSize() const { return ctx.config.wordsize; }
862
863void LocalImportChunk::writeTo(uint8_t *buf) const {
864 if (ctx.config.is64()) {
865 write64le(P: buf, V: sym->getRVA() + ctx.config.imageBase);
866 } else {
867 write32le(P: buf, V: sym->getRVA() + ctx.config.imageBase);
868 }
869}
870
871void RVATableChunk::writeTo(uint8_t *buf) const {
872 ulittle32_t *begin = reinterpret_cast<ulittle32_t *>(buf);
873 size_t cnt = 0;
874 for (const ChunkAndOffset &co : syms)
875 begin[cnt++] = co.inputChunk->getRVA() + co.offset;
876 llvm::sort(Start: begin, End: begin + cnt);
877 assert(std::unique(begin, begin + cnt) == begin + cnt &&
878 "RVA tables should be de-duplicated");
879}
880
881void RVAFlagTableChunk::writeTo(uint8_t *buf) const {
882 struct RVAFlag {
883 ulittle32_t rva;
884 uint8_t flag;
885 };
886 auto flags =
887 MutableArrayRef(reinterpret_cast<RVAFlag *>(buf), syms.size());
888 for (auto t : zip(t: syms, u&: flags)) {
889 const auto &sym = std::get<0>(t&: t);
890 auto &flag = std::get<1>(t&: t);
891 flag.rva = sym.inputChunk->getRVA() + sym.offset;
892 flag.flag = 0;
893 }
894 llvm::sort(C&: flags,
895 Comp: [](const RVAFlag &a, const RVAFlag &b) { return a.rva < b.rva; });
896 assert(llvm::unique(flags, [](const RVAFlag &a,
897 const RVAFlag &b) { return a.rva == b.rva; }) ==
898 flags.end() &&
899 "RVA tables should be de-duplicated");
900}
901
902size_t ECCodeMapChunk::getSize() const {
903 return map.size() * sizeof(chpe_range_entry);
904}
905
906void ECCodeMapChunk::writeTo(uint8_t *buf) const {
907 auto table = reinterpret_cast<chpe_range_entry *>(buf);
908 for (uint32_t i = 0; i < map.size(); i++) {
909 const ECCodeMapEntry &entry = map[i];
910 uint32_t start = entry.first->getRVA();
911 table[i].StartOffset = start | entry.type;
912 table[i].Length = entry.last->getRVA() + entry.last->getSize() - start;
913 }
914}
915
916// MinGW specific, for the "automatic import of variables from DLLs" feature.
917size_t PseudoRelocTableChunk::getSize() const {
918 if (relocs.empty())
919 return 0;
920 return 12 + 12 * relocs.size();
921}
922
923// MinGW specific.
924void PseudoRelocTableChunk::writeTo(uint8_t *buf) const {
925 if (relocs.empty())
926 return;
927
928 ulittle32_t *table = reinterpret_cast<ulittle32_t *>(buf);
929 // This is the list header, to signal the runtime pseudo relocation v2
930 // format.
931 table[0] = 0;
932 table[1] = 0;
933 table[2] = 1;
934
935 size_t idx = 3;
936 for (const RuntimePseudoReloc &rpr : relocs) {
937 table[idx + 0] = rpr.sym->getRVA();
938 table[idx + 1] = rpr.target->getRVA() + rpr.targetOffset;
939 table[idx + 2] = rpr.flags;
940 idx += 3;
941 }
942}
943
944// Windows-specific. This class represents a block in .reloc section.
945// The format is described here.
946//
947// On Windows, each DLL is linked against a fixed base address and
948// usually loaded to that address. However, if there's already another
949// DLL that overlaps, the loader has to relocate it. To do that, DLLs
950// contain .reloc sections which contain offsets that need to be fixed
951// up at runtime. If the loader finds that a DLL cannot be loaded to its
952// desired base address, it loads it to somewhere else, and add <actual
953// base address> - <desired base address> to each offset that is
954// specified by the .reloc section. In ELF terms, .reloc sections
955// contain relative relocations in REL format (as opposed to RELA.)
956//
957// This already significantly reduces the size of relocations compared
958// to ELF .rel.dyn, but Windows does more to reduce it (probably because
959// it was invented for PCs in the late '80s or early '90s.) Offsets in
960// .reloc are grouped by page where the page size is 12 bits, and
961// offsets sharing the same page address are stored consecutively to
962// represent them with less space. This is very similar to the page
963// table which is grouped by (multiple stages of) pages.
964//
965// For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
966// 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
967// bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
968// are represented like this:
969//
970// 0x00000 -- page address (4 bytes)
971// 16 -- size of this block (4 bytes)
972// 0xA030 -- entries (2 bytes each)
973// 0xA500
974// 0xA700
975// 0xAA00
976// 0x20000 -- page address (4 bytes)
977// 12 -- size of this block (4 bytes)
978// 0xA004 -- entries (2 bytes each)
979// 0xA008
980//
981// Usually we have a lot of relocations for each page, so the number of
982// bytes for one .reloc entry is close to 2 bytes on average.
983BaserelChunk::BaserelChunk(uint32_t page, Baserel *begin, Baserel *end) {
984 // Block header consists of 4 byte page RVA and 4 byte block size.
985 // Each entry is 2 byte. Last entry may be padding.
986 data.resize(new_size: alignTo(Value: (end - begin) * 2 + 8, Align: 4));
987 uint8_t *p = data.data();
988 write32le(P: p, V: page);
989 write32le(P: p + 4, V: data.size());
990 p += 8;
991 for (Baserel *i = begin; i != end; ++i) {
992 write16le(P: p, V: (i->type << 12) | (i->rva - page));
993 p += 2;
994 }
995}
996
997void BaserelChunk::writeTo(uint8_t *buf) const {
998 memcpy(dest: buf, src: data.data(), n: data.size());
999}
1000
1001uint8_t Baserel::getDefaultType(llvm::COFF::MachineTypes machine) {
1002 switch (machine) {
1003 case AMD64:
1004 case ARM64:
1005 return IMAGE_REL_BASED_DIR64;
1006 case I386:
1007 case ARMNT:
1008 return IMAGE_REL_BASED_HIGHLOW;
1009 default:
1010 llvm_unreachable("unknown machine type");
1011 }
1012}
1013
1014MergeChunk::MergeChunk(uint32_t alignment)
1015 : builder(StringTableBuilder::RAW, llvm::Align(alignment)) {
1016 setAlignment(alignment);
1017}
1018
1019void MergeChunk::addSection(COFFLinkerContext &ctx, SectionChunk *c) {
1020 assert(isPowerOf2_32(c->getAlignment()));
1021 uint8_t p2Align = llvm::Log2_32(Value: c->getAlignment());
1022 assert(p2Align < std::size(ctx.mergeChunkInstances));
1023 auto *&mc = ctx.mergeChunkInstances[p2Align];
1024 if (!mc)
1025 mc = make<MergeChunk>(args: c->getAlignment());
1026 mc->sections.push_back(x: c);
1027}
1028
1029void MergeChunk::finalizeContents() {
1030 assert(!finalized && "should only finalize once");
1031 for (SectionChunk *c : sections)
1032 if (c->live)
1033 builder.add(S: toStringRef(Input: c->getContents()));
1034 builder.finalize();
1035 finalized = true;
1036}
1037
1038void MergeChunk::assignSubsectionRVAs() {
1039 for (SectionChunk *c : sections) {
1040 if (!c->live)
1041 continue;
1042 size_t off = builder.getOffset(S: toStringRef(Input: c->getContents()));
1043 c->setRVA(rva + off);
1044 }
1045}
1046
1047uint32_t MergeChunk::getOutputCharacteristics() const {
1048 return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
1049}
1050
1051size_t MergeChunk::getSize() const {
1052 return builder.getSize();
1053}
1054
1055void MergeChunk::writeTo(uint8_t *buf) const {
1056 builder.write(Buf: buf);
1057}
1058
1059// MinGW specific.
1060size_t AbsolutePointerChunk::getSize() const { return ctx.config.wordsize; }
1061
1062void AbsolutePointerChunk::writeTo(uint8_t *buf) const {
1063 if (ctx.config.is64()) {
1064 write64le(P: buf, V: value);
1065 } else {
1066 write32le(P: buf, V: value);
1067 }
1068}
1069
1070} // namespace lld::coff
1071

source code of lld/COFF/Chunks.cpp