1//===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_UTILITY_ARCHSPEC_H
10#define LLDB_UTILITY_ARCHSPEC_H
11
12#include "lldb/Utility/CompletionRequest.h"
13#include "lldb/lldb-enumerations.h"
14#include "lldb/lldb-forward.h"
15#include "lldb/lldb-private-enumerations.h"
16#include "llvm/ADT/StringRef.h"
17#include "llvm/TargetParser/Triple.h"
18#include <cstddef>
19#include <cstdint>
20#include <string>
21
22namespace lldb_private {
23
24/// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture
25/// specification class.
26///
27/// A class designed to be created from a cpu type and subtype, a
28/// string representation, or an llvm::Triple. Keeping all of the conversions
29/// of strings to architecture enumeration values confined to this class
30/// allows new architecture support to be added easily.
31class ArchSpec {
32public:
33 enum MIPSSubType {
34 eMIPSSubType_unknown,
35 eMIPSSubType_mips32,
36 eMIPSSubType_mips32r2,
37 eMIPSSubType_mips32r6,
38 eMIPSSubType_mips32el,
39 eMIPSSubType_mips32r2el,
40 eMIPSSubType_mips32r6el,
41 eMIPSSubType_mips64,
42 eMIPSSubType_mips64r2,
43 eMIPSSubType_mips64r6,
44 eMIPSSubType_mips64el,
45 eMIPSSubType_mips64r2el,
46 eMIPSSubType_mips64r6el,
47 };
48
49 // Masks for the ases word of an ABI flags structure.
50 enum MIPSASE {
51 eMIPSAse_dsp = 0x00000001, // DSP ASE
52 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE
53 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme
54 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE
55 eMIPSAse_mdmx = 0x00000010, // MDMX ASE
56 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE
57 eMIPSAse_mt = 0x00000040, // MT ASE
58 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
59 eMIPSAse_virt = 0x00000100, // VZ ASE
60 eMIPSAse_msa = 0x00000200, // MSA ASE
61 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE
62 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
63 eMIPSAse_xpa = 0x00001000, // XPA ASE
64 eMIPSAse_mask = 0x00001fff,
65 eMIPSABI_O32 = 0x00002000,
66 eMIPSABI_N32 = 0x00004000,
67 eMIPSABI_N64 = 0x00008000,
68 eMIPSABI_O64 = 0x00020000,
69 eMIPSABI_EABI32 = 0x00040000,
70 eMIPSABI_EABI64 = 0x00080000,
71 eMIPSABI_mask = 0x000ff000
72 };
73
74 // MIPS Floating point ABI Values
75 enum MIPS_ABI_FP {
76 eMIPS_ABI_FP_ANY = 0x00000000,
77 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
78 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
79 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float
80 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
81 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx
82 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64
83 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg
84 eMIPS_ABI_FP_mask = 0x00700000
85 };
86
87 // ARM specific e_flags
88 enum ARMeflags {
89 eARM_abi_soft_float = 0x00000200,
90 eARM_abi_hard_float = 0x00000400
91 };
92
93 enum RISCVeflags {
94 eRISCV_rvc = 0x00000001, /// RVC, +c
95 eRISCV_float_abi_soft = 0x00000000, /// soft float
96 eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f
97 eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d
98 eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q
99 eRISCV_float_abi_mask = 0x00000006,
100 eRISCV_rve = 0x00000008, /// RVE, +e
101 eRISCV_tso = 0x00000010, /// RVTSO (total store ordering)
102 };
103
104 enum RISCVSubType {
105 eRISCVSubType_unknown,
106 eRISCVSubType_riscv32,
107 eRISCVSubType_riscv64,
108 };
109
110 enum LoongArcheflags {
111 eLoongArch_abi_soft_float = 0x00000000, /// soft float
112 eLoongArch_abi_single_float =
113 0x00000001, /// single precision floating point, +f
114 eLoongArch_abi_double_float =
115 0x00000002, /// double precision floating point, +d
116 eLoongArch_abi_mask = 0x00000003,
117 };
118
119 enum LoongArchSubType {
120 eLoongArchSubType_unknown,
121 eLoongArchSubType_loongarch32,
122 eLoongArchSubType_loongarch64,
123 };
124
125 enum Core {
126 eCore_arm_generic,
127 eCore_arm_armv4,
128 eCore_arm_armv4t,
129 eCore_arm_armv5,
130 eCore_arm_armv5e,
131 eCore_arm_armv5t,
132 eCore_arm_armv6,
133 eCore_arm_armv6m,
134 eCore_arm_armv7,
135 eCore_arm_armv7a,
136 eCore_arm_armv7l,
137 eCore_arm_armv7f,
138 eCore_arm_armv7s,
139 eCore_arm_armv7k,
140 eCore_arm_armv7m,
141 eCore_arm_armv7em,
142 eCore_arm_xscale,
143
144 eCore_thumb,
145 eCore_thumbv4t,
146 eCore_thumbv5,
147 eCore_thumbv5e,
148 eCore_thumbv6,
149 eCore_thumbv6m,
150 eCore_thumbv7,
151 eCore_thumbv7s,
152 eCore_thumbv7k,
153 eCore_thumbv7f,
154 eCore_thumbv7m,
155 eCore_thumbv7em,
156 eCore_arm_arm64,
157 eCore_arm_armv8,
158 eCore_arm_armv8a,
159 eCore_arm_armv8l,
160 eCore_arm_arm64e,
161 eCore_arm_arm64_32,
162 eCore_arm_aarch64,
163
164 eCore_mips32,
165 eCore_mips32r2,
166 eCore_mips32r3,
167 eCore_mips32r5,
168 eCore_mips32r6,
169 eCore_mips32el,
170 eCore_mips32r2el,
171 eCore_mips32r3el,
172 eCore_mips32r5el,
173 eCore_mips32r6el,
174 eCore_mips64,
175 eCore_mips64r2,
176 eCore_mips64r3,
177 eCore_mips64r5,
178 eCore_mips64r6,
179 eCore_mips64el,
180 eCore_mips64r2el,
181 eCore_mips64r3el,
182 eCore_mips64r5el,
183 eCore_mips64r6el,
184
185 eCore_msp430,
186
187 eCore_ppc_generic,
188 eCore_ppc_ppc601,
189 eCore_ppc_ppc602,
190 eCore_ppc_ppc603,
191 eCore_ppc_ppc603e,
192 eCore_ppc_ppc603ev,
193 eCore_ppc_ppc604,
194 eCore_ppc_ppc604e,
195 eCore_ppc_ppc620,
196 eCore_ppc_ppc750,
197 eCore_ppc_ppc7400,
198 eCore_ppc_ppc7450,
199 eCore_ppc_ppc970,
200
201 eCore_ppc64le_generic,
202 eCore_ppc64_generic,
203 eCore_ppc64_ppc970_64,
204
205 eCore_s390x_generic,
206
207 eCore_sparc_generic,
208
209 eCore_sparc9_generic,
210
211 eCore_x86_32_i386,
212 eCore_x86_32_i486,
213 eCore_x86_32_i486sx,
214 eCore_x86_32_i686,
215
216 eCore_x86_64_x86_64,
217 eCore_x86_64_x86_64h, // Haswell enabled x86_64
218 eCore_x86_64_amd64,
219
220 eCore_hexagon_generic,
221 eCore_hexagon_hexagonv4,
222 eCore_hexagon_hexagonv5,
223
224 eCore_riscv32,
225 eCore_riscv64,
226
227 eCore_loongarch32,
228 eCore_loongarch64,
229
230 eCore_uknownMach32,
231 eCore_uknownMach64,
232
233 eCore_arc, // little endian ARC
234
235 eCore_avr,
236
237 eCore_wasm32,
238
239 kNumCores,
240
241 kCore_invalid,
242 // The following constants are used for wildcard matching only
243 kCore_any,
244 kCore_arm_any,
245 kCore_ppc_any,
246 kCore_ppc64_any,
247 kCore_x86_32_any,
248 kCore_x86_64_any,
249 kCore_hexagon_any,
250
251 kCore_arm_first = eCore_arm_generic,
252 kCore_arm_last = eCore_arm_xscale,
253
254 kCore_thumb_first = eCore_thumb,
255 kCore_thumb_last = eCore_thumbv7em,
256
257 kCore_ppc_first = eCore_ppc_generic,
258 kCore_ppc_last = eCore_ppc_ppc970,
259
260 kCore_ppc64_first = eCore_ppc64_generic,
261 kCore_ppc64_last = eCore_ppc64_ppc970_64,
262
263 kCore_x86_32_first = eCore_x86_32_i386,
264 kCore_x86_32_last = eCore_x86_32_i686,
265
266 kCore_x86_64_first = eCore_x86_64_x86_64,
267 kCore_x86_64_last = eCore_x86_64_x86_64h,
268
269 kCore_hexagon_first = eCore_hexagon_generic,
270 kCore_hexagon_last = eCore_hexagon_hexagonv5,
271
272 kCore_mips32_first = eCore_mips32,
273 kCore_mips32_last = eCore_mips32r6,
274
275 kCore_mips32el_first = eCore_mips32el,
276 kCore_mips32el_last = eCore_mips32r6el,
277
278 kCore_mips64_first = eCore_mips64,
279 kCore_mips64_last = eCore_mips64r6,
280
281 kCore_mips64el_first = eCore_mips64el,
282 kCore_mips64el_last = eCore_mips64r6el,
283
284 kCore_mips_first = eCore_mips32,
285 kCore_mips_last = eCore_mips64r6el
286
287 };
288
289 /// Default constructor.
290 ///
291 /// Default constructor that initializes the object with invalid cpu type
292 /// and subtype values.
293 ArchSpec();
294
295 /// Constructor over triple.
296 ///
297 /// Constructs an ArchSpec with properties consistent with the given Triple.
298 explicit ArchSpec(const llvm::Triple &triple);
299 explicit ArchSpec(const char *triple_cstr);
300 explicit ArchSpec(llvm::StringRef triple_str);
301 /// Constructor over architecture name.
302 ///
303 /// Constructs an ArchSpec with properties consistent with the given object
304 /// type and architecture name.
305 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type,
306 uint32_t cpu_subtype);
307
308 /// Destructor.
309 ~ArchSpec();
310
311 /// Returns true if the OS, vendor and environment fields of the triple are
312 /// unset. The triple is expected to be normalized
313 /// (llvm::Triple::normalize).
314 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple);
315
316 static void ListSupportedArchNames(StringList &list);
317 static void AutoComplete(CompletionRequest &request);
318
319 /// Returns a static string representing the current architecture.
320 ///
321 /// \return A static string corresponding to the current
322 /// architecture.
323 const char *GetArchitectureName() const;
324
325 /// if MIPS architecture return true.
326 ///
327 /// \return a boolean value.
328 bool IsMIPS() const;
329
330 /// Returns a string representing current architecture as a target CPU for
331 /// tools like compiler, disassembler etc.
332 ///
333 /// \return A string representing target CPU for the current
334 /// architecture.
335 std::string GetClangTargetCPU() const;
336
337 /// Return a string representing target application ABI.
338 ///
339 /// \return A string representing target application ABI.
340 std::string GetTargetABI() const;
341
342 /// Clears the object state.
343 ///
344 /// Clears the object state back to a default invalid state.
345 void Clear();
346
347 /// Returns the size in bytes of an address of the current architecture.
348 ///
349 /// \return The byte size of an address of the current architecture.
350 uint32_t GetAddressByteSize() const;
351
352 /// Returns a machine family for the current architecture.
353 ///
354 /// \return An LLVM arch type.
355 llvm::Triple::ArchType GetMachine() const;
356
357 /// Tests if this ArchSpec is valid.
358 ///
359 /// \return True if the current architecture is valid, false
360 /// otherwise.
361 bool IsValid() const {
362 return m_core >= eCore_arm_generic && m_core < kNumCores;
363 }
364 explicit operator bool() const { return IsValid(); }
365
366 bool TripleVendorWasSpecified() const {
367 return !m_triple.getVendorName().empty();
368 }
369
370 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); }
371
372 bool TripleEnvironmentWasSpecified() const {
373 return m_triple.hasEnvironment();
374 }
375
376 /// Merges fields from another ArchSpec into this ArchSpec.
377 ///
378 /// This will use the supplied ArchSpec to fill in any fields of the triple
379 /// in this ArchSpec which were unspecified. This can be used to refine a
380 /// generic ArchSpec with a more specific one. For example, if this
381 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we
382 /// have a triple which is x64-pc-windows-msvc, then merging that triple
383 /// into this one will result in the triple i386-pc-windows-msvc.
384 ///
385 void MergeFrom(const ArchSpec &other);
386
387 /// Change the architecture object type, CPU type and OS type.
388 ///
389 /// \param[in] arch_type The object type of this ArchSpec.
390 ///
391 /// \param[in] cpu The required CPU type.
392 ///
393 /// \param[in] os The optional OS type
394 /// The default value of 0 was chosen to from the ELF spec value
395 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another
396 /// format uses this parameter and 0 does not work, use a value over
397 /// 255 because in the ELF header this is value is only a byte.
398 ///
399 /// \return True if the object, and CPU were successfully set.
400 ///
401 /// As a side effect, the vendor value is usually set to unknown. The
402 /// exceptions are
403 /// aarch64-apple-ios
404 /// arm-apple-ios
405 /// thumb-apple-ios
406 /// x86-apple-
407 /// x86_64-apple-
408 ///
409 /// As a side effect, the os value is usually set to unknown The exceptions
410 /// are
411 /// *-*-aix
412 /// aarch64-apple-ios
413 /// arm-apple-ios
414 /// thumb-apple-ios
415 /// powerpc-apple-darwin
416 /// *-*-freebsd
417 /// *-*-linux
418 /// *-*-netbsd
419 /// *-*-openbsd
420 /// *-*-solaris
421 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub,
422 uint32_t os = 0);
423
424 /// Returns the byte order for the architecture specification.
425 ///
426 /// \return The endian enumeration for the current endianness of
427 /// the architecture specification
428 lldb::ByteOrder GetByteOrder() const;
429
430 /// Sets this ArchSpec's byte order.
431 ///
432 /// In the common case there is no need to call this method as the byte
433 /// order can almost always be determined by the architecture. However, many
434 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed
435 /// byte order may be incorrect.
436 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; }
437
438 uint32_t GetMinimumOpcodeByteSize() const;
439
440 uint32_t GetMaximumOpcodeByteSize() const;
441
442 Core GetCore() const { return m_core; }
443
444 uint32_t GetMachOCPUType() const;
445
446 uint32_t GetMachOCPUSubType() const;
447
448 /// Architecture data byte width accessor
449 ///
450 /// \return the size in 8-bit (host) bytes of a minimum addressable unit
451 /// from the Architecture's data bus
452 uint32_t GetDataByteSize() const;
453
454 /// Architecture code byte width accessor
455 ///
456 /// \return the size in 8-bit (host) bytes of a minimum addressable unit
457 /// from the Architecture's code bus
458 uint32_t GetCodeByteSize() const;
459
460 /// Architecture triple accessor.
461 ///
462 /// \return A triple describing this ArchSpec.
463 llvm::Triple &GetTriple() { return m_triple; }
464
465 /// Architecture triple accessor.
466 ///
467 /// \return A triple describing this ArchSpec.
468 const llvm::Triple &GetTriple() const { return m_triple; }
469
470 void DumpTriple(llvm::raw_ostream &s) const;
471
472 /// Architecture triple setter.
473 ///
474 /// Configures this ArchSpec according to the given triple. If the triple
475 /// has unknown components in all of the vendor, OS, and the optional
476 /// environment field (i.e. "i386-unknown-unknown") then default values are
477 /// taken from the host. Architecture and environment components are used
478 /// to further resolve the CPU type and subtype, endian characteristics,
479 /// etc.
480 ///
481 /// \return A triple describing this ArchSpec.
482 bool SetTriple(const llvm::Triple &triple);
483
484 bool SetTriple(llvm::StringRef triple_str);
485
486 /// Returns the default endianness of the architecture.
487 ///
488 /// \return The endian enumeration for the default endianness of
489 /// the architecture.
490 lldb::ByteOrder GetDefaultEndian() const;
491
492 /// Returns true if 'char' is a signed type by default in the architecture
493 /// false otherwise
494 ///
495 /// \return True if 'char' is a signed type by default on the
496 /// architecture and false otherwise.
497 bool CharIsSignedByDefault() const;
498
499 enum MatchType : bool { CompatibleMatch, ExactMatch };
500
501 /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of
502 /// matching that is to be done. CompatibleMatch requires only a compatible
503 /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an
504 /// exact match (armv7s is not an exact match with armv7).
505 ///
506 /// \return true if the two ArchSpecs match.
507 bool IsMatch(const ArchSpec &rhs, MatchType match) const;
508
509 /// Shorthand for IsMatch(rhs, ExactMatch).
510 bool IsExactMatch(const ArchSpec &rhs) const {
511 return IsMatch(rhs, match: ExactMatch);
512 }
513
514 /// Shorthand for IsMatch(rhs, CompatibleMatch).
515 bool IsCompatibleMatch(const ArchSpec &rhs) const {
516 return IsMatch(rhs, match: CompatibleMatch);
517 }
518
519 bool IsFullySpecifiedTriple() const;
520
521 /// Detect whether this architecture uses thumb code exclusively
522 ///
523 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute
524 /// the Thumb instructions, never Arm. We should normally pick up
525 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints
526 /// on each function - but when doing bare-boards low level debugging
527 /// (especially common with these embedded processors), we may not have
528 /// those things easily accessible.
529 ///
530 /// \return true if this is an arm ArchSpec which can only execute Thumb
531 /// instructions
532 bool IsAlwaysThumbInstructions() const;
533
534 uint32_t GetFlags() const { return m_flags; }
535
536 void SetFlags(uint32_t flags) { m_flags = flags; }
537
538 void SetFlags(const std::string &elf_abi);
539
540protected:
541 void UpdateCore();
542
543 llvm::Triple m_triple;
544 Core m_core = kCore_invalid;
545 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid;
546
547 // Additional arch flags which we cannot get from triple and core For MIPS
548 // these are application specific extensions like micromips, mips16 etc.
549 uint32_t m_flags = 0;
550
551 // Called when m_def or m_entry are changed. Fills in all remaining members
552 // with default values.
553 void CoreUpdated(bool update_triple);
554};
555
556/// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than
557/// operator.
558///
559/// Tests two ArchSpec objects to see if \a lhs is less than \a rhs.
560///
561/// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in]
562/// rhs The Left Hand Side ArchSpec object to compare.
563///
564/// \return true if \a lhs is less than \a rhs
565bool operator<(const ArchSpec &lhs, const ArchSpec &rhs);
566bool operator==(const ArchSpec &lhs, const ArchSpec &rhs);
567
568bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch);
569
570} // namespace lldb_private
571
572#endif // LLDB_UTILITY_ARCHSPEC_H
573

source code of lldb/include/lldb/Utility/ArchSpec.h