1//===-- RegisterContext_mips.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H
10#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H
11
12#include <cstddef>
13#include <cstdint>
14
15// eh_frame and DWARF Register numbers (eRegisterKindEHFrame &
16// eRegisterKindDWARF)
17
18enum {
19 // GP Registers
20 dwarf_zero_mips = 0,
21 dwarf_r1_mips,
22 dwarf_r2_mips,
23 dwarf_r3_mips,
24 dwarf_r4_mips,
25 dwarf_r5_mips,
26 dwarf_r6_mips,
27 dwarf_r7_mips,
28 dwarf_r8_mips,
29 dwarf_r9_mips,
30 dwarf_r10_mips,
31 dwarf_r11_mips,
32 dwarf_r12_mips,
33 dwarf_r13_mips,
34 dwarf_r14_mips,
35 dwarf_r15_mips,
36 dwarf_r16_mips,
37 dwarf_r17_mips,
38 dwarf_r18_mips,
39 dwarf_r19_mips,
40 dwarf_r20_mips,
41 dwarf_r21_mips,
42 dwarf_r22_mips,
43 dwarf_r23_mips,
44 dwarf_r24_mips,
45 dwarf_r25_mips,
46 dwarf_r26_mips,
47 dwarf_r27_mips,
48 dwarf_gp_mips,
49 dwarf_sp_mips,
50 dwarf_r30_mips,
51 dwarf_ra_mips,
52 dwarf_sr_mips,
53 dwarf_lo_mips,
54 dwarf_hi_mips,
55 dwarf_bad_mips,
56 dwarf_cause_mips,
57 dwarf_pc_mips,
58 dwarf_f0_mips,
59 dwarf_f1_mips,
60 dwarf_f2_mips,
61 dwarf_f3_mips,
62 dwarf_f4_mips,
63 dwarf_f5_mips,
64 dwarf_f6_mips,
65 dwarf_f7_mips,
66 dwarf_f8_mips,
67 dwarf_f9_mips,
68 dwarf_f10_mips,
69 dwarf_f11_mips,
70 dwarf_f12_mips,
71 dwarf_f13_mips,
72 dwarf_f14_mips,
73 dwarf_f15_mips,
74 dwarf_f16_mips,
75 dwarf_f17_mips,
76 dwarf_f18_mips,
77 dwarf_f19_mips,
78 dwarf_f20_mips,
79 dwarf_f21_mips,
80 dwarf_f22_mips,
81 dwarf_f23_mips,
82 dwarf_f24_mips,
83 dwarf_f25_mips,
84 dwarf_f26_mips,
85 dwarf_f27_mips,
86 dwarf_f28_mips,
87 dwarf_f29_mips,
88 dwarf_f30_mips,
89 dwarf_f31_mips,
90 dwarf_fcsr_mips,
91 dwarf_fir_mips,
92 dwarf_w0_mips,
93 dwarf_w1_mips,
94 dwarf_w2_mips,
95 dwarf_w3_mips,
96 dwarf_w4_mips,
97 dwarf_w5_mips,
98 dwarf_w6_mips,
99 dwarf_w7_mips,
100 dwarf_w8_mips,
101 dwarf_w9_mips,
102 dwarf_w10_mips,
103 dwarf_w11_mips,
104 dwarf_w12_mips,
105 dwarf_w13_mips,
106 dwarf_w14_mips,
107 dwarf_w15_mips,
108 dwarf_w16_mips,
109 dwarf_w17_mips,
110 dwarf_w18_mips,
111 dwarf_w19_mips,
112 dwarf_w20_mips,
113 dwarf_w21_mips,
114 dwarf_w22_mips,
115 dwarf_w23_mips,
116 dwarf_w24_mips,
117 dwarf_w25_mips,
118 dwarf_w26_mips,
119 dwarf_w27_mips,
120 dwarf_w28_mips,
121 dwarf_w29_mips,
122 dwarf_w30_mips,
123 dwarf_w31_mips,
124 dwarf_mcsr_mips,
125 dwarf_mir_mips,
126 dwarf_config5_mips,
127 dwarf_ic_mips,
128 dwarf_dummy_mips
129};
130
131enum {
132 dwarf_zero_mips64 = 0,
133 dwarf_r1_mips64,
134 dwarf_r2_mips64,
135 dwarf_r3_mips64,
136 dwarf_r4_mips64,
137 dwarf_r5_mips64,
138 dwarf_r6_mips64,
139 dwarf_r7_mips64,
140 dwarf_r8_mips64,
141 dwarf_r9_mips64,
142 dwarf_r10_mips64,
143 dwarf_r11_mips64,
144 dwarf_r12_mips64,
145 dwarf_r13_mips64,
146 dwarf_r14_mips64,
147 dwarf_r15_mips64,
148 dwarf_r16_mips64,
149 dwarf_r17_mips64,
150 dwarf_r18_mips64,
151 dwarf_r19_mips64,
152 dwarf_r20_mips64,
153 dwarf_r21_mips64,
154 dwarf_r22_mips64,
155 dwarf_r23_mips64,
156 dwarf_r24_mips64,
157 dwarf_r25_mips64,
158 dwarf_r26_mips64,
159 dwarf_r27_mips64,
160 dwarf_gp_mips64,
161 dwarf_sp_mips64,
162 dwarf_r30_mips64,
163 dwarf_ra_mips64,
164 dwarf_sr_mips64,
165 dwarf_lo_mips64,
166 dwarf_hi_mips64,
167 dwarf_bad_mips64,
168 dwarf_cause_mips64,
169 dwarf_pc_mips64,
170 dwarf_f0_mips64,
171 dwarf_f1_mips64,
172 dwarf_f2_mips64,
173 dwarf_f3_mips64,
174 dwarf_f4_mips64,
175 dwarf_f5_mips64,
176 dwarf_f6_mips64,
177 dwarf_f7_mips64,
178 dwarf_f8_mips64,
179 dwarf_f9_mips64,
180 dwarf_f10_mips64,
181 dwarf_f11_mips64,
182 dwarf_f12_mips64,
183 dwarf_f13_mips64,
184 dwarf_f14_mips64,
185 dwarf_f15_mips64,
186 dwarf_f16_mips64,
187 dwarf_f17_mips64,
188 dwarf_f18_mips64,
189 dwarf_f19_mips64,
190 dwarf_f20_mips64,
191 dwarf_f21_mips64,
192 dwarf_f22_mips64,
193 dwarf_f23_mips64,
194 dwarf_f24_mips64,
195 dwarf_f25_mips64,
196 dwarf_f26_mips64,
197 dwarf_f27_mips64,
198 dwarf_f28_mips64,
199 dwarf_f29_mips64,
200 dwarf_f30_mips64,
201 dwarf_f31_mips64,
202 dwarf_fcsr_mips64,
203 dwarf_fir_mips64,
204 dwarf_ic_mips64,
205 dwarf_dummy_mips64,
206 dwarf_w0_mips64,
207 dwarf_w1_mips64,
208 dwarf_w2_mips64,
209 dwarf_w3_mips64,
210 dwarf_w4_mips64,
211 dwarf_w5_mips64,
212 dwarf_w6_mips64,
213 dwarf_w7_mips64,
214 dwarf_w8_mips64,
215 dwarf_w9_mips64,
216 dwarf_w10_mips64,
217 dwarf_w11_mips64,
218 dwarf_w12_mips64,
219 dwarf_w13_mips64,
220 dwarf_w14_mips64,
221 dwarf_w15_mips64,
222 dwarf_w16_mips64,
223 dwarf_w17_mips64,
224 dwarf_w18_mips64,
225 dwarf_w19_mips64,
226 dwarf_w20_mips64,
227 dwarf_w21_mips64,
228 dwarf_w22_mips64,
229 dwarf_w23_mips64,
230 dwarf_w24_mips64,
231 dwarf_w25_mips64,
232 dwarf_w26_mips64,
233 dwarf_w27_mips64,
234 dwarf_w28_mips64,
235 dwarf_w29_mips64,
236 dwarf_w30_mips64,
237 dwarf_w31_mips64,
238 dwarf_mcsr_mips64,
239 dwarf_mir_mips64,
240 dwarf_config5_mips64,
241};
242
243// GP registers
244struct GPR_linux_mips {
245 uint64_t zero;
246 uint64_t r1;
247 uint64_t r2;
248 uint64_t r3;
249 uint64_t r4;
250 uint64_t r5;
251 uint64_t r6;
252 uint64_t r7;
253 uint64_t r8;
254 uint64_t r9;
255 uint64_t r10;
256 uint64_t r11;
257 uint64_t r12;
258 uint64_t r13;
259 uint64_t r14;
260 uint64_t r15;
261 uint64_t r16;
262 uint64_t r17;
263 uint64_t r18;
264 uint64_t r19;
265 uint64_t r20;
266 uint64_t r21;
267 uint64_t r22;
268 uint64_t r23;
269 uint64_t r24;
270 uint64_t r25;
271 uint64_t r26;
272 uint64_t r27;
273 uint64_t gp;
274 uint64_t sp;
275 uint64_t r30;
276 uint64_t ra;
277 uint64_t mullo;
278 uint64_t mulhi;
279 uint64_t pc;
280 uint64_t badvaddr;
281 uint64_t sr;
282 uint64_t cause;
283 uint64_t config5;
284};
285
286struct FPR_linux_mips {
287 uint64_t f0;
288 uint64_t f1;
289 uint64_t f2;
290 uint64_t f3;
291 uint64_t f4;
292 uint64_t f5;
293 uint64_t f6;
294 uint64_t f7;
295 uint64_t f8;
296 uint64_t f9;
297 uint64_t f10;
298 uint64_t f11;
299 uint64_t f12;
300 uint64_t f13;
301 uint64_t f14;
302 uint64_t f15;
303 uint64_t f16;
304 uint64_t f17;
305 uint64_t f18;
306 uint64_t f19;
307 uint64_t f20;
308 uint64_t f21;
309 uint64_t f22;
310 uint64_t f23;
311 uint64_t f24;
312 uint64_t f25;
313 uint64_t f26;
314 uint64_t f27;
315 uint64_t f28;
316 uint64_t f29;
317 uint64_t f30;
318 uint64_t f31;
319 uint32_t fcsr;
320 uint32_t fir;
321 uint32_t config5;
322};
323
324struct MSAReg {
325 uint8_t byte[16];
326};
327
328struct MSA_linux_mips {
329 MSAReg w0;
330 MSAReg w1;
331 MSAReg w2;
332 MSAReg w3;
333 MSAReg w4;
334 MSAReg w5;
335 MSAReg w6;
336 MSAReg w7;
337 MSAReg w8;
338 MSAReg w9;
339 MSAReg w10;
340 MSAReg w11;
341 MSAReg w12;
342 MSAReg w13;
343 MSAReg w14;
344 MSAReg w15;
345 MSAReg w16;
346 MSAReg w17;
347 MSAReg w18;
348 MSAReg w19;
349 MSAReg w20;
350 MSAReg w21;
351 MSAReg w22;
352 MSAReg w23;
353 MSAReg w24;
354 MSAReg w25;
355 MSAReg w26;
356 MSAReg w27;
357 MSAReg w28;
358 MSAReg w29;
359 MSAReg w30;
360 MSAReg w31;
361 uint32_t fcsr; /* FPU control status register */
362 uint32_t fir; /* FPU implementaion revision */
363 uint32_t mcsr; /* MSA control status register */
364 uint32_t mir; /* MSA implementation revision */
365 uint32_t config5; /* Config5 register */
366};
367
368struct UserArea {
369 GPR_linux_mips gpr; // General purpose registers.
370 FPR_linux_mips fpr; // Floating point registers.
371 MSA_linux_mips msa; // MSA registers.
372};
373
374#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H
375

source code of lldb/source/Plugins/Process/Utility/RegisterContext_mips.h