1 | //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | |
9 | #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT |
10 | |
11 | #include <cstddef> |
12 | |
13 | #include "lldb/lldb-defines.h" |
14 | #include "lldb/lldb-enumerations.h" |
15 | #include "lldb/lldb-private.h" |
16 | |
17 | #include "Utility/ARM_DWARF_Registers.h" |
18 | #include "Utility/ARM_ehframe_Registers.h" |
19 | |
20 | using namespace lldb; |
21 | using namespace lldb_private; |
22 | |
23 | #ifndef GPR_OFFSET |
24 | #error GPR_OFFSET must be defined before including this header file |
25 | #endif |
26 | |
27 | #ifndef FPU_OFFSET |
28 | #error FPU_OFFSET must be defined before including this header file |
29 | #endif |
30 | |
31 | #ifndef FPSCR_OFFSET |
32 | #error FPSCR_OFFSET must be defined before including this header file |
33 | #endif |
34 | |
35 | #ifndef EXC_OFFSET |
36 | #error EXC_OFFSET_NAME must be defined before including this header file |
37 | #endif |
38 | |
39 | #ifndef DEFINE_DBG |
40 | #error DEFINE_DBG must be defined before including this header file |
41 | #endif |
42 | |
43 | enum { |
44 | gpr_r0 = 0, |
45 | gpr_r1, |
46 | gpr_r2, |
47 | gpr_r3, |
48 | gpr_r4, |
49 | gpr_r5, |
50 | gpr_r6, |
51 | gpr_r7, |
52 | gpr_r8, |
53 | gpr_r9, |
54 | gpr_r10, |
55 | gpr_r11, |
56 | gpr_r12, |
57 | gpr_r13, |
58 | gpr_sp = gpr_r13, |
59 | gpr_r14, |
60 | gpr_lr = gpr_r14, |
61 | gpr_r15, |
62 | gpr_pc = gpr_r15, |
63 | gpr_cpsr, |
64 | |
65 | fpu_s0, |
66 | fpu_s1, |
67 | fpu_s2, |
68 | fpu_s3, |
69 | fpu_s4, |
70 | fpu_s5, |
71 | fpu_s6, |
72 | fpu_s7, |
73 | fpu_s8, |
74 | fpu_s9, |
75 | fpu_s10, |
76 | fpu_s11, |
77 | fpu_s12, |
78 | fpu_s13, |
79 | fpu_s14, |
80 | fpu_s15, |
81 | fpu_s16, |
82 | fpu_s17, |
83 | fpu_s18, |
84 | fpu_s19, |
85 | fpu_s20, |
86 | fpu_s21, |
87 | fpu_s22, |
88 | fpu_s23, |
89 | fpu_s24, |
90 | fpu_s25, |
91 | fpu_s26, |
92 | fpu_s27, |
93 | fpu_s28, |
94 | fpu_s29, |
95 | fpu_s30, |
96 | fpu_s31, |
97 | fpu_fpscr, |
98 | |
99 | fpu_d0, |
100 | fpu_d1, |
101 | fpu_d2, |
102 | fpu_d3, |
103 | fpu_d4, |
104 | fpu_d5, |
105 | fpu_d6, |
106 | fpu_d7, |
107 | fpu_d8, |
108 | fpu_d9, |
109 | fpu_d10, |
110 | fpu_d11, |
111 | fpu_d12, |
112 | fpu_d13, |
113 | fpu_d14, |
114 | fpu_d15, |
115 | fpu_d16, |
116 | fpu_d17, |
117 | fpu_d18, |
118 | fpu_d19, |
119 | fpu_d20, |
120 | fpu_d21, |
121 | fpu_d22, |
122 | fpu_d23, |
123 | fpu_d24, |
124 | fpu_d25, |
125 | fpu_d26, |
126 | fpu_d27, |
127 | fpu_d28, |
128 | fpu_d29, |
129 | fpu_d30, |
130 | fpu_d31, |
131 | |
132 | fpu_q0, |
133 | fpu_q1, |
134 | fpu_q2, |
135 | fpu_q3, |
136 | fpu_q4, |
137 | fpu_q5, |
138 | fpu_q6, |
139 | fpu_q7, |
140 | fpu_q8, |
141 | fpu_q9, |
142 | fpu_q10, |
143 | fpu_q11, |
144 | fpu_q12, |
145 | fpu_q13, |
146 | fpu_q14, |
147 | fpu_q15, |
148 | |
149 | exc_exception, |
150 | exc_fsr, |
151 | exc_far, |
152 | |
153 | dbg_bvr0, |
154 | dbg_bvr1, |
155 | dbg_bvr2, |
156 | dbg_bvr3, |
157 | dbg_bvr4, |
158 | dbg_bvr5, |
159 | dbg_bvr6, |
160 | dbg_bvr7, |
161 | dbg_bvr8, |
162 | dbg_bvr9, |
163 | dbg_bvr10, |
164 | dbg_bvr11, |
165 | dbg_bvr12, |
166 | dbg_bvr13, |
167 | dbg_bvr14, |
168 | dbg_bvr15, |
169 | |
170 | dbg_bcr0, |
171 | dbg_bcr1, |
172 | dbg_bcr2, |
173 | dbg_bcr3, |
174 | dbg_bcr4, |
175 | dbg_bcr5, |
176 | dbg_bcr6, |
177 | dbg_bcr7, |
178 | dbg_bcr8, |
179 | dbg_bcr9, |
180 | dbg_bcr10, |
181 | dbg_bcr11, |
182 | dbg_bcr12, |
183 | dbg_bcr13, |
184 | dbg_bcr14, |
185 | dbg_bcr15, |
186 | |
187 | dbg_wvr0, |
188 | dbg_wvr1, |
189 | dbg_wvr2, |
190 | dbg_wvr3, |
191 | dbg_wvr4, |
192 | dbg_wvr5, |
193 | dbg_wvr6, |
194 | dbg_wvr7, |
195 | dbg_wvr8, |
196 | dbg_wvr9, |
197 | dbg_wvr10, |
198 | dbg_wvr11, |
199 | dbg_wvr12, |
200 | dbg_wvr13, |
201 | dbg_wvr14, |
202 | dbg_wvr15, |
203 | |
204 | dbg_wcr0, |
205 | dbg_wcr1, |
206 | dbg_wcr2, |
207 | dbg_wcr3, |
208 | dbg_wcr4, |
209 | dbg_wcr5, |
210 | dbg_wcr6, |
211 | dbg_wcr7, |
212 | dbg_wcr8, |
213 | dbg_wcr9, |
214 | dbg_wcr10, |
215 | dbg_wcr11, |
216 | dbg_wcr12, |
217 | dbg_wcr13, |
218 | dbg_wcr14, |
219 | dbg_wcr15, |
220 | |
221 | k_num_registers |
222 | }; |
223 | |
224 | static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM}; |
225 | static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM}; |
226 | static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM}; |
227 | static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM}; |
228 | static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM}; |
229 | static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM}; |
230 | static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM}; |
231 | static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM}; |
232 | static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM}; |
233 | static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM}; |
234 | static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM}; |
235 | static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM}; |
236 | static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM}; |
237 | static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM}; |
238 | static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM}; |
239 | static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM}; |
240 | static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM}; |
241 | static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM}; |
242 | static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM}; |
243 | static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM}; |
244 | static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM}; |
245 | static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM}; |
246 | static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM}; |
247 | static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM}; |
248 | static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM}; |
249 | static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM}; |
250 | static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM}; |
251 | static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM}; |
252 | static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; |
253 | static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; |
254 | static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; |
255 | static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; |
256 | |
257 | static uint32_t g_d0_invalidates[] = {fpu_q0, fpu_s0, fpu_s1, |
258 | LLDB_INVALID_REGNUM}; |
259 | static uint32_t g_d1_invalidates[] = {fpu_q0, fpu_s2, fpu_s3, |
260 | LLDB_INVALID_REGNUM}; |
261 | static uint32_t g_d2_invalidates[] = {fpu_q1, fpu_s4, fpu_s5, |
262 | LLDB_INVALID_REGNUM}; |
263 | static uint32_t g_d3_invalidates[] = {fpu_q1, fpu_s6, fpu_s7, |
264 | LLDB_INVALID_REGNUM}; |
265 | static uint32_t g_d4_invalidates[] = {fpu_q2, fpu_s8, fpu_s9, |
266 | LLDB_INVALID_REGNUM}; |
267 | static uint32_t g_d5_invalidates[] = {fpu_q2, fpu_s10, fpu_s11, |
268 | LLDB_INVALID_REGNUM}; |
269 | static uint32_t g_d6_invalidates[] = {fpu_q3, fpu_s12, fpu_s13, |
270 | LLDB_INVALID_REGNUM}; |
271 | static uint32_t g_d7_invalidates[] = {fpu_q3, fpu_s14, fpu_s15, |
272 | LLDB_INVALID_REGNUM}; |
273 | static uint32_t g_d8_invalidates[] = {fpu_q4, fpu_s16, fpu_s17, |
274 | LLDB_INVALID_REGNUM}; |
275 | static uint32_t g_d9_invalidates[] = {fpu_q4, fpu_s18, fpu_s19, |
276 | LLDB_INVALID_REGNUM}; |
277 | static uint32_t g_d10_invalidates[] = {fpu_q5, fpu_s20, fpu_s21, |
278 | LLDB_INVALID_REGNUM}; |
279 | static uint32_t g_d11_invalidates[] = {fpu_q5, fpu_s22, fpu_s23, |
280 | LLDB_INVALID_REGNUM}; |
281 | static uint32_t g_d12_invalidates[] = {fpu_q6, fpu_s24, fpu_s25, |
282 | LLDB_INVALID_REGNUM}; |
283 | static uint32_t g_d13_invalidates[] = {fpu_q6, fpu_s26, fpu_s27, |
284 | LLDB_INVALID_REGNUM}; |
285 | static uint32_t g_d14_invalidates[] = {fpu_q7, fpu_s28, fpu_s29, |
286 | LLDB_INVALID_REGNUM}; |
287 | static uint32_t g_d15_invalidates[] = {fpu_q7, fpu_s30, fpu_s31, |
288 | LLDB_INVALID_REGNUM}; |
289 | static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; |
290 | static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; |
291 | static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; |
292 | static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; |
293 | static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM}; |
294 | static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM}; |
295 | static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM}; |
296 | static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM}; |
297 | static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM}; |
298 | static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM}; |
299 | static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM}; |
300 | static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM}; |
301 | static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; |
302 | static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; |
303 | static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; |
304 | static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; |
305 | |
306 | static uint32_t g_q0_invalidates[] = { |
307 | fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM}; |
308 | static uint32_t g_q1_invalidates[] = { |
309 | fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM}; |
310 | static uint32_t g_q2_invalidates[] = { |
311 | fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM}; |
312 | static uint32_t g_q3_invalidates[] = { |
313 | fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM}; |
314 | static uint32_t g_q4_invalidates[] = { |
315 | fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM}; |
316 | static uint32_t g_q5_invalidates[] = { |
317 | fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM}; |
318 | static uint32_t g_q6_invalidates[] = { |
319 | fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM}; |
320 | static uint32_t g_q7_invalidates[] = { |
321 | fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM}; |
322 | static uint32_t g_q8_invalidates[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM}; |
323 | static uint32_t g_q9_invalidates[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM}; |
324 | static uint32_t g_q10_invalidates[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM}; |
325 | static uint32_t g_q11_invalidates[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM}; |
326 | static uint32_t g_q12_invalidates[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM}; |
327 | static uint32_t g_q13_invalidates[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM}; |
328 | static uint32_t g_q14_invalidates[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM}; |
329 | static uint32_t g_q15_invalidates[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM}; |
330 | |
331 | static uint32_t g_q0_contained[] = {fpu_q0, LLDB_INVALID_REGNUM}; |
332 | static uint32_t g_q1_contained[] = {fpu_q1, LLDB_INVALID_REGNUM}; |
333 | static uint32_t g_q2_contained[] = {fpu_q2, LLDB_INVALID_REGNUM}; |
334 | static uint32_t g_q3_contained[] = {fpu_q3, LLDB_INVALID_REGNUM}; |
335 | static uint32_t g_q4_contained[] = {fpu_q4, LLDB_INVALID_REGNUM}; |
336 | static uint32_t g_q5_contained[] = {fpu_q5, LLDB_INVALID_REGNUM}; |
337 | static uint32_t g_q6_contained[] = {fpu_q6, LLDB_INVALID_REGNUM}; |
338 | static uint32_t g_q7_contained[] = {fpu_q7, LLDB_INVALID_REGNUM}; |
339 | static uint32_t g_q8_contained[] = {fpu_q8, LLDB_INVALID_REGNUM}; |
340 | static uint32_t g_q9_contained[] = {fpu_q9, LLDB_INVALID_REGNUM}; |
341 | static uint32_t g_q10_contained[] = {fpu_q10, LLDB_INVALID_REGNUM}; |
342 | static uint32_t g_q11_contained[] = {fpu_q11, LLDB_INVALID_REGNUM}; |
343 | static uint32_t g_q12_contained[] = {fpu_q12, LLDB_INVALID_REGNUM}; |
344 | static uint32_t g_q13_contained[] = {fpu_q13, LLDB_INVALID_REGNUM}; |
345 | static uint32_t g_q14_contained[] = {fpu_q14, LLDB_INVALID_REGNUM}; |
346 | static uint32_t g_q15_contained[] = {fpu_q15, LLDB_INVALID_REGNUM}; |
347 | |
348 | #define FPU_REG(name, size, offset, qreg) \ |
349 | { \ |
350 | #name, nullptr, size, FPU_OFFSET(offset), eEncodingIEEE754, eFormatFloat, \ |
351 | {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ |
352 | LLDB_INVALID_REGNUM, fpu_##name }, \ |
353 | g_##qreg##_contained, g_##name##_invalidates, nullptr, \ |
354 | } |
355 | |
356 | #define FPU_QREG(name, offset) \ |
357 | { \ |
358 | #name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \ |
359 | eFormatVectorOfUInt8, \ |
360 | {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ |
361 | LLDB_INVALID_REGNUM, fpu_##name }, \ |
362 | nullptr, g_##name##_invalidates, nullptr, \ |
363 | } |
364 | |
365 | static RegisterInfo g_register_infos_arm[] = { |
366 | // NAME ALT SZ OFFSET ENCODING FORMAT |
367 | // EH_FRAME DWARF GENERIC |
368 | // PROCESS PLUGIN LLDB NATIVE VALUE REGS INVALIDATE REGS |
369 | // =========== ======= == ============== ================ |
370 | // ==================== =================== =================== |
371 | // ========================== =================== ============= |
372 | // ============== ================= |
373 | { |
374 | .name: "r0" , |
375 | .alt_name: nullptr, |
376 | .byte_size: 4, |
377 | GPR_OFFSET(0), |
378 | .encoding: eEncodingUint, |
379 | .format: eFormatHex, |
380 | .kinds: {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, |
381 | gpr_r0}, |
382 | .value_regs: nullptr, |
383 | .invalidate_regs: nullptr, |
384 | .flags_type: nullptr, |
385 | }, |
386 | { |
387 | .name: "r1" , |
388 | .alt_name: nullptr, |
389 | .byte_size: 4, |
390 | GPR_OFFSET(1), |
391 | .encoding: eEncodingUint, |
392 | .format: eFormatHex, |
393 | .kinds: {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, |
394 | gpr_r1}, |
395 | .value_regs: nullptr, |
396 | .invalidate_regs: nullptr, |
397 | .flags_type: nullptr, |
398 | }, |
399 | { |
400 | .name: "r2" , |
401 | .alt_name: nullptr, |
402 | .byte_size: 4, |
403 | GPR_OFFSET(2), |
404 | .encoding: eEncodingUint, |
405 | .format: eFormatHex, |
406 | .kinds: {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, |
407 | gpr_r2}, |
408 | .value_regs: nullptr, |
409 | .invalidate_regs: nullptr, |
410 | .flags_type: nullptr, |
411 | }, |
412 | { |
413 | .name: "r3" , |
414 | .alt_name: nullptr, |
415 | .byte_size: 4, |
416 | GPR_OFFSET(3), |
417 | .encoding: eEncodingUint, |
418 | .format: eFormatHex, |
419 | .kinds: {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, |
420 | gpr_r3}, |
421 | .value_regs: nullptr, |
422 | .invalidate_regs: nullptr, |
423 | .flags_type: nullptr, |
424 | }, |
425 | { |
426 | .name: "r4" , |
427 | .alt_name: nullptr, |
428 | .byte_size: 4, |
429 | GPR_OFFSET(4), |
430 | .encoding: eEncodingUint, |
431 | .format: eFormatHex, |
432 | .kinds: {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
433 | gpr_r4}, |
434 | .value_regs: nullptr, |
435 | .invalidate_regs: nullptr, |
436 | .flags_type: nullptr, |
437 | }, |
438 | { |
439 | .name: "r5" , |
440 | .alt_name: nullptr, |
441 | .byte_size: 4, |
442 | GPR_OFFSET(5), |
443 | .encoding: eEncodingUint, |
444 | .format: eFormatHex, |
445 | .kinds: {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
446 | gpr_r5}, |
447 | .value_regs: nullptr, |
448 | .invalidate_regs: nullptr, |
449 | .flags_type: nullptr, |
450 | }, |
451 | { |
452 | .name: "r6" , |
453 | .alt_name: nullptr, |
454 | .byte_size: 4, |
455 | GPR_OFFSET(6), |
456 | .encoding: eEncodingUint, |
457 | .format: eFormatHex, |
458 | .kinds: {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
459 | gpr_r6}, |
460 | .value_regs: nullptr, |
461 | .invalidate_regs: nullptr, |
462 | .flags_type: nullptr, |
463 | }, |
464 | { |
465 | .name: "r7" , |
466 | .alt_name: nullptr, |
467 | .byte_size: 4, |
468 | GPR_OFFSET(7), |
469 | .encoding: eEncodingUint, |
470 | .format: eFormatHex, |
471 | .kinds: {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
472 | gpr_r7}, |
473 | .value_regs: nullptr, |
474 | .invalidate_regs: nullptr, |
475 | .flags_type: nullptr, |
476 | }, |
477 | { |
478 | .name: "r8" , |
479 | .alt_name: nullptr, |
480 | .byte_size: 4, |
481 | GPR_OFFSET(8), |
482 | .encoding: eEncodingUint, |
483 | .format: eFormatHex, |
484 | .kinds: {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
485 | gpr_r8}, |
486 | .value_regs: nullptr, |
487 | .invalidate_regs: nullptr, |
488 | .flags_type: nullptr, |
489 | }, |
490 | { |
491 | .name: "r9" , |
492 | .alt_name: nullptr, |
493 | .byte_size: 4, |
494 | GPR_OFFSET(9), |
495 | .encoding: eEncodingUint, |
496 | .format: eFormatHex, |
497 | .kinds: {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
498 | gpr_r9}, |
499 | .value_regs: nullptr, |
500 | .invalidate_regs: nullptr, |
501 | .flags_type: nullptr, |
502 | }, |
503 | { |
504 | .name: "r10" , |
505 | .alt_name: nullptr, |
506 | .byte_size: 4, |
507 | GPR_OFFSET(10), |
508 | .encoding: eEncodingUint, |
509 | .format: eFormatHex, |
510 | .kinds: {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
511 | gpr_r10}, |
512 | .value_regs: nullptr, |
513 | .invalidate_regs: nullptr, |
514 | .flags_type: nullptr, |
515 | }, |
516 | { |
517 | .name: "r11" , |
518 | .alt_name: nullptr, |
519 | .byte_size: 4, |
520 | GPR_OFFSET(11), |
521 | .encoding: eEncodingUint, |
522 | .format: eFormatHex, |
523 | .kinds: {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, |
524 | gpr_r11}, |
525 | .value_regs: nullptr, |
526 | .invalidate_regs: nullptr, |
527 | .flags_type: nullptr, |
528 | }, |
529 | { |
530 | .name: "r12" , |
531 | .alt_name: nullptr, |
532 | .byte_size: 4, |
533 | GPR_OFFSET(12), |
534 | .encoding: eEncodingUint, |
535 | .format: eFormatHex, |
536 | .kinds: {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
537 | gpr_r12}, |
538 | .value_regs: nullptr, |
539 | .invalidate_regs: nullptr, |
540 | .flags_type: nullptr, |
541 | }, |
542 | { |
543 | .name: "sp" , |
544 | .alt_name: "r13" , |
545 | .byte_size: 4, |
546 | GPR_OFFSET(13), |
547 | .encoding: eEncodingUint, |
548 | .format: eFormatHex, |
549 | .kinds: {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, |
550 | gpr_sp}, |
551 | .value_regs: nullptr, |
552 | .invalidate_regs: nullptr, |
553 | .flags_type: nullptr, |
554 | }, |
555 | { |
556 | .name: "lr" , |
557 | .alt_name: "r14" , |
558 | .byte_size: 4, |
559 | GPR_OFFSET(14), |
560 | .encoding: eEncodingUint, |
561 | .format: eFormatHex, |
562 | .kinds: {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, |
563 | gpr_lr}, |
564 | .value_regs: nullptr, |
565 | .invalidate_regs: nullptr, |
566 | .flags_type: nullptr, |
567 | }, |
568 | { |
569 | .name: "pc" , |
570 | .alt_name: "r15" , |
571 | .byte_size: 4, |
572 | GPR_OFFSET(15), |
573 | .encoding: eEncodingUint, |
574 | .format: eFormatHex, |
575 | .kinds: {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, |
576 | gpr_pc}, |
577 | .value_regs: nullptr, |
578 | .invalidate_regs: nullptr, |
579 | .flags_type: nullptr, |
580 | }, |
581 | { |
582 | .name: "cpsr" , |
583 | .alt_name: "psr" , |
584 | .byte_size: 4, |
585 | GPR_OFFSET(16), |
586 | .encoding: eEncodingUint, |
587 | .format: eFormatHex, |
588 | .kinds: {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, |
589 | LLDB_INVALID_REGNUM, gpr_cpsr}, |
590 | .value_regs: nullptr, |
591 | .invalidate_regs: nullptr, |
592 | .flags_type: nullptr, |
593 | }, |
594 | |
595 | FPU_REG(s0, 4, 0, q0), |
596 | FPU_REG(s1, 4, 1, q0), |
597 | FPU_REG(s2, 4, 2, q0), |
598 | FPU_REG(s3, 4, 3, q0), |
599 | FPU_REG(s4, 4, 4, q1), |
600 | FPU_REG(s5, 4, 5, q1), |
601 | FPU_REG(s6, 4, 6, q1), |
602 | FPU_REG(s7, 4, 7, q1), |
603 | FPU_REG(s8, 4, 8, q2), |
604 | FPU_REG(s9, 4, 9, q2), |
605 | FPU_REG(s10, 4, 10, q2), |
606 | FPU_REG(s11, 4, 11, q2), |
607 | FPU_REG(s12, 4, 12, q3), |
608 | FPU_REG(s13, 4, 13, q3), |
609 | FPU_REG(s14, 4, 14, q3), |
610 | FPU_REG(s15, 4, 15, q3), |
611 | FPU_REG(s16, 4, 16, q4), |
612 | FPU_REG(s17, 4, 17, q4), |
613 | FPU_REG(s18, 4, 18, q4), |
614 | FPU_REG(s19, 4, 19, q4), |
615 | FPU_REG(s20, 4, 20, q5), |
616 | FPU_REG(s21, 4, 21, q5), |
617 | FPU_REG(s22, 4, 22, q5), |
618 | FPU_REG(s23, 4, 23, q5), |
619 | FPU_REG(s24, 4, 24, q6), |
620 | FPU_REG(s25, 4, 25, q6), |
621 | FPU_REG(s26, 4, 26, q6), |
622 | FPU_REG(s27, 4, 27, q6), |
623 | FPU_REG(s28, 4, 28, q7), |
624 | FPU_REG(s29, 4, 29, q7), |
625 | FPU_REG(s30, 4, 30, q7), |
626 | FPU_REG(s31, 4, 31, q7), |
627 | |
628 | { |
629 | .name: "fpscr" , |
630 | .alt_name: nullptr, |
631 | .byte_size: 4, |
632 | FPSCR_OFFSET, |
633 | .encoding: eEncodingUint, |
634 | .format: eFormatHex, |
635 | .kinds: {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
636 | LLDB_INVALID_REGNUM, fpu_fpscr}, |
637 | .value_regs: nullptr, |
638 | .invalidate_regs: nullptr, |
639 | .flags_type: nullptr, |
640 | }, |
641 | |
642 | FPU_REG(d0, 8, 0, q0), |
643 | FPU_REG(d1, 8, 2, q0), |
644 | FPU_REG(d2, 8, 4, q1), |
645 | FPU_REG(d3, 8, 6, q1), |
646 | FPU_REG(d4, 8, 8, q2), |
647 | FPU_REG(d5, 8, 10, q2), |
648 | FPU_REG(d6, 8, 12, q3), |
649 | FPU_REG(d7, 8, 14, q3), |
650 | FPU_REG(d8, 8, 16, q4), |
651 | FPU_REG(d9, 8, 18, q4), |
652 | FPU_REG(d10, 8, 20, q5), |
653 | FPU_REG(d11, 8, 22, q5), |
654 | FPU_REG(d12, 8, 24, q6), |
655 | FPU_REG(d13, 8, 26, q6), |
656 | FPU_REG(d14, 8, 28, q7), |
657 | FPU_REG(d15, 8, 30, q7), |
658 | FPU_REG(d16, 8, 32, q8), |
659 | FPU_REG(d17, 8, 34, q8), |
660 | FPU_REG(d18, 8, 36, q9), |
661 | FPU_REG(d19, 8, 38, q9), |
662 | FPU_REG(d20, 8, 40, q10), |
663 | FPU_REG(d21, 8, 42, q10), |
664 | FPU_REG(d22, 8, 44, q11), |
665 | FPU_REG(d23, 8, 46, q11), |
666 | FPU_REG(d24, 8, 48, q12), |
667 | FPU_REG(d25, 8, 50, q12), |
668 | FPU_REG(d26, 8, 52, q13), |
669 | FPU_REG(d27, 8, 54, q13), |
670 | FPU_REG(d28, 8, 56, q14), |
671 | FPU_REG(d29, 8, 58, q14), |
672 | FPU_REG(d30, 8, 60, q15), |
673 | FPU_REG(d31, 8, 62, q15), |
674 | |
675 | FPU_QREG(q0, 0), |
676 | FPU_QREG(q1, 4), |
677 | FPU_QREG(q2, 8), |
678 | FPU_QREG(q3, 12), |
679 | FPU_QREG(q4, 16), |
680 | FPU_QREG(q5, 20), |
681 | FPU_QREG(q6, 24), |
682 | FPU_QREG(q7, 28), |
683 | FPU_QREG(q8, 32), |
684 | FPU_QREG(q9, 36), |
685 | FPU_QREG(q10, 40), |
686 | FPU_QREG(q11, 44), |
687 | FPU_QREG(q12, 48), |
688 | FPU_QREG(q13, 52), |
689 | FPU_QREG(q14, 56), |
690 | FPU_QREG(q15, 60), |
691 | |
692 | { |
693 | .name: "exception" , |
694 | .alt_name: nullptr, |
695 | .byte_size: 4, |
696 | EXC_OFFSET(0), |
697 | .encoding: eEncodingUint, |
698 | .format: eFormatHex, |
699 | .kinds: {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
700 | LLDB_INVALID_REGNUM, exc_exception}, |
701 | .value_regs: nullptr, |
702 | .invalidate_regs: nullptr, |
703 | .flags_type: nullptr, |
704 | }, |
705 | { |
706 | .name: "fsr" , |
707 | .alt_name: nullptr, |
708 | .byte_size: 4, |
709 | EXC_OFFSET(1), |
710 | .encoding: eEncodingUint, |
711 | .format: eFormatHex, |
712 | .kinds: {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
713 | LLDB_INVALID_REGNUM, exc_fsr}, |
714 | .value_regs: nullptr, |
715 | .invalidate_regs: nullptr, |
716 | .flags_type: nullptr, |
717 | }, |
718 | { |
719 | .name: "far" , |
720 | .alt_name: nullptr, |
721 | .byte_size: 4, |
722 | EXC_OFFSET(2), |
723 | .encoding: eEncodingUint, |
724 | .format: eFormatHex, |
725 | .kinds: {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, |
726 | LLDB_INVALID_REGNUM, exc_far}, |
727 | .value_regs: nullptr, |
728 | .invalidate_regs: nullptr, |
729 | .flags_type: nullptr, |
730 | }, |
731 | |
732 | {DEFINE_DBG(bvr, 0)}, |
733 | {DEFINE_DBG(bvr, 1)}, |
734 | {DEFINE_DBG(bvr, 2)}, |
735 | {DEFINE_DBG(bvr, 3)}, |
736 | {DEFINE_DBG(bvr, 4)}, |
737 | {DEFINE_DBG(bvr, 5)}, |
738 | {DEFINE_DBG(bvr, 6)}, |
739 | {DEFINE_DBG(bvr, 7)}, |
740 | {DEFINE_DBG(bvr, 8)}, |
741 | {DEFINE_DBG(bvr, 9)}, |
742 | {DEFINE_DBG(bvr, 10)}, |
743 | {DEFINE_DBG(bvr, 11)}, |
744 | {DEFINE_DBG(bvr, 12)}, |
745 | {DEFINE_DBG(bvr, 13)}, |
746 | {DEFINE_DBG(bvr, 14)}, |
747 | {DEFINE_DBG(bvr, 15)}, |
748 | |
749 | {DEFINE_DBG(bcr, 0)}, |
750 | {DEFINE_DBG(bcr, 1)}, |
751 | {DEFINE_DBG(bcr, 2)}, |
752 | {DEFINE_DBG(bcr, 3)}, |
753 | {DEFINE_DBG(bcr, 4)}, |
754 | {DEFINE_DBG(bcr, 5)}, |
755 | {DEFINE_DBG(bcr, 6)}, |
756 | {DEFINE_DBG(bcr, 7)}, |
757 | {DEFINE_DBG(bcr, 8)}, |
758 | {DEFINE_DBG(bcr, 9)}, |
759 | {DEFINE_DBG(bcr, 10)}, |
760 | {DEFINE_DBG(bcr, 11)}, |
761 | {DEFINE_DBG(bcr, 12)}, |
762 | {DEFINE_DBG(bcr, 13)}, |
763 | {DEFINE_DBG(bcr, 14)}, |
764 | {DEFINE_DBG(bcr, 15)}, |
765 | |
766 | {DEFINE_DBG(wvr, 0)}, |
767 | {DEFINE_DBG(wvr, 1)}, |
768 | {DEFINE_DBG(wvr, 2)}, |
769 | {DEFINE_DBG(wvr, 3)}, |
770 | {DEFINE_DBG(wvr, 4)}, |
771 | {DEFINE_DBG(wvr, 5)}, |
772 | {DEFINE_DBG(wvr, 6)}, |
773 | {DEFINE_DBG(wvr, 7)}, |
774 | {DEFINE_DBG(wvr, 8)}, |
775 | {DEFINE_DBG(wvr, 9)}, |
776 | {DEFINE_DBG(wvr, 10)}, |
777 | {DEFINE_DBG(wvr, 11)}, |
778 | {DEFINE_DBG(wvr, 12)}, |
779 | {DEFINE_DBG(wvr, 13)}, |
780 | {DEFINE_DBG(wvr, 14)}, |
781 | {DEFINE_DBG(wvr, 15)}, |
782 | |
783 | {DEFINE_DBG(wcr, 0)}, |
784 | {DEFINE_DBG(wcr, 1)}, |
785 | {DEFINE_DBG(wcr, 2)}, |
786 | {DEFINE_DBG(wcr, 3)}, |
787 | {DEFINE_DBG(wcr, 4)}, |
788 | {DEFINE_DBG(wcr, 5)}, |
789 | {DEFINE_DBG(wcr, 6)}, |
790 | {DEFINE_DBG(wcr, 7)}, |
791 | {DEFINE_DBG(wcr, 8)}, |
792 | {DEFINE_DBG(wcr, 9)}, |
793 | {DEFINE_DBG(wcr, 10)}, |
794 | {DEFINE_DBG(wcr, 11)}, |
795 | {DEFINE_DBG(wcr, 12)}, |
796 | {DEFINE_DBG(wcr, 13)}, |
797 | {DEFINE_DBG(wcr, 14)}, |
798 | {DEFINE_DBG(wcr, 15)}}; |
799 | |
800 | #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT |
801 | |