1//===-- RegisterInfos_arm64_sve.h -------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
10
11enum {
12 sve_vg = exc_far,
13
14 sve_z0,
15 sve_z1,
16 sve_z2,
17 sve_z3,
18 sve_z4,
19 sve_z5,
20 sve_z6,
21 sve_z7,
22 sve_z8,
23 sve_z9,
24 sve_z10,
25 sve_z11,
26 sve_z12,
27 sve_z13,
28 sve_z14,
29 sve_z15,
30 sve_z16,
31 sve_z17,
32 sve_z18,
33 sve_z19,
34 sve_z20,
35 sve_z21,
36 sve_z22,
37 sve_z23,
38 sve_z24,
39 sve_z25,
40 sve_z26,
41 sve_z27,
42 sve_z28,
43 sve_z29,
44 sve_z30,
45 sve_z31,
46
47 sve_p0,
48 sve_p1,
49 sve_p2,
50 sve_p3,
51 sve_p4,
52 sve_p5,
53 sve_p6,
54 sve_p7,
55 sve_p8,
56 sve_p9,
57 sve_p10,
58 sve_p11,
59 sve_p12,
60 sve_p13,
61 sve_p14,
62 sve_p15,
63
64 sve_ffr,
65};
66
67#ifndef SVE_OFFSET_VG
68#error SVE_OFFSET_VG must be defined before including this header file
69#endif
70
71static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0,
72 LLDB_INVALID_REGNUM};
73static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1,
74 LLDB_INVALID_REGNUM};
75static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2,
76 LLDB_INVALID_REGNUM};
77static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3,
78 LLDB_INVALID_REGNUM};
79static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4,
80 LLDB_INVALID_REGNUM};
81static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5,
82 LLDB_INVALID_REGNUM};
83static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6,
84 LLDB_INVALID_REGNUM};
85static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7,
86 LLDB_INVALID_REGNUM};
87static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8,
88 LLDB_INVALID_REGNUM};
89static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9,
90 LLDB_INVALID_REGNUM};
91static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10,
92 LLDB_INVALID_REGNUM};
93static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11,
94 LLDB_INVALID_REGNUM};
95static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12,
96 LLDB_INVALID_REGNUM};
97static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13,
98 LLDB_INVALID_REGNUM};
99static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14,
100 LLDB_INVALID_REGNUM};
101static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15,
102 LLDB_INVALID_REGNUM};
103static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16,
104 LLDB_INVALID_REGNUM};
105static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17,
106 LLDB_INVALID_REGNUM};
107static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18,
108 LLDB_INVALID_REGNUM};
109static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19,
110 LLDB_INVALID_REGNUM};
111static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20,
112 LLDB_INVALID_REGNUM};
113static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21,
114 LLDB_INVALID_REGNUM};
115static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22,
116 LLDB_INVALID_REGNUM};
117static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23,
118 LLDB_INVALID_REGNUM};
119static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24,
120 LLDB_INVALID_REGNUM};
121static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25,
122 LLDB_INVALID_REGNUM};
123static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26,
124 LLDB_INVALID_REGNUM};
125static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27,
126 LLDB_INVALID_REGNUM};
127static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28,
128 LLDB_INVALID_REGNUM};
129static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29,
130 LLDB_INVALID_REGNUM};
131static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30,
132 LLDB_INVALID_REGNUM};
133static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31,
134 LLDB_INVALID_REGNUM};
135
136static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0, fpu_s0,
137 LLDB_INVALID_REGNUM};
138static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1, fpu_s1,
139 LLDB_INVALID_REGNUM};
140static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2, fpu_s2,
141 LLDB_INVALID_REGNUM};
142static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3, fpu_s3,
143 LLDB_INVALID_REGNUM};
144static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4, fpu_s4,
145 LLDB_INVALID_REGNUM};
146static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5, fpu_s5,
147 LLDB_INVALID_REGNUM};
148static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6, fpu_s6,
149 LLDB_INVALID_REGNUM};
150static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7, fpu_s7,
151 LLDB_INVALID_REGNUM};
152static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8, fpu_s8,
153 LLDB_INVALID_REGNUM};
154static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9, fpu_s9,
155 LLDB_INVALID_REGNUM};
156static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10, fpu_s10,
157 LLDB_INVALID_REGNUM};
158static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11, fpu_s11,
159 LLDB_INVALID_REGNUM};
160static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12, fpu_s12,
161 LLDB_INVALID_REGNUM};
162static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13, fpu_s13,
163 LLDB_INVALID_REGNUM};
164static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14, fpu_s14,
165 LLDB_INVALID_REGNUM};
166static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15, fpu_s15,
167 LLDB_INVALID_REGNUM};
168static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16, fpu_s16,
169 LLDB_INVALID_REGNUM};
170static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17, fpu_s17,
171 LLDB_INVALID_REGNUM};
172static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18, fpu_s18,
173 LLDB_INVALID_REGNUM};
174static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19, fpu_s19,
175 LLDB_INVALID_REGNUM};
176static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20, fpu_s20,
177 LLDB_INVALID_REGNUM};
178static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21, fpu_s21,
179 LLDB_INVALID_REGNUM};
180static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22, fpu_s22,
181 LLDB_INVALID_REGNUM};
182static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23, fpu_s23,
183 LLDB_INVALID_REGNUM};
184static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24, fpu_s24,
185 LLDB_INVALID_REGNUM};
186static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25, fpu_s25,
187 LLDB_INVALID_REGNUM};
188static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26, fpu_s26,
189 LLDB_INVALID_REGNUM};
190static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27, fpu_s27,
191 LLDB_INVALID_REGNUM};
192static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28, fpu_s28,
193 LLDB_INVALID_REGNUM};
194static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29, fpu_s29,
195 LLDB_INVALID_REGNUM};
196static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30, fpu_s30,
197 LLDB_INVALID_REGNUM};
198static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31, fpu_s31,
199 LLDB_INVALID_REGNUM};
200
201static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0, fpu_s0,
202 LLDB_INVALID_REGNUM};
203static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1, fpu_s1,
204 LLDB_INVALID_REGNUM};
205static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2, fpu_s2,
206 LLDB_INVALID_REGNUM};
207static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3, fpu_s3,
208 LLDB_INVALID_REGNUM};
209static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4, fpu_s4,
210 LLDB_INVALID_REGNUM};
211static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5, fpu_s5,
212 LLDB_INVALID_REGNUM};
213static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6, fpu_s6,
214 LLDB_INVALID_REGNUM};
215static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7, fpu_s7,
216 LLDB_INVALID_REGNUM};
217static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8, fpu_s8,
218 LLDB_INVALID_REGNUM};
219static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9, fpu_s9,
220 LLDB_INVALID_REGNUM};
221static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10, fpu_s10,
222 LLDB_INVALID_REGNUM};
223static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11, fpu_s11,
224 LLDB_INVALID_REGNUM};
225static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12, fpu_s12,
226 LLDB_INVALID_REGNUM};
227static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13, fpu_s13,
228 LLDB_INVALID_REGNUM};
229static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14, fpu_s14,
230 LLDB_INVALID_REGNUM};
231static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15, fpu_s15,
232 LLDB_INVALID_REGNUM};
233static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16, fpu_s16,
234 LLDB_INVALID_REGNUM};
235static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17, fpu_s17,
236 LLDB_INVALID_REGNUM};
237static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18, fpu_s18,
238 LLDB_INVALID_REGNUM};
239static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19, fpu_s19,
240 LLDB_INVALID_REGNUM};
241static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20, fpu_s20,
242 LLDB_INVALID_REGNUM};
243static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21, fpu_s21,
244 LLDB_INVALID_REGNUM};
245static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22, fpu_s22,
246 LLDB_INVALID_REGNUM};
247static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23, fpu_s23,
248 LLDB_INVALID_REGNUM};
249static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24, fpu_s24,
250 LLDB_INVALID_REGNUM};
251static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25, fpu_s25,
252 LLDB_INVALID_REGNUM};
253static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26, fpu_s26,
254 LLDB_INVALID_REGNUM};
255static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27, fpu_s27,
256 LLDB_INVALID_REGNUM};
257static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28, fpu_s28,
258 LLDB_INVALID_REGNUM};
259static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29, fpu_s29,
260 LLDB_INVALID_REGNUM};
261static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30, fpu_s30,
262 LLDB_INVALID_REGNUM};
263static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31, fpu_s31,
264 LLDB_INVALID_REGNUM};
265
266static uint32_t g_contained_z0[] = {sve_z0, LLDB_INVALID_REGNUM};
267static uint32_t g_contained_z1[] = {sve_z1, LLDB_INVALID_REGNUM};
268static uint32_t g_contained_z2[] = {sve_z2, LLDB_INVALID_REGNUM};
269static uint32_t g_contained_z3[] = {sve_z3, LLDB_INVALID_REGNUM};
270static uint32_t g_contained_z4[] = {sve_z4, LLDB_INVALID_REGNUM};
271static uint32_t g_contained_z5[] = {sve_z5, LLDB_INVALID_REGNUM};
272static uint32_t g_contained_z6[] = {sve_z6, LLDB_INVALID_REGNUM};
273static uint32_t g_contained_z7[] = {sve_z7, LLDB_INVALID_REGNUM};
274static uint32_t g_contained_z8[] = {sve_z8, LLDB_INVALID_REGNUM};
275static uint32_t g_contained_z9[] = {sve_z9, LLDB_INVALID_REGNUM};
276static uint32_t g_contained_z10[] = {sve_z10, LLDB_INVALID_REGNUM};
277static uint32_t g_contained_z11[] = {sve_z11, LLDB_INVALID_REGNUM};
278static uint32_t g_contained_z12[] = {sve_z12, LLDB_INVALID_REGNUM};
279static uint32_t g_contained_z13[] = {sve_z13, LLDB_INVALID_REGNUM};
280static uint32_t g_contained_z14[] = {sve_z14, LLDB_INVALID_REGNUM};
281static uint32_t g_contained_z15[] = {sve_z15, LLDB_INVALID_REGNUM};
282static uint32_t g_contained_z16[] = {sve_z16, LLDB_INVALID_REGNUM};
283static uint32_t g_contained_z17[] = {sve_z17, LLDB_INVALID_REGNUM};
284static uint32_t g_contained_z18[] = {sve_z18, LLDB_INVALID_REGNUM};
285static uint32_t g_contained_z19[] = {sve_z19, LLDB_INVALID_REGNUM};
286static uint32_t g_contained_z20[] = {sve_z20, LLDB_INVALID_REGNUM};
287static uint32_t g_contained_z21[] = {sve_z21, LLDB_INVALID_REGNUM};
288static uint32_t g_contained_z22[] = {sve_z22, LLDB_INVALID_REGNUM};
289static uint32_t g_contained_z23[] = {sve_z23, LLDB_INVALID_REGNUM};
290static uint32_t g_contained_z24[] = {sve_z24, LLDB_INVALID_REGNUM};
291static uint32_t g_contained_z25[] = {sve_z25, LLDB_INVALID_REGNUM};
292static uint32_t g_contained_z26[] = {sve_z26, LLDB_INVALID_REGNUM};
293static uint32_t g_contained_z27[] = {sve_z27, LLDB_INVALID_REGNUM};
294static uint32_t g_contained_z28[] = {sve_z28, LLDB_INVALID_REGNUM};
295static uint32_t g_contained_z29[] = {sve_z29, LLDB_INVALID_REGNUM};
296static uint32_t g_contained_z30[] = {sve_z30, LLDB_INVALID_REGNUM};
297static uint32_t g_contained_z31[] = {sve_z31, LLDB_INVALID_REGNUM};
298
299#define VG_OFFSET_NAME(reg) SVE_OFFSET_VG
300
301#define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM)
302#define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM)
303
304// Default offset SVE Z registers and all corresponding pseudo registers
305// ( S, D and V registers) is zero and will be configured during execution.
306
307// clang-format off
308
309// Defines sve pseudo vector (V) register with 16-byte size
310#define DEFINE_VREG_SVE(vreg, zreg) \
311 { \
312 #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
313 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
314 nullptr, \
315 }
316
317// Defines S and D pseudo registers mapping over corresponding vector register
318#define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \
319 { \
320 #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \
321 LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \
322 nullptr, \
323 }
324
325// Defines a Z vector register with 16-byte default size
326#define DEFINE_ZREG(reg) \
327 { \
328 #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
329 SVE_REG_KIND(reg), nullptr, nullptr, nullptr, \
330 }
331
332// Defines a P vector register with 2-byte default size
333#define DEFINE_PREG(reg) \
334 { \
335 #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
336 SVE_REG_KIND(reg), nullptr, nullptr, nullptr, \
337 }
338
339static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
340 // DEFINE_GPR64(name, GENERIC KIND)
341 DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
342 DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
343 DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
344 DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
345 DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
346 DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
347 DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
348 DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
349 DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
350 DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
351 DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
352 DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
353 DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
354 DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
355 DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
356 DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
357 DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
358 DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
359 DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
360 DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
361 DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
362 DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
363 DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
364 DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
365 DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
366 DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
367 DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
368 DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
369 DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
370 // DEFINE_GPR64(name, GENERIC KIND)
371 DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
372 DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
373 DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
374 DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
375
376 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
377 DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
378
379 // DEFINE_GPR32(name, parent name)
380 DEFINE_GPR32(w0, x0),
381 DEFINE_GPR32(w1, x1),
382 DEFINE_GPR32(w2, x2),
383 DEFINE_GPR32(w3, x3),
384 DEFINE_GPR32(w4, x4),
385 DEFINE_GPR32(w5, x5),
386 DEFINE_GPR32(w6, x6),
387 DEFINE_GPR32(w7, x7),
388 DEFINE_GPR32(w8, x8),
389 DEFINE_GPR32(w9, x9),
390 DEFINE_GPR32(w10, x10),
391 DEFINE_GPR32(w11, x11),
392 DEFINE_GPR32(w12, x12),
393 DEFINE_GPR32(w13, x13),
394 DEFINE_GPR32(w14, x14),
395 DEFINE_GPR32(w15, x15),
396 DEFINE_GPR32(w16, x16),
397 DEFINE_GPR32(w17, x17),
398 DEFINE_GPR32(w18, x18),
399 DEFINE_GPR32(w19, x19),
400 DEFINE_GPR32(w20, x20),
401 DEFINE_GPR32(w21, x21),
402 DEFINE_GPR32(w22, x22),
403 DEFINE_GPR32(w23, x23),
404 DEFINE_GPR32(w24, x24),
405 DEFINE_GPR32(w25, x25),
406 DEFINE_GPR32(w26, x26),
407 DEFINE_GPR32(w27, x27),
408 DEFINE_GPR32(w28, x28),
409
410 // DEFINE_VREG_SVE(v register, z register)
411 DEFINE_VREG_SVE(v0, z0),
412 DEFINE_VREG_SVE(v1, z1),
413 DEFINE_VREG_SVE(v2, z2),
414 DEFINE_VREG_SVE(v3, z3),
415 DEFINE_VREG_SVE(v4, z4),
416 DEFINE_VREG_SVE(v5, z5),
417 DEFINE_VREG_SVE(v6, z6),
418 DEFINE_VREG_SVE(v7, z7),
419 DEFINE_VREG_SVE(v8, z8),
420 DEFINE_VREG_SVE(v9, z9),
421 DEFINE_VREG_SVE(v10, z10),
422 DEFINE_VREG_SVE(v11, z11),
423 DEFINE_VREG_SVE(v12, z12),
424 DEFINE_VREG_SVE(v13, z13),
425 DEFINE_VREG_SVE(v14, z14),
426 DEFINE_VREG_SVE(v15, z15),
427 DEFINE_VREG_SVE(v16, z16),
428 DEFINE_VREG_SVE(v17, z17),
429 DEFINE_VREG_SVE(v18, z18),
430 DEFINE_VREG_SVE(v19, z19),
431 DEFINE_VREG_SVE(v20, z20),
432 DEFINE_VREG_SVE(v21, z21),
433 DEFINE_VREG_SVE(v22, z22),
434 DEFINE_VREG_SVE(v23, z23),
435 DEFINE_VREG_SVE(v24, z24),
436 DEFINE_VREG_SVE(v25, z25),
437 DEFINE_VREG_SVE(v26, z26),
438 DEFINE_VREG_SVE(v27, z27),
439 DEFINE_VREG_SVE(v28, z28),
440 DEFINE_VREG_SVE(v29, z29),
441 DEFINE_VREG_SVE(v30, z30),
442 DEFINE_VREG_SVE(v31, z31),
443
444 // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
445 DEFINE_FPU_PSEUDO_SVE(s0, 4, z0),
446 DEFINE_FPU_PSEUDO_SVE(s1, 4, z1),
447 DEFINE_FPU_PSEUDO_SVE(s2, 4, z2),
448 DEFINE_FPU_PSEUDO_SVE(s3, 4, z3),
449 DEFINE_FPU_PSEUDO_SVE(s4, 4, z4),
450 DEFINE_FPU_PSEUDO_SVE(s5, 4, z5),
451 DEFINE_FPU_PSEUDO_SVE(s6, 4, z6),
452 DEFINE_FPU_PSEUDO_SVE(s7, 4, z7),
453 DEFINE_FPU_PSEUDO_SVE(s8, 4, z8),
454 DEFINE_FPU_PSEUDO_SVE(s9, 4, z9),
455 DEFINE_FPU_PSEUDO_SVE(s10, 4, z10),
456 DEFINE_FPU_PSEUDO_SVE(s11, 4, z11),
457 DEFINE_FPU_PSEUDO_SVE(s12, 4, z12),
458 DEFINE_FPU_PSEUDO_SVE(s13, 4, z13),
459 DEFINE_FPU_PSEUDO_SVE(s14, 4, z14),
460 DEFINE_FPU_PSEUDO_SVE(s15, 4, z15),
461 DEFINE_FPU_PSEUDO_SVE(s16, 4, z16),
462 DEFINE_FPU_PSEUDO_SVE(s17, 4, z17),
463 DEFINE_FPU_PSEUDO_SVE(s18, 4, z18),
464 DEFINE_FPU_PSEUDO_SVE(s19, 4, z19),
465 DEFINE_FPU_PSEUDO_SVE(s20, 4, z20),
466 DEFINE_FPU_PSEUDO_SVE(s21, 4, z21),
467 DEFINE_FPU_PSEUDO_SVE(s22, 4, z22),
468 DEFINE_FPU_PSEUDO_SVE(s23, 4, z23),
469 DEFINE_FPU_PSEUDO_SVE(s24, 4, z24),
470 DEFINE_FPU_PSEUDO_SVE(s25, 4, z25),
471 DEFINE_FPU_PSEUDO_SVE(s26, 4, z26),
472 DEFINE_FPU_PSEUDO_SVE(s27, 4, z27),
473 DEFINE_FPU_PSEUDO_SVE(s28, 4, z28),
474 DEFINE_FPU_PSEUDO_SVE(s29, 4, z29),
475 DEFINE_FPU_PSEUDO_SVE(s30, 4, z30),
476 DEFINE_FPU_PSEUDO_SVE(s31, 4, z31),
477
478 DEFINE_FPU_PSEUDO_SVE(d0, 8, z0),
479 DEFINE_FPU_PSEUDO_SVE(d1, 8, z1),
480 DEFINE_FPU_PSEUDO_SVE(d2, 8, z2),
481 DEFINE_FPU_PSEUDO_SVE(d3, 8, z3),
482 DEFINE_FPU_PSEUDO_SVE(d4, 8, z4),
483 DEFINE_FPU_PSEUDO_SVE(d5, 8, z5),
484 DEFINE_FPU_PSEUDO_SVE(d6, 8, z6),
485 DEFINE_FPU_PSEUDO_SVE(d7, 8, z7),
486 DEFINE_FPU_PSEUDO_SVE(d8, 8, z8),
487 DEFINE_FPU_PSEUDO_SVE(d9, 8, z9),
488 DEFINE_FPU_PSEUDO_SVE(d10, 8, z10),
489 DEFINE_FPU_PSEUDO_SVE(d11, 8, z11),
490 DEFINE_FPU_PSEUDO_SVE(d12, 8, z12),
491 DEFINE_FPU_PSEUDO_SVE(d13, 8, z13),
492 DEFINE_FPU_PSEUDO_SVE(d14, 8, z14),
493 DEFINE_FPU_PSEUDO_SVE(d15, 8, z15),
494 DEFINE_FPU_PSEUDO_SVE(d16, 8, z16),
495 DEFINE_FPU_PSEUDO_SVE(d17, 8, z17),
496 DEFINE_FPU_PSEUDO_SVE(d18, 8, z18),
497 DEFINE_FPU_PSEUDO_SVE(d19, 8, z19),
498 DEFINE_FPU_PSEUDO_SVE(d20, 8, z20),
499 DEFINE_FPU_PSEUDO_SVE(d21, 8, z21),
500 DEFINE_FPU_PSEUDO_SVE(d22, 8, z22),
501 DEFINE_FPU_PSEUDO_SVE(d23, 8, z23),
502 DEFINE_FPU_PSEUDO_SVE(d24, 8, z24),
503 DEFINE_FPU_PSEUDO_SVE(d25, 8, z25),
504 DEFINE_FPU_PSEUDO_SVE(d26, 8, z26),
505 DEFINE_FPU_PSEUDO_SVE(d27, 8, z27),
506 DEFINE_FPU_PSEUDO_SVE(d28, 8, z28),
507 DEFINE_FPU_PSEUDO_SVE(d29, 8, z29),
508 DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
509 DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
510
511 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
512 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
513 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
514
515 DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
516 // DEFINE_ZREG(name)
517 DEFINE_ZREG(z0),
518 DEFINE_ZREG(z1),
519 DEFINE_ZREG(z2),
520 DEFINE_ZREG(z3),
521 DEFINE_ZREG(z4),
522 DEFINE_ZREG(z5),
523 DEFINE_ZREG(z6),
524 DEFINE_ZREG(z7),
525 DEFINE_ZREG(z8),
526 DEFINE_ZREG(z9),
527 DEFINE_ZREG(z10),
528 DEFINE_ZREG(z11),
529 DEFINE_ZREG(z12),
530 DEFINE_ZREG(z13),
531 DEFINE_ZREG(z14),
532 DEFINE_ZREG(z15),
533 DEFINE_ZREG(z16),
534 DEFINE_ZREG(z17),
535 DEFINE_ZREG(z18),
536 DEFINE_ZREG(z19),
537 DEFINE_ZREG(z20),
538 DEFINE_ZREG(z21),
539 DEFINE_ZREG(z22),
540 DEFINE_ZREG(z23),
541 DEFINE_ZREG(z24),
542 DEFINE_ZREG(z25),
543 DEFINE_ZREG(z26),
544 DEFINE_ZREG(z27),
545 DEFINE_ZREG(z28),
546 DEFINE_ZREG(z29),
547 DEFINE_ZREG(z30),
548 DEFINE_ZREG(z31),
549
550 // DEFINE_PREG(name)
551 DEFINE_PREG(p0),
552 DEFINE_PREG(p1),
553 DEFINE_PREG(p2),
554 DEFINE_PREG(p3),
555 DEFINE_PREG(p4),
556 DEFINE_PREG(p5),
557 DEFINE_PREG(p6),
558 DEFINE_PREG(p7),
559 DEFINE_PREG(p8),
560 DEFINE_PREG(p9),
561 DEFINE_PREG(p10),
562 DEFINE_PREG(p11),
563 DEFINE_PREG(p12),
564 DEFINE_PREG(p13),
565 DEFINE_PREG(p14),
566 DEFINE_PREG(p15),
567
568 // DEFINE FFR
569 DEFINE_PREG(ffr)
570 // clang-format on
571};
572
573#endif // DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT
574

source code of lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h