| 1 | //===-- RegisterInfos_ppc64.h -----------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | |
| 9 | #ifdef DECLARE_REGISTER_INFOS_PPC64_STRUCT |
| 10 | |
| 11 | #include <cstddef> |
| 12 | |
| 13 | // Computes the offset of the given GPR_PPC64 in the user data area. |
| 14 | #define GPR_PPC64_OFFSET(regname) (offsetof(GPR_PPC64, regname)) |
| 15 | #define FPR_PPC64_OFFSET(regname) (offsetof(FPR_PPC64, regname) \ |
| 16 | + sizeof(GPR_PPC64)) |
| 17 | #define VMX_PPC64_OFFSET(regname) (offsetof(VMX_PPC64, regname) \ |
| 18 | + sizeof(GPR_PPC64) + sizeof(FPR_PPC64)) |
| 19 | #define GPR_PPC64_SIZE(regname) (sizeof(((GPR_PPC64 *)NULL)->regname)) |
| 20 | |
| 21 | #include "Utility/PPC64_DWARF_Registers.h" |
| 22 | #include "lldb-ppc64-register-enums.h" |
| 23 | |
| 24 | // Note that the size and offset will be updated by platform-specific classes. |
| 25 | #define DEFINE_GPR_PPC64(reg, alt, lldb_kind) \ |
| 26 | { \ |
| 27 | #reg, alt, GPR_PPC64_SIZE(reg), GPR_PPC64_OFFSET(reg), lldb::eEncodingUint,\ |
| 28 | lldb::eFormatHex, \ |
| 29 | {ppc64_dwarf::dwarf_##reg##_ppc64, \ |
| 30 | ppc64_dwarf::dwarf_##reg##_ppc64, \ |
| 31 | lldb_kind, \ |
| 32 | LLDB_INVALID_REGNUM, \ |
| 33 | gpr_##reg##_ppc64 }, \ |
| 34 | NULL, NULL, NULL, \ |
| 35 | } |
| 36 | #define DEFINE_FPR_PPC64(reg, alt, lldb_kind) \ |
| 37 | { \ |
| 38 | #reg, alt, 8, FPR_PPC64_OFFSET(reg), lldb::eEncodingIEEE754, \ |
| 39 | lldb::eFormatFloat, \ |
| 40 | {ppc64_dwarf::dwarf_##reg##_ppc64, \ |
| 41 | ppc64_dwarf::dwarf_##reg##_ppc64, lldb_kind, LLDB_INVALID_REGNUM, \ |
| 42 | fpr_##reg##_ppc64 }, \ |
| 43 | NULL, NULL, NULL, \ |
| 44 | } |
| 45 | #define DEFINE_VMX_PPC64(reg, lldb_kind) \ |
| 46 | { \ |
| 47 | #reg, NULL, 16, VMX_PPC64_OFFSET(reg), lldb::eEncodingVector, \ |
| 48 | lldb::eFormatVectorOfUInt32, \ |
| 49 | {ppc64_dwarf::dwarf_##reg##_ppc64, \ |
| 50 | ppc64_dwarf::dwarf_##reg##_ppc64, lldb_kind, LLDB_INVALID_REGNUM, \ |
| 51 | vmx_##reg##_ppc64 }, \ |
| 52 | NULL, NULL, NULL, \ |
| 53 | } |
| 54 | |
| 55 | // General purpose registers. |
| 56 | // EH_Frame, Generic, Process Plugin |
| 57 | #define PPC64_REGS \ |
| 58 | DEFINE_GPR_PPC64(r0, NULL, LLDB_INVALID_REGNUM) \ |
| 59 | , DEFINE_GPR_PPC64(r1, NULL, LLDB_REGNUM_GENERIC_SP), \ |
| 60 | DEFINE_GPR_PPC64(r2, NULL, LLDB_INVALID_REGNUM), \ |
| 61 | DEFINE_GPR_PPC64(r3, NULL, LLDB_REGNUM_GENERIC_ARG1), \ |
| 62 | DEFINE_GPR_PPC64(r4, NULL, LLDB_REGNUM_GENERIC_ARG2), \ |
| 63 | DEFINE_GPR_PPC64(r5, NULL, LLDB_REGNUM_GENERIC_ARG3), \ |
| 64 | DEFINE_GPR_PPC64(r6, NULL, LLDB_REGNUM_GENERIC_ARG4), \ |
| 65 | DEFINE_GPR_PPC64(r7, NULL, LLDB_REGNUM_GENERIC_ARG5), \ |
| 66 | DEFINE_GPR_PPC64(r8, NULL, LLDB_REGNUM_GENERIC_ARG6), \ |
| 67 | DEFINE_GPR_PPC64(r9, NULL, LLDB_REGNUM_GENERIC_ARG7), \ |
| 68 | DEFINE_GPR_PPC64(r10, NULL, LLDB_REGNUM_GENERIC_ARG8), \ |
| 69 | DEFINE_GPR_PPC64(r11, NULL, LLDB_INVALID_REGNUM), \ |
| 70 | DEFINE_GPR_PPC64(r12, NULL, LLDB_INVALID_REGNUM), \ |
| 71 | DEFINE_GPR_PPC64(r13, NULL, LLDB_INVALID_REGNUM), \ |
| 72 | DEFINE_GPR_PPC64(r14, NULL, LLDB_INVALID_REGNUM), \ |
| 73 | DEFINE_GPR_PPC64(r15, NULL, LLDB_INVALID_REGNUM), \ |
| 74 | DEFINE_GPR_PPC64(r16, NULL, LLDB_INVALID_REGNUM), \ |
| 75 | DEFINE_GPR_PPC64(r17, NULL, LLDB_INVALID_REGNUM), \ |
| 76 | DEFINE_GPR_PPC64(r18, NULL, LLDB_INVALID_REGNUM), \ |
| 77 | DEFINE_GPR_PPC64(r19, NULL, LLDB_INVALID_REGNUM), \ |
| 78 | DEFINE_GPR_PPC64(r20, NULL, LLDB_INVALID_REGNUM), \ |
| 79 | DEFINE_GPR_PPC64(r21, NULL, LLDB_INVALID_REGNUM), \ |
| 80 | DEFINE_GPR_PPC64(r22, NULL, LLDB_INVALID_REGNUM), \ |
| 81 | DEFINE_GPR_PPC64(r23, NULL, LLDB_INVALID_REGNUM), \ |
| 82 | DEFINE_GPR_PPC64(r24, NULL, LLDB_INVALID_REGNUM), \ |
| 83 | DEFINE_GPR_PPC64(r25, NULL, LLDB_INVALID_REGNUM), \ |
| 84 | DEFINE_GPR_PPC64(r26, NULL, LLDB_INVALID_REGNUM), \ |
| 85 | DEFINE_GPR_PPC64(r27, NULL, LLDB_INVALID_REGNUM), \ |
| 86 | DEFINE_GPR_PPC64(r28, NULL, LLDB_INVALID_REGNUM), \ |
| 87 | DEFINE_GPR_PPC64(r29, NULL, LLDB_INVALID_REGNUM), \ |
| 88 | DEFINE_GPR_PPC64(r30, NULL, LLDB_INVALID_REGNUM), \ |
| 89 | DEFINE_GPR_PPC64(r31, NULL, LLDB_INVALID_REGNUM), \ |
| 90 | DEFINE_GPR_PPC64(cr, NULL, LLDB_REGNUM_GENERIC_FLAGS), \ |
| 91 | DEFINE_GPR_PPC64(msr, NULL, LLDB_INVALID_REGNUM), \ |
| 92 | DEFINE_GPR_PPC64(xer, NULL, LLDB_INVALID_REGNUM), \ |
| 93 | DEFINE_GPR_PPC64(lr, NULL, LLDB_REGNUM_GENERIC_RA), \ |
| 94 | DEFINE_GPR_PPC64(ctr, NULL, LLDB_INVALID_REGNUM), \ |
| 95 | DEFINE_GPR_PPC64(pc, NULL, LLDB_REGNUM_GENERIC_PC), \ |
| 96 | DEFINE_FPR_PPC64(f0, NULL, LLDB_INVALID_REGNUM), \ |
| 97 | DEFINE_FPR_PPC64(f1, NULL, LLDB_INVALID_REGNUM), \ |
| 98 | DEFINE_FPR_PPC64(f2, NULL, LLDB_INVALID_REGNUM), \ |
| 99 | DEFINE_FPR_PPC64(f3, NULL, LLDB_INVALID_REGNUM), \ |
| 100 | DEFINE_FPR_PPC64(f4, NULL, LLDB_INVALID_REGNUM), \ |
| 101 | DEFINE_FPR_PPC64(f5, NULL, LLDB_INVALID_REGNUM), \ |
| 102 | DEFINE_FPR_PPC64(f6, NULL, LLDB_INVALID_REGNUM), \ |
| 103 | DEFINE_FPR_PPC64(f7, NULL, LLDB_INVALID_REGNUM), \ |
| 104 | DEFINE_FPR_PPC64(f8, NULL, LLDB_INVALID_REGNUM), \ |
| 105 | DEFINE_FPR_PPC64(f9, NULL, LLDB_INVALID_REGNUM), \ |
| 106 | DEFINE_FPR_PPC64(f10, NULL, LLDB_INVALID_REGNUM), \ |
| 107 | DEFINE_FPR_PPC64(f11, NULL, LLDB_INVALID_REGNUM), \ |
| 108 | DEFINE_FPR_PPC64(f12, NULL, LLDB_INVALID_REGNUM), \ |
| 109 | DEFINE_FPR_PPC64(f13, NULL, LLDB_INVALID_REGNUM), \ |
| 110 | DEFINE_FPR_PPC64(f14, NULL, LLDB_INVALID_REGNUM), \ |
| 111 | DEFINE_FPR_PPC64(f15, NULL, LLDB_INVALID_REGNUM), \ |
| 112 | DEFINE_FPR_PPC64(f16, NULL, LLDB_INVALID_REGNUM), \ |
| 113 | DEFINE_FPR_PPC64(f17, NULL, LLDB_INVALID_REGNUM), \ |
| 114 | DEFINE_FPR_PPC64(f18, NULL, LLDB_INVALID_REGNUM), \ |
| 115 | DEFINE_FPR_PPC64(f19, NULL, LLDB_INVALID_REGNUM), \ |
| 116 | DEFINE_FPR_PPC64(f20, NULL, LLDB_INVALID_REGNUM), \ |
| 117 | DEFINE_FPR_PPC64(f21, NULL, LLDB_INVALID_REGNUM), \ |
| 118 | DEFINE_FPR_PPC64(f22, NULL, LLDB_INVALID_REGNUM), \ |
| 119 | DEFINE_FPR_PPC64(f23, NULL, LLDB_INVALID_REGNUM), \ |
| 120 | DEFINE_FPR_PPC64(f24, NULL, LLDB_INVALID_REGNUM), \ |
| 121 | DEFINE_FPR_PPC64(f25, NULL, LLDB_INVALID_REGNUM), \ |
| 122 | DEFINE_FPR_PPC64(f26, NULL, LLDB_INVALID_REGNUM), \ |
| 123 | DEFINE_FPR_PPC64(f27, NULL, LLDB_INVALID_REGNUM), \ |
| 124 | DEFINE_FPR_PPC64(f28, NULL, LLDB_INVALID_REGNUM), \ |
| 125 | DEFINE_FPR_PPC64(f29, NULL, LLDB_INVALID_REGNUM), \ |
| 126 | DEFINE_FPR_PPC64(f30, NULL, LLDB_INVALID_REGNUM), \ |
| 127 | DEFINE_FPR_PPC64(f31, NULL, LLDB_INVALID_REGNUM), \ |
| 128 | {"fpscr", \ |
| 129 | NULL, \ |
| 130 | 8, \ |
| 131 | FPR_PPC64_OFFSET(fpscr), \ |
| 132 | lldb::eEncodingUint, \ |
| 133 | lldb::eFormatHex, \ |
| 134 | {ppc64_dwarf::dwarf_fpscr_ppc64, \ |
| 135 | ppc64_dwarf::dwarf_fpscr_ppc64, LLDB_INVALID_REGNUM, \ |
| 136 | LLDB_INVALID_REGNUM, fpr_fpscr_ppc64}, \ |
| 137 | NULL, \ |
| 138 | NULL, \ |
| 139 | NULL, \ |
| 140 | }, \ |
| 141 | DEFINE_VMX_PPC64(vr0, LLDB_INVALID_REGNUM), \ |
| 142 | DEFINE_VMX_PPC64(vr1, LLDB_INVALID_REGNUM), \ |
| 143 | DEFINE_VMX_PPC64(vr2, LLDB_INVALID_REGNUM), \ |
| 144 | DEFINE_VMX_PPC64(vr3, LLDB_INVALID_REGNUM), \ |
| 145 | DEFINE_VMX_PPC64(vr4, LLDB_INVALID_REGNUM), \ |
| 146 | DEFINE_VMX_PPC64(vr5, LLDB_INVALID_REGNUM), \ |
| 147 | DEFINE_VMX_PPC64(vr6, LLDB_INVALID_REGNUM), \ |
| 148 | DEFINE_VMX_PPC64(vr7, LLDB_INVALID_REGNUM), \ |
| 149 | DEFINE_VMX_PPC64(vr8, LLDB_INVALID_REGNUM), \ |
| 150 | DEFINE_VMX_PPC64(vr9, LLDB_INVALID_REGNUM), \ |
| 151 | DEFINE_VMX_PPC64(vr10, LLDB_INVALID_REGNUM), \ |
| 152 | DEFINE_VMX_PPC64(vr11, LLDB_INVALID_REGNUM), \ |
| 153 | DEFINE_VMX_PPC64(vr12, LLDB_INVALID_REGNUM), \ |
| 154 | DEFINE_VMX_PPC64(vr13, LLDB_INVALID_REGNUM), \ |
| 155 | DEFINE_VMX_PPC64(vr14, LLDB_INVALID_REGNUM), \ |
| 156 | DEFINE_VMX_PPC64(vr15, LLDB_INVALID_REGNUM), \ |
| 157 | DEFINE_VMX_PPC64(vr16, LLDB_INVALID_REGNUM), \ |
| 158 | DEFINE_VMX_PPC64(vr17, LLDB_INVALID_REGNUM), \ |
| 159 | DEFINE_VMX_PPC64(vr18, LLDB_INVALID_REGNUM), \ |
| 160 | DEFINE_VMX_PPC64(vr19, LLDB_INVALID_REGNUM), \ |
| 161 | DEFINE_VMX_PPC64(vr20, LLDB_INVALID_REGNUM), \ |
| 162 | DEFINE_VMX_PPC64(vr21, LLDB_INVALID_REGNUM), \ |
| 163 | DEFINE_VMX_PPC64(vr22, LLDB_INVALID_REGNUM), \ |
| 164 | DEFINE_VMX_PPC64(vr23, LLDB_INVALID_REGNUM), \ |
| 165 | DEFINE_VMX_PPC64(vr24, LLDB_INVALID_REGNUM), \ |
| 166 | DEFINE_VMX_PPC64(vr25, LLDB_INVALID_REGNUM), \ |
| 167 | DEFINE_VMX_PPC64(vr26, LLDB_INVALID_REGNUM), \ |
| 168 | DEFINE_VMX_PPC64(vr27, LLDB_INVALID_REGNUM), \ |
| 169 | DEFINE_VMX_PPC64(vr28, LLDB_INVALID_REGNUM), \ |
| 170 | DEFINE_VMX_PPC64(vr29, LLDB_INVALID_REGNUM), \ |
| 171 | DEFINE_VMX_PPC64(vr30, LLDB_INVALID_REGNUM), \ |
| 172 | DEFINE_VMX_PPC64(vr31, LLDB_INVALID_REGNUM), \ |
| 173 | {"vscr", \ |
| 174 | NULL, \ |
| 175 | 4, \ |
| 176 | VMX_PPC64_OFFSET(vscr), \ |
| 177 | lldb::eEncodingUint, \ |
| 178 | lldb::eFormatHex, \ |
| 179 | {ppc64_dwarf::dwarf_vscr_ppc64, ppc64_dwarf::dwarf_vscr_ppc64, \ |
| 180 | LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, vmx_vscr_ppc64}, \ |
| 181 | NULL, \ |
| 182 | NULL, \ |
| 183 | NULL, \ |
| 184 | }, \ |
| 185 | {"vrsave", \ |
| 186 | NULL, \ |
| 187 | 4, \ |
| 188 | VMX_PPC64_OFFSET(vrsave), \ |
| 189 | lldb::eEncodingUint, \ |
| 190 | lldb::eFormatHex, \ |
| 191 | {ppc64_dwarf::dwarf_vrsave_ppc64, \ |
| 192 | ppc64_dwarf::dwarf_vrsave_ppc64, LLDB_INVALID_REGNUM, \ |
| 193 | LLDB_INVALID_REGNUM, vmx_vrsave_ppc64}, \ |
| 194 | NULL, \ |
| 195 | NULL, \ |
| 196 | NULL, \ |
| 197 | }, /* */ |
| 198 | |
| 199 | typedef struct _GPR_PPC64 { |
| 200 | uint64_t r0; |
| 201 | uint64_t r1; |
| 202 | uint64_t r2; |
| 203 | uint64_t r3; |
| 204 | uint64_t r4; |
| 205 | uint64_t r5; |
| 206 | uint64_t r6; |
| 207 | uint64_t r7; |
| 208 | uint64_t r8; |
| 209 | uint64_t r9; |
| 210 | uint64_t r10; |
| 211 | uint64_t r11; |
| 212 | uint64_t r12; |
| 213 | uint64_t r13; |
| 214 | uint64_t r14; |
| 215 | uint64_t r15; |
| 216 | uint64_t r16; |
| 217 | uint64_t r17; |
| 218 | uint64_t r18; |
| 219 | uint64_t r19; |
| 220 | uint64_t r20; |
| 221 | uint64_t r21; |
| 222 | uint64_t r22; |
| 223 | uint64_t r23; |
| 224 | uint64_t r24; |
| 225 | uint64_t r25; |
| 226 | uint64_t r26; |
| 227 | uint64_t r27; |
| 228 | uint64_t r28; |
| 229 | uint64_t r29; |
| 230 | uint64_t r30; |
| 231 | uint64_t r31; |
| 232 | uint64_t cr; |
| 233 | uint64_t msr; |
| 234 | uint64_t xer; |
| 235 | uint64_t lr; |
| 236 | uint64_t ctr; |
| 237 | uint64_t pc; |
| 238 | uint64_t pad[3]; |
| 239 | } GPR_PPC64; |
| 240 | |
| 241 | typedef struct _FPR_PPC64 { |
| 242 | uint64_t f0; |
| 243 | uint64_t f1; |
| 244 | uint64_t f2; |
| 245 | uint64_t f3; |
| 246 | uint64_t f4; |
| 247 | uint64_t f5; |
| 248 | uint64_t f6; |
| 249 | uint64_t f7; |
| 250 | uint64_t f8; |
| 251 | uint64_t f9; |
| 252 | uint64_t f10; |
| 253 | uint64_t f11; |
| 254 | uint64_t f12; |
| 255 | uint64_t f13; |
| 256 | uint64_t f14; |
| 257 | uint64_t f15; |
| 258 | uint64_t f16; |
| 259 | uint64_t f17; |
| 260 | uint64_t f18; |
| 261 | uint64_t f19; |
| 262 | uint64_t f20; |
| 263 | uint64_t f21; |
| 264 | uint64_t f22; |
| 265 | uint64_t f23; |
| 266 | uint64_t f24; |
| 267 | uint64_t f25; |
| 268 | uint64_t f26; |
| 269 | uint64_t f27; |
| 270 | uint64_t f28; |
| 271 | uint64_t f29; |
| 272 | uint64_t f30; |
| 273 | uint64_t f31; |
| 274 | uint64_t fpscr; |
| 275 | } FPR_PPC64; |
| 276 | |
| 277 | typedef struct _VMX_PPC64 { |
| 278 | uint32_t vr0[4]; |
| 279 | uint32_t vr1[4]; |
| 280 | uint32_t vr2[4]; |
| 281 | uint32_t vr3[4]; |
| 282 | uint32_t vr4[4]; |
| 283 | uint32_t vr5[4]; |
| 284 | uint32_t vr6[4]; |
| 285 | uint32_t vr7[4]; |
| 286 | uint32_t vr8[4]; |
| 287 | uint32_t vr9[4]; |
| 288 | uint32_t vr10[4]; |
| 289 | uint32_t vr11[4]; |
| 290 | uint32_t vr12[4]; |
| 291 | uint32_t vr13[4]; |
| 292 | uint32_t vr14[4]; |
| 293 | uint32_t vr15[4]; |
| 294 | uint32_t vr16[4]; |
| 295 | uint32_t vr17[4]; |
| 296 | uint32_t vr18[4]; |
| 297 | uint32_t vr19[4]; |
| 298 | uint32_t vr20[4]; |
| 299 | uint32_t vr21[4]; |
| 300 | uint32_t vr22[4]; |
| 301 | uint32_t vr23[4]; |
| 302 | uint32_t vr24[4]; |
| 303 | uint32_t vr25[4]; |
| 304 | uint32_t vr26[4]; |
| 305 | uint32_t vr27[4]; |
| 306 | uint32_t vr28[4]; |
| 307 | uint32_t vr29[4]; |
| 308 | uint32_t vr30[4]; |
| 309 | uint32_t vr31[4]; |
| 310 | uint32_t pad[2]; |
| 311 | uint32_t vscr[2]; |
| 312 | uint32_t vrsave; |
| 313 | } VMX_PPC64; |
| 314 | |
| 315 | |
| 316 | static lldb_private::RegisterInfo g_register_infos_ppc64[] = { |
| 317 | PPC64_REGS |
| 318 | }; |
| 319 | |
| 320 | static_assert((sizeof(g_register_infos_ppc64) / |
| 321 | sizeof(g_register_infos_ppc64[0])) == |
| 322 | k_num_registers_ppc64, |
| 323 | "g_register_infos_powerpc64 has wrong number of register infos" ); |
| 324 | |
| 325 | #undef DEFINE_FPR_PPC64 |
| 326 | #undef DEFINE_GPR_PPC64 |
| 327 | #undef DEFINE_VMX_PPC64 |
| 328 | |
| 329 | #endif // DECLARE_REGISTER_INFOS_PPC64_STRUCT |
| 330 | |