1//===-- RISCV_DWARF_Registers.h ---------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H
10#define LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H
11
12#include "lldb/lldb-private.h"
13
14namespace riscv_dwarf {
15
16enum {
17 dwarf_gpr_x0 = 0,
18 dwarf_gpr_x1,
19 dwarf_gpr_x2,
20 dwarf_gpr_x3,
21 dwarf_gpr_x4,
22 dwarf_gpr_x5,
23 dwarf_gpr_x6,
24 dwarf_gpr_x7,
25 dwarf_gpr_x8,
26 dwarf_gpr_x9,
27 dwarf_gpr_x10,
28 dwarf_gpr_x11,
29 dwarf_gpr_x12,
30 dwarf_gpr_x13,
31 dwarf_gpr_x14,
32 dwarf_gpr_x15,
33 dwarf_gpr_x16,
34 dwarf_gpr_x17,
35 dwarf_gpr_x18,
36 dwarf_gpr_x19,
37 dwarf_gpr_x20,
38 dwarf_gpr_x21,
39 dwarf_gpr_x22,
40 dwarf_gpr_x23,
41 dwarf_gpr_x24,
42 dwarf_gpr_x25,
43 dwarf_gpr_x26,
44 dwarf_gpr_x27,
45 dwarf_gpr_x28,
46 dwarf_gpr_x29,
47 dwarf_gpr_x30,
48 dwarf_gpr_x31 = 31,
49
50 dwarf_fpr_f0 = 32,
51 dwarf_fpr_f1,
52 dwarf_fpr_f2,
53 dwarf_fpr_f3,
54 dwarf_fpr_f4,
55 dwarf_fpr_f5,
56 dwarf_fpr_f6,
57 dwarf_fpr_f7,
58 dwarf_fpr_f8,
59 dwarf_fpr_f9,
60 dwarf_fpr_f10,
61 dwarf_fpr_f11,
62 dwarf_fpr_f12,
63 dwarf_fpr_f13,
64 dwarf_fpr_f14,
65 dwarf_fpr_f15,
66 dwarf_fpr_f16,
67 dwarf_fpr_f17,
68 dwarf_fpr_f18,
69 dwarf_fpr_f19,
70 dwarf_fpr_f20,
71 dwarf_fpr_f21,
72 dwarf_fpr_f22,
73 dwarf_fpr_f23,
74 dwarf_fpr_f24,
75 dwarf_fpr_f25,
76 dwarf_fpr_f26,
77 dwarf_fpr_f27,
78 dwarf_fpr_f28,
79 dwarf_fpr_f29,
80 dwarf_fpr_f30,
81 dwarf_fpr_f31 = 63,
82
83 // alternate frame return column
84 dwarf_alt_fr_col = 64,
85
86 dwarf_vpr_v0 = 96,
87 dwarf_vpr_v1,
88 dwarf_vpr_v2,
89 dwarf_vpr_v3,
90 dwarf_vpr_v4,
91 dwarf_vpr_v5,
92 dwarf_vpr_v6,
93 dwarf_vpr_v7,
94 dwarf_vpr_v8,
95 dwarf_vpr_v9,
96 dwarf_vpr_v10,
97 dwarf_vpr_v11,
98 dwarf_vpr_v12,
99 dwarf_vpr_v13,
100 dwarf_vpr_v14,
101 dwarf_vpr_v15,
102 dwarf_vpr_v16,
103 dwarf_vpr_v17,
104 dwarf_vpr_v18,
105 dwarf_vpr_v19,
106 dwarf_vpr_v20,
107 dwarf_vpr_v21,
108 dwarf_vpr_v22,
109 dwarf_vpr_v23,
110 dwarf_vpr_v24,
111 dwarf_vpr_v25,
112 dwarf_vpr_v26,
113 dwarf_vpr_v27,
114 dwarf_vpr_v28,
115 dwarf_vpr_v29,
116 dwarf_vpr_v30,
117 dwarf_vpr_v31 = 127,
118 dwarf_first_csr = 4096,
119 dwarf_fpr_fcsr = dwarf_first_csr + 0x003,
120 // The vector extension adds seven unprivileged CSRs
121 // (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb)
122 // to a base scalar RISC-V ISA.
123 dwarf_vpr_vstart = dwarf_first_csr + 0x008,
124 dwarf_vpr_vxsat = dwarf_first_csr + 0x009,
125 dwarf_vpr_vxrm = dwarf_first_csr + 0x00A,
126 dwarf_vpr_vcsr = dwarf_first_csr + 0x00F,
127 dwarf_vpr_vl = dwarf_first_csr + 0xC20,
128 dwarf_vpr_vtype = dwarf_first_csr + 0xC21,
129 dwarf_vpr_vlenb = dwarf_first_csr + 0xC22,
130 dwarf_last_csr = 8191,
131
132 // register ABI name
133 dwarf_gpr_zero = dwarf_gpr_x0,
134 dwarf_gpr_ra = dwarf_gpr_x1,
135 dwarf_gpr_sp = dwarf_gpr_x2,
136 dwarf_gpr_gp = dwarf_gpr_x3,
137 dwarf_gpr_tp = dwarf_gpr_x4,
138 dwarf_gpr_t0 = dwarf_gpr_x5,
139 dwarf_gpr_t1 = dwarf_gpr_x6,
140 dwarf_gpr_t2 = dwarf_gpr_x7,
141 dwarf_gpr_fp = dwarf_gpr_x8,
142 dwarf_gpr_s1 = dwarf_gpr_x9,
143 dwarf_gpr_a0 = dwarf_gpr_x10,
144 dwarf_gpr_a1 = dwarf_gpr_x11,
145 dwarf_gpr_a2 = dwarf_gpr_x12,
146 dwarf_gpr_a3 = dwarf_gpr_x13,
147 dwarf_gpr_a4 = dwarf_gpr_x14,
148 dwarf_gpr_a5 = dwarf_gpr_x15,
149 dwarf_gpr_a6 = dwarf_gpr_x16,
150 dwarf_gpr_a7 = dwarf_gpr_x17,
151 dwarf_gpr_s2 = dwarf_gpr_x18,
152 dwarf_gpr_s3 = dwarf_gpr_x19,
153 dwarf_gpr_s4 = dwarf_gpr_x20,
154 dwarf_gpr_s5 = dwarf_gpr_x21,
155 dwarf_gpr_s6 = dwarf_gpr_x22,
156 dwarf_gpr_s7 = dwarf_gpr_x23,
157 dwarf_gpr_s8 = dwarf_gpr_x24,
158 dwarf_gpr_s9 = dwarf_gpr_x25,
159 dwarf_gpr_s10 = dwarf_gpr_x26,
160 dwarf_gpr_s11 = dwarf_gpr_x27,
161 dwarf_gpr_t3 = dwarf_gpr_x28,
162 dwarf_gpr_t4 = dwarf_gpr_x29,
163 dwarf_gpr_t5 = dwarf_gpr_x30,
164 dwarf_gpr_t6 = dwarf_gpr_x31,
165
166 dwarf_fpr_ft0 = dwarf_fpr_f0,
167 dwarf_fpr_ft1 = dwarf_fpr_f1,
168 dwarf_fpr_ft2 = dwarf_fpr_f2,
169 dwarf_fpr_ft3 = dwarf_fpr_f3,
170 dwarf_fpr_ft4 = dwarf_fpr_f4,
171 dwarf_fpr_ft5 = dwarf_fpr_f5,
172 dwarf_fpr_ft6 = dwarf_fpr_f6,
173 dwarf_fpr_ft7 = dwarf_fpr_f7,
174 dwarf_fpr_fs0 = dwarf_fpr_f8,
175 dwarf_fpr_fs1 = dwarf_fpr_f9,
176 dwarf_fpr_fa0 = dwarf_fpr_f10,
177 dwarf_fpr_fa1 = dwarf_fpr_f11,
178 dwarf_fpr_fa2 = dwarf_fpr_f12,
179 dwarf_fpr_fa3 = dwarf_fpr_f13,
180 dwarf_fpr_fa4 = dwarf_fpr_f14,
181 dwarf_fpr_fa5 = dwarf_fpr_f15,
182 dwarf_fpr_fa6 = dwarf_fpr_f16,
183 dwarf_fpr_fa7 = dwarf_fpr_f17,
184 dwarf_fpr_fs2 = dwarf_fpr_f18,
185 dwarf_fpr_fs3 = dwarf_fpr_f19,
186 dwarf_fpr_fs4 = dwarf_fpr_f20,
187 dwarf_fpr_fs5 = dwarf_fpr_f21,
188 dwarf_fpr_fs6 = dwarf_fpr_f22,
189 dwarf_fpr_fs7 = dwarf_fpr_f23,
190 dwarf_fpr_fs8 = dwarf_fpr_f24,
191 dwarf_fpr_fs9 = dwarf_fpr_f25,
192 dwarf_fpr_fs10 = dwarf_fpr_f26,
193 dwarf_fpr_fs11 = dwarf_fpr_f27,
194 dwarf_fpr_ft8 = dwarf_fpr_f28,
195 dwarf_fpr_ft9 = dwarf_fpr_f29,
196 dwarf_fpr_ft10 = dwarf_fpr_f30,
197 dwarf_fpr_ft11 = dwarf_fpr_f31,
198
199 // mock pc regnum
200 dwarf_gpr_pc = 11451,
201};
202
203} // namespace riscv_dwarf
204
205#endif // LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H
206

source code of lldb/source/Utility/RISCV_DWARF_Registers.h