1void __attribute__((naked)) incomplete_cas(int *a, int *b) {
2 // Stop at the first instruction (an lr without a corresponding sc), then make
3 // a step instruction and ensure that execution stops at the next instruction
4 // (and).
5 asm volatile("1:\n\t"
6 "lr.w a2, (a0)\n\t"
7 "and a5, a2, a4\n\t"
8 "beq a5, a1, 2f\n\t"
9 "xor a5, a2, a0\n\t"
10 "and a5, a5, a4\n\t"
11 "xor a5, a2, a5\n\t"
12 "bnez a5, 1b\n\t"
13 "2:\n\t"
14 "ret\n\t");
15}
16
17int main() {
18 int a = 4;
19 int b = 2;
20 incomplete_cas(a: &a, b: &b);
21}
22

source code of lldb/test/API/riscv/step/incomplete_sequence_without_sc.c