1void __attribute__((naked)) cas(int *a, int *b) {
2 // This atomic sequence implements a copy-and-swap function. This test should
3 // at the first instruction, and after step instruction, we should stop at the
4 // end of the sequence (on the ret instruction).
5 asm volatile("1:\n\t"
6 "lr.w a2, (a0)\n\t"
7 "and a5, a2, a4\n\t"
8 "beq a5, a1, 2f\n\t"
9 "xor a5, a2, a0\n\t"
10 "and a5, a5, a4\n\t"
11 "xor a5, a2, a5\n\t"
12 "sc.w a5, a1, (a3)\n\t"
13 "beqz a5, 1b\n\t"
14 "2:\n\t"
15 "ret\n\t");
16}
17
18int main() {
19 int a = 4;
20 int b = 2;
21 cas(a: &a, b: &b);
22}
23

source code of lldb/test/API/riscv/step/main.c