| 1 | //===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR |
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| 10 | // register bank selection. Use/def analysis as in the default RegBankSelect can |
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| 11 | // be useful in narrower circumstances (e.g. choosing AGPR vs. VGPR for gfx908). |
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| 12 | // |
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| 13 | //===----------------------------------------------------------------------===// |
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| 14 | |
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| 15 | #include "AMDGPURegBankSelect.h" |
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| 16 | #include "AMDGPU.h" |
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| 17 | #include "GCNSubtarget.h" |
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| 18 | #include "llvm/CodeGen/MachineUniformityAnalysis.h" |
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| 19 | #include "llvm/InitializePasses.h" |
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| 20 | |
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| 21 | #define DEBUG_TYPE "regbankselect" |
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| 22 | |
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| 23 | using namespace llvm; |
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| 24 | |
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| 25 | AMDGPURegBankSelect::AMDGPURegBankSelect(Mode RunningMode) |
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| 26 | : RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {} |
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| 27 | |
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| 28 | char AMDGPURegBankSelect::ID = 0; |
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| 29 | |
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| 30 | StringRef AMDGPURegBankSelect::getPassName() const { |
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| 31 | return "AMDGPURegBankSelect" ; |
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| 32 | } |
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| 33 | |
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| 34 | void AMDGPURegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const { |
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| 35 | AU.addRequired<MachineCycleInfoWrapperPass>(); |
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| 36 | AU.addRequired<MachineDominatorTree>(); |
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| 37 | // TODO: Preserve DomTree |
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| 38 | RegBankSelect::getAnalysisUsage(AU); |
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| 39 | } |
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| 40 | |
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| 41 | INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE, |
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| 42 | "AMDGPU Register Bank Select" , false, false) |
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| 43 | INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) |
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| 44 | INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) |
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| 45 | INITIALIZE_PASS_END(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE, |
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| 46 | "AMDGPU Register Bank Select" , false, false) |
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| 47 | |
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| 48 | bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { |
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| 49 | // If the ISel pipeline failed, do not bother running that pass. |
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| 50 | if (MF.getProperties().hasProperty( |
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| 51 | P: MachineFunctionProperties::Property::FailedISel)) |
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| 52 | return false; |
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| 53 | |
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| 54 | LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n'); |
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| 55 | const Function &F = MF.getFunction(); |
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| 56 | Mode SaveOptMode = OptMode; |
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| 57 | if (F.hasOptNone()) |
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| 58 | OptMode = Mode::Fast; |
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| 59 | init(MF); |
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| 60 | |
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| 61 | assert(checkFunctionIsLegal(MF)); |
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| 62 | |
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| 63 | const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); |
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| 64 | MachineCycleInfo &CycleInfo = |
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| 65 | getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo(); |
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| 66 | MachineDominatorTree &DomTree = getAnalysis<MachineDominatorTree>(); |
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| 67 | |
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| 68 | MachineUniformityInfo Uniformity = |
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| 69 | computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase(), |
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| 70 | !ST.isSingleLaneExecution(F)); |
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| 71 | (void)Uniformity; // TODO: Use this |
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| 72 | |
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| 73 | assignRegisterBanks(MF); |
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| 74 | |
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| 75 | OptMode = SaveOptMode; |
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| 76 | return false; |
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| 77 | } |
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| 78 | |
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