1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
19 RegTupleAlignUnitsWidth = 2,
20 HasVGPRBit = RegTupleAlignUnitsWidth,
21 HasAGPRBit,
22 HasSGPRbit,
23
24 HasVGPR = 1 << HasVGPRBit,
25 HasAGPR = 1 << HasAGPRBit,
26 HasSGPR = 1 << HasSGPRbit,
27
28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
30}; // enum SIRCFlagsr
31
32namespace SIEncodingFamily {
33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
34// and the columns of the getMCOpcodeGen table.
35enum {
36 SI = 0,
37 VI = 1,
38 SDWA = 2,
39 SDWA9 = 3,
40 GFX80 = 4,
41 GFX9 = 5,
42 GFX10 = 6,
43 SDWA10 = 7,
44 GFX90A = 8,
45 GFX940 = 9,
46 GFX11 = 10,
47 GFX12 = 11,
48};
49}
50
51namespace SIInstrFlags {
52// This needs to be kept in sync with the field bits in InstSI.
53enum : uint64_t {
54 // Low bits - basic encoding information.
55 SALU = 1 << 0,
56 VALU = 1 << 1,
57
58 // SALU instruction formats.
59 SOP1 = 1 << 2,
60 SOP2 = 1 << 3,
61 SOPC = 1 << 4,
62 SOPK = 1 << 5,
63 SOPP = 1 << 6,
64
65 // VALU instruction formats.
66 VOP1 = 1 << 7,
67 VOP2 = 1 << 8,
68 VOPC = 1 << 9,
69
70 // TODO: Should this be spilt into VOP3 a and b?
71 VOP3 = 1 << 10,
72 VOP3P = 1 << 12,
73
74 VINTRP = 1 << 13,
75 SDWA = 1 << 14,
76 DPP = 1 << 15,
77 TRANS = 1 << 16,
78
79 // Memory instruction formats.
80 MUBUF = 1 << 17,
81 MTBUF = 1 << 18,
82 SMRD = 1 << 19,
83 MIMG = 1 << 20,
84 VIMAGE = 1 << 21,
85 VSAMPLE = 1 << 22,
86 EXP = 1 << 23,
87 FLAT = 1 << 24,
88 DS = 1 << 25,
89
90 // Combined SGPR/VGPR Spill bit
91 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
92 Spill = 1 << 26,
93
94 // LDSDIR instruction format.
95 LDSDIR = 1 << 28,
96
97 // VINTERP instruction format.
98 VINTERP = 1 << 29,
99
100 // High bits - other information.
101 VM_CNT = UINT64_C(1) << 32,
102 EXP_CNT = UINT64_C(1) << 33,
103 LGKM_CNT = UINT64_C(1) << 34,
104
105 WQM = UINT64_C(1) << 35,
106 DisableWQM = UINT64_C(1) << 36,
107 Gather4 = UINT64_C(1) << 37,
108
109 // Reserved, must be 0.
110 Reserved0 = UINT64_C(1) << 38,
111
112 SCALAR_STORE = UINT64_C(1) << 39,
113 FIXED_SIZE = UINT64_C(1) << 40,
114
115 // Reserved, must be 0.
116 Reserved1 = UINT64_C(1) << 41,
117
118 VOP3_OPSEL = UINT64_C(1) << 42,
119 maybeAtomic = UINT64_C(1) << 43,
120 renamedInGFX9 = UINT64_C(1) << 44,
121
122 // Is a clamp on FP type.
123 FPClamp = UINT64_C(1) << 45,
124
125 // Is an integer clamp
126 IntClamp = UINT64_C(1) << 46,
127
128 // Clamps lo component of register.
129 ClampLo = UINT64_C(1) << 47,
130
131 // Clamps hi component of register.
132 // ClampLo and ClampHi set for packed clamp.
133 ClampHi = UINT64_C(1) << 48,
134
135 // Is a packed VOP3P instruction.
136 IsPacked = UINT64_C(1) << 49,
137
138 // Is a D16 buffer instruction.
139 D16Buf = UINT64_C(1) << 50,
140
141 // FLAT instruction accesses FLAT_GLBL segment.
142 FlatGlobal = UINT64_C(1) << 51,
143
144 // Uses floating point double precision rounding mode
145 FPDPRounding = UINT64_C(1) << 52,
146
147 // Instruction is FP atomic.
148 FPAtomic = UINT64_C(1) << 53,
149
150 // Is a MFMA instruction.
151 IsMAI = UINT64_C(1) << 54,
152
153 // Is a DOT instruction.
154 IsDOT = UINT64_C(1) << 55,
155
156 // FLAT instruction accesses FLAT_SCRATCH segment.
157 FlatScratch = UINT64_C(1) << 56,
158
159 // Atomic without return.
160 IsAtomicNoRet = UINT64_C(1) << 57,
161
162 // Atomic with return.
163 IsAtomicRet = UINT64_C(1) << 58,
164
165 // Is a WMMA instruction.
166 IsWMMA = UINT64_C(1) << 59,
167
168 // Whether tied sources will be read.
169 TiedSourceNotRead = UINT64_C(1) << 60,
170
171 // Is never uniform.
172 IsNeverUniform = UINT64_C(1) << 61,
173
174 // ds_gws_* instructions.
175 GWS = UINT64_C(1) << 62,
176
177 // Is a SWMMAC instruction.
178 IsSWMMAC = UINT64_C(1) << 63,
179};
180
181// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
182// The result is true if any of these tests are true.
183enum ClassFlags : unsigned {
184 S_NAN = 1 << 0, // Signaling NaN
185 Q_NAN = 1 << 1, // Quiet NaN
186 N_INFINITY = 1 << 2, // Negative infinity
187 N_NORMAL = 1 << 3, // Negative normal
188 N_SUBNORMAL = 1 << 4, // Negative subnormal
189 N_ZERO = 1 << 5, // Negative zero
190 P_ZERO = 1 << 6, // Positive zero
191 P_SUBNORMAL = 1 << 7, // Positive subnormal
192 P_NORMAL = 1 << 8, // Positive normal
193 P_INFINITY = 1 << 9 // Positive infinity
194};
195}
196
197namespace AMDGPU {
198enum OperandType : unsigned {
199 /// Operands with register or 32-bit immediate
200 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
201 OPERAND_REG_IMM_INT64,
202 OPERAND_REG_IMM_INT16,
203 OPERAND_REG_IMM_FP32,
204 OPERAND_REG_IMM_FP64,
205 OPERAND_REG_IMM_BF16,
206 OPERAND_REG_IMM_FP16,
207 OPERAND_REG_IMM_V2BF16,
208 OPERAND_REG_IMM_V2FP16,
209 OPERAND_REG_IMM_V2INT16,
210 OPERAND_REG_IMM_V2INT32,
211 OPERAND_REG_IMM_V2FP32,
212
213 /// Operands with register or inline constant
214 OPERAND_REG_INLINE_C_INT16,
215 OPERAND_REG_INLINE_C_INT32,
216 OPERAND_REG_INLINE_C_INT64,
217 OPERAND_REG_INLINE_C_BF16,
218 OPERAND_REG_INLINE_C_FP16,
219 OPERAND_REG_INLINE_C_FP32,
220 OPERAND_REG_INLINE_C_FP64,
221 OPERAND_REG_INLINE_C_V2INT16,
222 OPERAND_REG_INLINE_C_V2BF16,
223 OPERAND_REG_INLINE_C_V2FP16,
224
225 // Operand for split barrier inline constant
226 OPERAND_INLINE_SPLIT_BARRIER_INT32,
227
228 /// Operand with 32-bit immediate that uses the constant bus.
229 OPERAND_KIMM32,
230 OPERAND_KIMM16,
231
232 /// Operands with an AccVGPR register or inline constant
233 OPERAND_REG_INLINE_AC_INT32,
234 OPERAND_REG_INLINE_AC_FP32,
235 OPERAND_REG_INLINE_AC_FP64,
236
237 // Operand for source modifiers for VOP instructions
238 OPERAND_INPUT_MODS,
239
240 // Operand for SDWA instructions
241 OPERAND_SDWA_VOPC_DST,
242
243 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
244 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
245
246 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
247 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
248
249 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
250 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_FP64,
251
252 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
253 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
254
255 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
256 OPERAND_KIMM_LAST = OPERAND_KIMM16
257
258};
259}
260
261// Input operand modifiers bit-masks
262// NEG and SEXT share same bit-mask because they can't be set simultaneously.
263namespace SISrcMods {
264 enum : unsigned {
265 NONE = 0,
266 NEG = 1 << 0, // Floating-point negate modifier
267 ABS = 1 << 1, // Floating-point absolute modifier
268 SEXT = 1 << 0, // Integer sign-extend modifier
269 NEG_HI = ABS, // Floating-point negate high packed component modifier.
270 OP_SEL_0 = 1 << 2,
271 OP_SEL_1 = 1 << 3,
272 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
273 };
274}
275
276namespace SIOutMods {
277 enum : unsigned {
278 NONE = 0,
279 MUL2 = 1,
280 MUL4 = 2,
281 DIV2 = 3
282 };
283}
284
285namespace AMDGPU {
286namespace VGPRIndexMode {
287
288enum Id : unsigned { // id of symbolic names
289 ID_SRC0 = 0,
290 ID_SRC1,
291 ID_SRC2,
292 ID_DST,
293
294 ID_MIN = ID_SRC0,
295 ID_MAX = ID_DST
296};
297
298enum EncBits : unsigned {
299 OFF = 0,
300 SRC0_ENABLE = 1 << ID_SRC0,
301 SRC1_ENABLE = 1 << ID_SRC1,
302 SRC2_ENABLE = 1 << ID_SRC2,
303 DST_ENABLE = 1 << ID_DST,
304 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
305 UNDEF = 0xFFFF
306};
307
308} // namespace VGPRIndexMode
309} // namespace AMDGPU
310
311namespace AMDGPUAsmVariants {
312 enum : unsigned {
313 DEFAULT = 0,
314 VOP3 = 1,
315 SDWA = 2,
316 SDWA9 = 3,
317 DPP = 4,
318 VOP3_DPP = 5
319 };
320} // namespace AMDGPUAsmVariants
321
322namespace AMDGPU {
323namespace EncValues { // Encoding values of enum9/8/7 operands
324
325enum : unsigned {
326 SGPR_MIN = 0,
327 SGPR_MAX_SI = 101,
328 SGPR_MAX_GFX10 = 105,
329 TTMP_VI_MIN = 112,
330 TTMP_VI_MAX = 123,
331 TTMP_GFX9PLUS_MIN = 108,
332 TTMP_GFX9PLUS_MAX = 123,
333 INLINE_INTEGER_C_MIN = 128,
334 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
335 INLINE_INTEGER_C_MAX = 208,
336 INLINE_FLOATING_C_MIN = 240,
337 INLINE_FLOATING_C_MAX = 248,
338 LITERAL_CONST = 255,
339 VGPR_MIN = 256,
340 VGPR_MAX = 511,
341 IS_VGPR = 256, // Indicates VGPR or AGPR
342};
343
344} // namespace EncValues
345
346// Register codes as defined in the TableGen's HWEncoding field.
347namespace HWEncoding {
348enum : unsigned {
349 REG_IDX_MASK = 0xff,
350 IS_VGPR = 1 << 8,
351 IS_AGPR = 1 << 9,
352 IS_HI16 = 1 << 10,
353};
354} // namespace HWEncoding
355
356namespace CPol {
357
358enum CPol {
359 GLC = 1,
360 SLC = 2,
361 DLC = 4,
362 SCC = 16,
363 SC0 = GLC,
364 SC1 = SCC,
365 NT = SLC,
366 ALL_pregfx12 = GLC | SLC | DLC | SCC,
367 SWZ_pregfx12 = 8,
368
369 // Below are GFX12+ cache policy bits
370
371 // Temporal hint
372 TH = 0x7, // All TH bits
373 TH_RT = 0, // regular
374 TH_NT = 1, // non-temporal
375 TH_HT = 2, // high-temporal
376 TH_LU = 3, // last use
377 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
378 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
379 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
380 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
381 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
382 TH_BYPASS = 3, // only to be used with scope = 3
383
384 TH_RESERVED = 7, // unused value for load insts
385
386 // Bits of TH for atomics
387 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
388 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
389 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
390
391 // Scope
392 SCOPE = 0x3 << 3, // All Scope bits
393 SCOPE_CU = 0 << 3,
394 SCOPE_SE = 1 << 3,
395 SCOPE_DEV = 2 << 3,
396 SCOPE_SYS = 3 << 3,
397
398 SWZ = 1 << 6, // Swizzle bit
399
400 ALL = TH | SCOPE,
401
402 // Helper bits
403 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
404 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
405 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
406 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
407
408 // Volatile (used to preserve/signal operation volatility for buffer
409 // operations not a real instruction bit)
410 VOLATILE = 1 << 31,
411};
412
413} // namespace CPol
414
415namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
416
417enum Id { // Message ID, width(4) [3:0].
418 ID_INTERRUPT = 1,
419
420 ID_GS_PreGFX11 = 2, // replaced in GFX11
421 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
422
423 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
424 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
425
426 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
427 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
428 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
429 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
430 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
431 ID_GS_ALLOC_REQ = 9, // added in GFX9
432 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
433 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
434 ID_SYSMSG = 15,
435
436 ID_RTN_GET_DOORBELL = 128,
437 ID_RTN_GET_DDID = 129,
438 ID_RTN_GET_TMA = 130,
439 ID_RTN_GET_REALTIME = 131,
440 ID_RTN_SAVE_WAVE = 132,
441 ID_RTN_GET_TBA = 133,
442 ID_RTN_GET_TBA_TO_PC = 134,
443 ID_RTN_GET_SE_AID_ID = 135,
444
445 ID_MASK_PreGFX11_ = 0xF,
446 ID_MASK_GFX11Plus_ = 0xFF
447};
448
449enum Op { // Both GS and SYS operation IDs.
450 OP_SHIFT_ = 4,
451 OP_NONE_ = 0,
452 // Bits used for operation encoding
453 OP_WIDTH_ = 3,
454 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
455 // GS operations are encoded in bits 5:4
456 OP_GS_NOP = 0,
457 OP_GS_CUT = 1,
458 OP_GS_EMIT = 2,
459 OP_GS_EMIT_CUT = 3,
460 OP_GS_FIRST_ = OP_GS_NOP,
461 // SYS operations are encoded in bits 6:4
462 OP_SYS_ECC_ERR_INTERRUPT = 1,
463 OP_SYS_REG_RD = 2,
464 OP_SYS_HOST_TRAP_ACK = 3,
465 OP_SYS_TTRACE_PC = 4,
466 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
467};
468
469enum StreamId : unsigned { // Stream ID, (2) [9:8].
470 STREAM_ID_NONE_ = 0,
471 STREAM_ID_DEFAULT_ = 0,
472 STREAM_ID_LAST_ = 4,
473 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
474 STREAM_ID_SHIFT_ = 8,
475 STREAM_ID_WIDTH_= 2,
476 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
477};
478
479} // namespace SendMsg
480
481namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
482
483enum Id { // HwRegCode, (6) [5:0]
484 ID_MODE = 1,
485 ID_STATUS = 2,
486 ID_TRAPSTS = 3,
487 ID_HW_ID = 4,
488 ID_GPR_ALLOC = 5,
489 ID_LDS_ALLOC = 6,
490 ID_IB_STS = 7,
491 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
492 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
493 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
494 ID_MEM_BASES = 15,
495 ID_TBA_LO = 16,
496 ID_TBA_HI = 17,
497 ID_TMA_LO = 18,
498 ID_TMA_HI = 19,
499 ID_FLAT_SCR_LO = 20,
500 ID_FLAT_SCR_HI = 21,
501 ID_XNACK_MASK = 22,
502 ID_HW_ID1 = 23,
503 ID_HW_ID2 = 24,
504 ID_POPS_PACKER = 25,
505 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
506 ID_SHADER_CYCLES = 29,
507 ID_SHADER_CYCLES_HI = 30,
508 ID_DVGPR_ALLOC_LO = 31,
509 ID_DVGPR_ALLOC_HI = 32,
510
511 // Register numbers reused in GFX11
512 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
513 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
514
515 // Register numbers reused in GFX12+
516 ID_STATE_PRIV = 4,
517 ID_PERF_SNAPSHOT_DATA1 = 15,
518 ID_PERF_SNAPSHOT_DATA2 = 16,
519 ID_EXCP_FLAG_PRIV = 17,
520 ID_EXCP_FLAG_USER = 18,
521 ID_TRAP_CTRL = 19,
522
523 // GFX94* specific registers
524 ID_XCC_ID = 20,
525 ID_SQ_PERF_SNAPSHOT_DATA = 21,
526 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
527 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
528 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
529};
530
531enum Offset : unsigned { // Offset, (5) [10:6]
532 OFFSET_MEM_VIOL = 8,
533 OFFSET_ME_ID = 8, // in HW_ID2
534};
535
536enum ModeRegisterMasks : uint32_t {
537 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
538 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
539 DX10_CLAMP_MASK = 1 << 8,
540 IEEE_MODE_MASK = 1 << 9,
541 LOD_CLAMP_MASK = 1 << 10,
542 DEBUG_MASK = 1 << 11,
543
544 // EXCP_EN fields.
545 EXCP_EN_INVALID_MASK = 1 << 12,
546 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
547 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
548 EXCP_EN_OVERFLOW_MASK = 1 << 15,
549 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
550 EXCP_EN_INEXACT_MASK = 1 << 17,
551 EXCP_EN_INT_DIV0_MASK = 1 << 18,
552
553 GPR_IDX_EN_MASK = 1 << 27,
554 VSKIP_MASK = 1 << 28,
555 CSP_MASK = 0x7u << 29 // Bits 29..31
556};
557
558} // namespace Hwreg
559
560namespace MTBUFFormat {
561
562enum DataFormat : int64_t {
563 DFMT_INVALID = 0,
564 DFMT_8,
565 DFMT_16,
566 DFMT_8_8,
567 DFMT_32,
568 DFMT_16_16,
569 DFMT_10_11_11,
570 DFMT_11_11_10,
571 DFMT_10_10_10_2,
572 DFMT_2_10_10_10,
573 DFMT_8_8_8_8,
574 DFMT_32_32,
575 DFMT_16_16_16_16,
576 DFMT_32_32_32,
577 DFMT_32_32_32_32,
578 DFMT_RESERVED_15,
579
580 DFMT_MIN = DFMT_INVALID,
581 DFMT_MAX = DFMT_RESERVED_15,
582
583 DFMT_UNDEF = -1,
584 DFMT_DEFAULT = DFMT_8,
585
586 DFMT_SHIFT = 0,
587 DFMT_MASK = 0xF
588};
589
590enum NumFormat : int64_t {
591 NFMT_UNORM = 0,
592 NFMT_SNORM,
593 NFMT_USCALED,
594 NFMT_SSCALED,
595 NFMT_UINT,
596 NFMT_SINT,
597 NFMT_RESERVED_6, // VI and GFX9
598 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
599 NFMT_FLOAT,
600
601 NFMT_MIN = NFMT_UNORM,
602 NFMT_MAX = NFMT_FLOAT,
603
604 NFMT_UNDEF = -1,
605 NFMT_DEFAULT = NFMT_UNORM,
606
607 NFMT_SHIFT = 4,
608 NFMT_MASK = 7
609};
610
611enum MergedFormat : int64_t {
612 DFMT_NFMT_UNDEF = -1,
613 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
614 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
615
616
617 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
618
619 DFMT_NFMT_MAX = DFMT_NFMT_MASK
620};
621
622enum UnifiedFormatCommon : int64_t {
623 UFMT_MAX = 127,
624 UFMT_UNDEF = -1,
625 UFMT_DEFAULT = 1
626};
627
628} // namespace MTBUFFormat
629
630namespace UfmtGFX10 {
631enum UnifiedFormat : int64_t {
632 UFMT_INVALID = 0,
633
634 UFMT_8_UNORM,
635 UFMT_8_SNORM,
636 UFMT_8_USCALED,
637 UFMT_8_SSCALED,
638 UFMT_8_UINT,
639 UFMT_8_SINT,
640
641 UFMT_16_UNORM,
642 UFMT_16_SNORM,
643 UFMT_16_USCALED,
644 UFMT_16_SSCALED,
645 UFMT_16_UINT,
646 UFMT_16_SINT,
647 UFMT_16_FLOAT,
648
649 UFMT_8_8_UNORM,
650 UFMT_8_8_SNORM,
651 UFMT_8_8_USCALED,
652 UFMT_8_8_SSCALED,
653 UFMT_8_8_UINT,
654 UFMT_8_8_SINT,
655
656 UFMT_32_UINT,
657 UFMT_32_SINT,
658 UFMT_32_FLOAT,
659
660 UFMT_16_16_UNORM,
661 UFMT_16_16_SNORM,
662 UFMT_16_16_USCALED,
663 UFMT_16_16_SSCALED,
664 UFMT_16_16_UINT,
665 UFMT_16_16_SINT,
666 UFMT_16_16_FLOAT,
667
668 UFMT_10_11_11_UNORM,
669 UFMT_10_11_11_SNORM,
670 UFMT_10_11_11_USCALED,
671 UFMT_10_11_11_SSCALED,
672 UFMT_10_11_11_UINT,
673 UFMT_10_11_11_SINT,
674 UFMT_10_11_11_FLOAT,
675
676 UFMT_11_11_10_UNORM,
677 UFMT_11_11_10_SNORM,
678 UFMT_11_11_10_USCALED,
679 UFMT_11_11_10_SSCALED,
680 UFMT_11_11_10_UINT,
681 UFMT_11_11_10_SINT,
682 UFMT_11_11_10_FLOAT,
683
684 UFMT_10_10_10_2_UNORM,
685 UFMT_10_10_10_2_SNORM,
686 UFMT_10_10_10_2_USCALED,
687 UFMT_10_10_10_2_SSCALED,
688 UFMT_10_10_10_2_UINT,
689 UFMT_10_10_10_2_SINT,
690
691 UFMT_2_10_10_10_UNORM,
692 UFMT_2_10_10_10_SNORM,
693 UFMT_2_10_10_10_USCALED,
694 UFMT_2_10_10_10_SSCALED,
695 UFMT_2_10_10_10_UINT,
696 UFMT_2_10_10_10_SINT,
697
698 UFMT_8_8_8_8_UNORM,
699 UFMT_8_8_8_8_SNORM,
700 UFMT_8_8_8_8_USCALED,
701 UFMT_8_8_8_8_SSCALED,
702 UFMT_8_8_8_8_UINT,
703 UFMT_8_8_8_8_SINT,
704
705 UFMT_32_32_UINT,
706 UFMT_32_32_SINT,
707 UFMT_32_32_FLOAT,
708
709 UFMT_16_16_16_16_UNORM,
710 UFMT_16_16_16_16_SNORM,
711 UFMT_16_16_16_16_USCALED,
712 UFMT_16_16_16_16_SSCALED,
713 UFMT_16_16_16_16_UINT,
714 UFMT_16_16_16_16_SINT,
715 UFMT_16_16_16_16_FLOAT,
716
717 UFMT_32_32_32_UINT,
718 UFMT_32_32_32_SINT,
719 UFMT_32_32_32_FLOAT,
720 UFMT_32_32_32_32_UINT,
721 UFMT_32_32_32_32_SINT,
722 UFMT_32_32_32_32_FLOAT,
723
724 UFMT_FIRST = UFMT_INVALID,
725 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
726};
727
728} // namespace UfmtGFX10
729
730namespace UfmtGFX11 {
731enum UnifiedFormat : int64_t {
732 UFMT_INVALID = 0,
733
734 UFMT_8_UNORM,
735 UFMT_8_SNORM,
736 UFMT_8_USCALED,
737 UFMT_8_SSCALED,
738 UFMT_8_UINT,
739 UFMT_8_SINT,
740
741 UFMT_16_UNORM,
742 UFMT_16_SNORM,
743 UFMT_16_USCALED,
744 UFMT_16_SSCALED,
745 UFMT_16_UINT,
746 UFMT_16_SINT,
747 UFMT_16_FLOAT,
748
749 UFMT_8_8_UNORM,
750 UFMT_8_8_SNORM,
751 UFMT_8_8_USCALED,
752 UFMT_8_8_SSCALED,
753 UFMT_8_8_UINT,
754 UFMT_8_8_SINT,
755
756 UFMT_32_UINT,
757 UFMT_32_SINT,
758 UFMT_32_FLOAT,
759
760 UFMT_16_16_UNORM,
761 UFMT_16_16_SNORM,
762 UFMT_16_16_USCALED,
763 UFMT_16_16_SSCALED,
764 UFMT_16_16_UINT,
765 UFMT_16_16_SINT,
766 UFMT_16_16_FLOAT,
767
768 UFMT_10_11_11_FLOAT,
769
770 UFMT_11_11_10_FLOAT,
771
772 UFMT_10_10_10_2_UNORM,
773 UFMT_10_10_10_2_SNORM,
774 UFMT_10_10_10_2_UINT,
775 UFMT_10_10_10_2_SINT,
776
777 UFMT_2_10_10_10_UNORM,
778 UFMT_2_10_10_10_SNORM,
779 UFMT_2_10_10_10_USCALED,
780 UFMT_2_10_10_10_SSCALED,
781 UFMT_2_10_10_10_UINT,
782 UFMT_2_10_10_10_SINT,
783
784 UFMT_8_8_8_8_UNORM,
785 UFMT_8_8_8_8_SNORM,
786 UFMT_8_8_8_8_USCALED,
787 UFMT_8_8_8_8_SSCALED,
788 UFMT_8_8_8_8_UINT,
789 UFMT_8_8_8_8_SINT,
790
791 UFMT_32_32_UINT,
792 UFMT_32_32_SINT,
793 UFMT_32_32_FLOAT,
794
795 UFMT_16_16_16_16_UNORM,
796 UFMT_16_16_16_16_SNORM,
797 UFMT_16_16_16_16_USCALED,
798 UFMT_16_16_16_16_SSCALED,
799 UFMT_16_16_16_16_UINT,
800 UFMT_16_16_16_16_SINT,
801 UFMT_16_16_16_16_FLOAT,
802
803 UFMT_32_32_32_UINT,
804 UFMT_32_32_32_SINT,
805 UFMT_32_32_32_FLOAT,
806 UFMT_32_32_32_32_UINT,
807 UFMT_32_32_32_32_SINT,
808 UFMT_32_32_32_32_FLOAT,
809
810 UFMT_FIRST = UFMT_INVALID,
811 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
812};
813
814} // namespace UfmtGFX11
815
816namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
817
818enum Id : unsigned { // id of symbolic names
819 ID_QUAD_PERM = 0,
820 ID_BITMASK_PERM,
821 ID_SWAP,
822 ID_REVERSE,
823 ID_BROADCAST,
824 ID_FFT,
825 ID_ROTATE
826};
827
828// clang-format off
829enum EncBits : unsigned {
830
831 // swizzle mode encodings
832
833 QUAD_PERM_ENC = 0x8000,
834 QUAD_PERM_ENC_MASK = 0xFF00,
835
836 BITMASK_PERM_ENC = 0x0000,
837 BITMASK_PERM_ENC_MASK = 0x8000,
838
839 FFT_MODE_ENC = 0xE000,
840
841 ROTATE_MODE_ENC = 0xC000,
842 FFT_ROTATE_MODE_MASK = 0xF000,
843
844 ROTATE_MODE_LO = 0xC000,
845 FFT_MODE_LO = 0xE000,
846
847 // QUAD_PERM encodings
848
849 LANE_MASK = 0x3,
850 LANE_MAX = LANE_MASK,
851 LANE_SHIFT = 2,
852 LANE_NUM = 4,
853
854 // BITMASK_PERM encodings
855
856 BITMASK_MASK = 0x1F,
857 BITMASK_MAX = BITMASK_MASK,
858 BITMASK_WIDTH = 5,
859
860 BITMASK_AND_SHIFT = 0,
861 BITMASK_OR_SHIFT = 5,
862 BITMASK_XOR_SHIFT = 10,
863
864 // FFT encodings
865
866 FFT_SWIZZLE_MASK = 0x1F,
867 FFT_SWIZZLE_MAX = 0x1F,
868
869 // ROTATE encodings
870 ROTATE_MAX_SIZE = 0x1F,
871 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
872 ROTATE_DIR_MASK = 0x1,
873 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
874 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
875};
876// clang-format on
877
878} // namespace Swizzle
879
880namespace SDWA {
881
882enum SdwaSel : unsigned {
883 BYTE_0 = 0,
884 BYTE_1 = 1,
885 BYTE_2 = 2,
886 BYTE_3 = 3,
887 WORD_0 = 4,
888 WORD_1 = 5,
889 DWORD = 6,
890};
891
892enum DstUnused : unsigned {
893 UNUSED_PAD = 0,
894 UNUSED_SEXT = 1,
895 UNUSED_PRESERVE = 2,
896};
897
898enum SDWA9EncValues : unsigned {
899 SRC_SGPR_MASK = 0x100,
900 SRC_VGPR_MASK = 0xFF,
901 VOPC_DST_VCC_MASK = 0x80,
902 VOPC_DST_SGPR_MASK = 0x7F,
903
904 SRC_VGPR_MIN = 0,
905 SRC_VGPR_MAX = 255,
906 SRC_SGPR_MIN = 256,
907 SRC_SGPR_MAX_SI = 357,
908 SRC_SGPR_MAX_GFX10 = 361,
909 SRC_TTMP_MIN = 364,
910 SRC_TTMP_MAX = 379,
911};
912
913} // namespace SDWA
914
915namespace DPP {
916
917// clang-format off
918enum DppCtrl : unsigned {
919 QUAD_PERM_FIRST = 0,
920 QUAD_PERM_ID = 0xE4, // identity permutation
921 QUAD_PERM_LAST = 0xFF,
922 DPP_UNUSED1 = 0x100,
923 ROW_SHL0 = 0x100,
924 ROW_SHL_FIRST = 0x101,
925 ROW_SHL_LAST = 0x10F,
926 DPP_UNUSED2 = 0x110,
927 ROW_SHR0 = 0x110,
928 ROW_SHR_FIRST = 0x111,
929 ROW_SHR_LAST = 0x11F,
930 DPP_UNUSED3 = 0x120,
931 ROW_ROR0 = 0x120,
932 ROW_ROR_FIRST = 0x121,
933 ROW_ROR_LAST = 0x12F,
934 WAVE_SHL1 = 0x130,
935 DPP_UNUSED4_FIRST = 0x131,
936 DPP_UNUSED4_LAST = 0x133,
937 WAVE_ROL1 = 0x134,
938 DPP_UNUSED5_FIRST = 0x135,
939 DPP_UNUSED5_LAST = 0x137,
940 WAVE_SHR1 = 0x138,
941 DPP_UNUSED6_FIRST = 0x139,
942 DPP_UNUSED6_LAST = 0x13B,
943 WAVE_ROR1 = 0x13C,
944 DPP_UNUSED7_FIRST = 0x13D,
945 DPP_UNUSED7_LAST = 0x13F,
946 ROW_MIRROR = 0x140,
947 ROW_HALF_MIRROR = 0x141,
948 BCAST15 = 0x142,
949 BCAST31 = 0x143,
950 DPP_UNUSED8_FIRST = 0x144,
951 DPP_UNUSED8_LAST = 0x14F,
952 ROW_NEWBCAST_FIRST= 0x150,
953 ROW_NEWBCAST_LAST = 0x15F,
954 ROW_SHARE0 = 0x150,
955 ROW_SHARE_FIRST = 0x150,
956 ROW_SHARE_LAST = 0x15F,
957 ROW_XMASK0 = 0x160,
958 ROW_XMASK_FIRST = 0x160,
959 ROW_XMASK_LAST = 0x16F,
960 DPP_LAST = ROW_XMASK_LAST
961};
962// clang-format on
963
964enum DppFiMode {
965 DPP_FI_0 = 0,
966 DPP_FI_1 = 1,
967 DPP8_FI_0 = 0xE9,
968 DPP8_FI_1 = 0xEA,
969};
970
971} // namespace DPP
972
973namespace Exp {
974
975enum Target : unsigned {
976 ET_MRT0 = 0,
977 ET_MRT7 = 7,
978 ET_MRTZ = 8,
979 ET_NULL = 9, // Pre-GFX11
980 ET_POS0 = 12,
981 ET_POS3 = 15,
982 ET_POS4 = 16, // GFX10+
983 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
984 ET_PRIM = 20, // GFX10+
985 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
986 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
987 ET_PARAM0 = 32, // Pre-GFX11
988 ET_PARAM31 = 63, // Pre-GFX11
989
990 ET_NULL_MAX_IDX = 0,
991 ET_MRTZ_MAX_IDX = 0,
992 ET_PRIM_MAX_IDX = 0,
993 ET_MRT_MAX_IDX = 7,
994 ET_POS_MAX_IDX = 4,
995 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
996 ET_PARAM_MAX_IDX = 31,
997
998 ET_INVALID = 255,
999};
1000
1001} // namespace Exp
1002
1003namespace VOP3PEncoding {
1004
1005enum OpSel : uint64_t {
1006 OP_SEL_HI_0 = UINT64_C(1) << 59,
1007 OP_SEL_HI_1 = UINT64_C(1) << 60,
1008 OP_SEL_HI_2 = UINT64_C(1) << 14,
1009};
1010
1011} // namespace VOP3PEncoding
1012
1013namespace ImplicitArg {
1014// Implicit kernel argument offset for code object version 5.
1015enum Offset_COV5 : unsigned {
1016 HOSTCALL_PTR_OFFSET = 80,
1017 MULTIGRID_SYNC_ARG_OFFSET = 88,
1018 HEAP_PTR_OFFSET = 96,
1019
1020 DEFAULT_QUEUE_OFFSET = 104,
1021 COMPLETION_ACTION_OFFSET = 112,
1022
1023 PRIVATE_BASE_OFFSET = 192,
1024 SHARED_BASE_OFFSET = 196,
1025 QUEUE_PTR_OFFSET = 200,
1026};
1027
1028} // namespace ImplicitArg
1029
1030namespace MFMAScaleFormats {
1031// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix
1032// format.
1033enum MFMAScaleFormats {
1034 FP8_E4M3 = 0,
1035 FP8_E5M2 = 1,
1036 FP6_E2M3 = 2,
1037 FP6_E3M2 = 3,
1038 FP4_E2M1 = 4
1039};
1040} // namespace MFMAScaleFormats
1041
1042namespace VirtRegFlag {
1043// Virtual register flags used for various target specific handlings during
1044// codegen.
1045enum Register_Flag : uint8_t {
1046 // Register operand in a whole-wave mode operation.
1047 WWM_REG = 1 << 0,
1048};
1049
1050} // namespace VirtRegFlag
1051
1052} // namespace AMDGPU
1053
1054namespace AMDGPU {
1055namespace Barrier {
1056
1057enum Type { TRAP = -2, WORKGROUP = -1 };
1058
1059enum {
1060 BARRIER_SCOPE_WORKGROUP = 0,
1061};
1062
1063} // namespace Barrier
1064} // namespace AMDGPU
1065
1066// clang-format off
1067
1068#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1069#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1070#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1071#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1072#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1073#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1074
1075#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1076#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1077#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1078#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1079#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1080#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1081
1082#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1083#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1084#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1085#define C_00B228_WGP_MODE 0xF7FFFFFF
1086#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1087#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1088#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1089
1090#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1091#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1092#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1093#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1094#define C_00B428_WGP_MODE 0xFBFFFFFF
1095#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1096#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1097#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1098
1099#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1100
1101#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1102#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1103#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1104#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1105#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1106#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1107#define C_00B84C_USER_SGPR 0xFFFFFFC1
1108#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1109#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1110#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1111#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1112#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1113#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1114#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1115#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1116#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1117#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1118#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1119#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1120#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1121#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1122#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1123#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1124#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1125#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1126/* CIK */
1127#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1128#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1129#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1130/* */
1131#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1132#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1133#define C_00B84C_LDS_SIZE 0xFF007FFF
1134#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1135#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1136#define C_00B84C_EXCP_EN 0x80FFFFFF
1137
1138#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1139#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1140
1141#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1142#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1143#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1144#define C_00B848_VGPRS 0xFFFFFFC0
1145#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1146#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1147#define C_00B848_SGPRS 0xFFFFFC3F
1148#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1149#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1150#define C_00B848_PRIORITY 0xFFFFF3FF
1151#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1152#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1153#define C_00B848_FLOAT_MODE 0xFFF00FFF
1154#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1155#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1156#define C_00B848_PRIV 0xFFEFFFFF
1157#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1158#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1159#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1160#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1161#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1162#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1163#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1164#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1165#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1166#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1167#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1168#define C_00B848_IEEE_MODE 0xFF7FFFFF
1169#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1170#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1171#define C_00B848_WGP_MODE 0xDFFFFFFF
1172#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1173#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1174#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1175#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1176#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1177#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1178
1179// Helpers for setting FLOAT_MODE
1180#define FP_ROUND_ROUND_TO_NEAREST 0
1181#define FP_ROUND_ROUND_TO_INF 1
1182#define FP_ROUND_ROUND_TO_NEGINF 2
1183#define FP_ROUND_ROUND_TO_ZERO 3
1184
1185// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1186// precision.
1187#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1188#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1189
1190#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1191#define FP_DENORM_FLUSH_OUT 1
1192#define FP_DENORM_FLUSH_IN 2
1193#define FP_DENORM_FLUSH_NONE 3
1194
1195
1196// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1197// precision.
1198#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1199#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1200
1201#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1202#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1203#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1204#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1205
1206#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1207#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1208#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1209#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1210
1211#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1212#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1213#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1214#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1215#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1216#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1217#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1218#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1219
1220#define R_SPILLED_SGPRS 0x4
1221#define R_SPILLED_VGPRS 0x8
1222
1223// clang-format on
1224
1225} // End namespace llvm
1226
1227#endif
1228

source code of llvm/lib/Target/AMDGPU/SIDefines.h