1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
19 RegTupleAlignUnitsWidth = 2,
20 HasVGPRBit = RegTupleAlignUnitsWidth,
21 HasAGPRBit,
22 HasSGPRbit,
23
24 HasVGPR = 1 << HasVGPRBit,
25 HasAGPR = 1 << HasAGPRBit,
26 HasSGPR = 1 << HasSGPRbit,
27
28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,
29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
30}; // enum SIRCFlagsr
31
32namespace SIEncodingFamily {
33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
34// and the columns of the getMCOpcodeGen table.
35enum {
36 SI = 0,
37 VI = 1,
38 SDWA = 2,
39 SDWA9 = 3,
40 GFX80 = 4,
41 GFX9 = 5,
42 GFX10 = 6,
43 SDWA10 = 7,
44 GFX90A = 8,
45 GFX940 = 9,
46 GFX11 = 10,
47 GFX12 = 11,
48};
49}
50
51namespace SIInstrFlags {
52// This needs to be kept in sync with the field bits in InstSI.
53enum : uint64_t {
54 // Low bits - basic encoding information.
55 SALU = 1 << 0,
56 VALU = 1 << 1,
57
58 // SALU instruction formats.
59 SOP1 = 1 << 2,
60 SOP2 = 1 << 3,
61 SOPC = 1 << 4,
62 SOPK = 1 << 5,
63 SOPP = 1 << 6,
64
65 // VALU instruction formats.
66 VOP1 = 1 << 7,
67 VOP2 = 1 << 8,
68 VOPC = 1 << 9,
69
70 // TODO: Should this be spilt into VOP3 a and b?
71 VOP3 = 1 << 10,
72 VOP3P = 1 << 12,
73
74 VINTRP = 1 << 13,
75 SDWA = 1 << 14,
76 DPP = 1 << 15,
77 TRANS = 1 << 16,
78
79 // Memory instruction formats.
80 MUBUF = 1 << 17,
81 MTBUF = 1 << 18,
82 SMRD = 1 << 19,
83 MIMG = 1 << 20,
84 VIMAGE = 1 << 21,
85 VSAMPLE = 1 << 22,
86 EXP = 1 << 23,
87 FLAT = 1 << 24,
88 DS = 1 << 25,
89
90 // Combined SGPR/VGPR Spill bit
91 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
92 Spill = 1 << 26,
93
94 // LDSDIR instruction format.
95 LDSDIR = 1 << 28,
96
97 // VINTERP instruction format.
98 VINTERP = 1 << 29,
99
100 // High bits - other information.
101 VM_CNT = UINT64_C(1) << 32,
102 EXP_CNT = UINT64_C(1) << 33,
103 LGKM_CNT = UINT64_C(1) << 34,
104
105 WQM = UINT64_C(1) << 35,
106 DisableWQM = UINT64_C(1) << 36,
107 Gather4 = UINT64_C(1) << 37,
108
109 // Reserved, must be 0.
110 Reserved0 = UINT64_C(1) << 38,
111
112 SCALAR_STORE = UINT64_C(1) << 39,
113 FIXED_SIZE = UINT64_C(1) << 40,
114
115 // Reserved, must be 0.
116 Reserved1 = UINT64_C(1) << 41,
117
118 VOP3_OPSEL = UINT64_C(1) << 42,
119 maybeAtomic = UINT64_C(1) << 43,
120 renamedInGFX9 = UINT64_C(1) << 44,
121
122 // Is a clamp on FP type.
123 FPClamp = UINT64_C(1) << 45,
124
125 // Is an integer clamp
126 IntClamp = UINT64_C(1) << 46,
127
128 // Clamps lo component of register.
129 ClampLo = UINT64_C(1) << 47,
130
131 // Clamps hi component of register.
132 // ClampLo and ClampHi set for packed clamp.
133 ClampHi = UINT64_C(1) << 48,
134
135 // Is a packed VOP3P instruction.
136 IsPacked = UINT64_C(1) << 49,
137
138 // Is a D16 buffer instruction.
139 D16Buf = UINT64_C(1) << 50,
140
141 // FLAT instruction accesses FLAT_GLBL segment.
142 FlatGlobal = UINT64_C(1) << 51,
143
144 // Uses floating point double precision rounding mode
145 FPDPRounding = UINT64_C(1) << 52,
146
147 // Instruction is FP atomic.
148 FPAtomic = UINT64_C(1) << 53,
149
150 // Is a MFMA instruction.
151 IsMAI = UINT64_C(1) << 54,
152
153 // Is a DOT instruction.
154 IsDOT = UINT64_C(1) << 55,
155
156 // FLAT instruction accesses FLAT_SCRATCH segment.
157 FlatScratch = UINT64_C(1) << 56,
158
159 // Atomic without return.
160 IsAtomicNoRet = UINT64_C(1) << 57,
161
162 // Atomic with return.
163 IsAtomicRet = UINT64_C(1) << 58,
164
165 // Is a WMMA instruction.
166 IsWMMA = UINT64_C(1) << 59,
167
168 // Whether tied sources will be read.
169 TiedSourceNotRead = UINT64_C(1) << 60,
170
171 // Is never uniform.
172 IsNeverUniform = UINT64_C(1) << 61,
173
174 // ds_gws_* instructions.
175 GWS = UINT64_C(1) << 62,
176
177 // Is a SWMMAC instruction.
178 IsSWMMAC = UINT64_C(1) << 63,
179};
180
181// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
182// The result is true if any of these tests are true.
183enum ClassFlags : unsigned {
184 S_NAN = 1 << 0, // Signaling NaN
185 Q_NAN = 1 << 1, // Quiet NaN
186 N_INFINITY = 1 << 2, // Negative infinity
187 N_NORMAL = 1 << 3, // Negative normal
188 N_SUBNORMAL = 1 << 4, // Negative subnormal
189 N_ZERO = 1 << 5, // Negative zero
190 P_ZERO = 1 << 6, // Positive zero
191 P_SUBNORMAL = 1 << 7, // Positive subnormal
192 P_NORMAL = 1 << 8, // Positive normal
193 P_INFINITY = 1 << 9 // Positive infinity
194};
195}
196
197namespace AMDGPU {
198enum OperandType : unsigned {
199 /// Operands with register or 32-bit immediate
200 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
201 OPERAND_REG_IMM_INT64,
202 OPERAND_REG_IMM_INT16,
203 OPERAND_REG_IMM_FP32,
204 OPERAND_REG_IMM_FP64,
205 OPERAND_REG_IMM_BF16,
206 OPERAND_REG_IMM_FP16,
207 OPERAND_REG_IMM_BF16_DEFERRED,
208 OPERAND_REG_IMM_FP16_DEFERRED,
209 OPERAND_REG_IMM_FP32_DEFERRED,
210 OPERAND_REG_IMM_V2BF16,
211 OPERAND_REG_IMM_V2FP16,
212 OPERAND_REG_IMM_V2INT16,
213 OPERAND_REG_IMM_V2INT32,
214 OPERAND_REG_IMM_V2FP32,
215
216 /// Operands with register or inline constant
217 OPERAND_REG_INLINE_C_INT16,
218 OPERAND_REG_INLINE_C_INT32,
219 OPERAND_REG_INLINE_C_INT64,
220 OPERAND_REG_INLINE_C_BF16,
221 OPERAND_REG_INLINE_C_FP16,
222 OPERAND_REG_INLINE_C_FP32,
223 OPERAND_REG_INLINE_C_FP64,
224 OPERAND_REG_INLINE_C_V2INT16,
225 OPERAND_REG_INLINE_C_V2BF16,
226 OPERAND_REG_INLINE_C_V2FP16,
227 OPERAND_REG_INLINE_C_V2INT32,
228 OPERAND_REG_INLINE_C_V2FP32,
229
230 // Operand for split barrier inline constant
231 OPERAND_INLINE_SPLIT_BARRIER_INT32,
232
233 /// Operand with 32-bit immediate that uses the constant bus.
234 OPERAND_KIMM32,
235 OPERAND_KIMM16,
236
237 /// Operands with an AccVGPR register or inline constant
238 OPERAND_REG_INLINE_AC_INT16,
239 OPERAND_REG_INLINE_AC_INT32,
240 OPERAND_REG_INLINE_AC_BF16,
241 OPERAND_REG_INLINE_AC_FP16,
242 OPERAND_REG_INLINE_AC_FP32,
243 OPERAND_REG_INLINE_AC_FP64,
244 OPERAND_REG_INLINE_AC_V2INT16,
245 OPERAND_REG_INLINE_AC_V2BF16,
246 OPERAND_REG_INLINE_AC_V2FP16,
247 OPERAND_REG_INLINE_AC_V2INT32,
248 OPERAND_REG_INLINE_AC_V2FP32,
249
250 // Operand for source modifiers for VOP instructions
251 OPERAND_INPUT_MODS,
252
253 // Operand for SDWA instructions
254 OPERAND_SDWA_VOPC_DST,
255
256 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
257 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
258
259 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
260 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,
261
262 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
263 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,
264
265 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
266 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
267
268 OPERAND_KIMM_FIRST = OPERAND_KIMM32,
269 OPERAND_KIMM_LAST = OPERAND_KIMM16
270
271};
272
273// Should be in sync with the OperandSemantics defined in SIRegisterInfo.td
274enum OperandSemantics : unsigned {
275 INT = 0,
276 FP16 = 1,
277 BF16 = 2,
278 FP32 = 3,
279 FP64 = 4,
280};
281}
282
283// Input operand modifiers bit-masks
284// NEG and SEXT share same bit-mask because they can't be set simultaneously.
285namespace SISrcMods {
286 enum : unsigned {
287 NONE = 0,
288 NEG = 1 << 0, // Floating-point negate modifier
289 ABS = 1 << 1, // Floating-point absolute modifier
290 SEXT = 1 << 0, // Integer sign-extend modifier
291 NEG_HI = ABS, // Floating-point negate high packed component modifier.
292 OP_SEL_0 = 1 << 2,
293 OP_SEL_1 = 1 << 3,
294 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
295 };
296}
297
298namespace SIOutMods {
299 enum : unsigned {
300 NONE = 0,
301 MUL2 = 1,
302 MUL4 = 2,
303 DIV2 = 3
304 };
305}
306
307namespace AMDGPU {
308namespace VGPRIndexMode {
309
310enum Id : unsigned { // id of symbolic names
311 ID_SRC0 = 0,
312 ID_SRC1,
313 ID_SRC2,
314 ID_DST,
315
316 ID_MIN = ID_SRC0,
317 ID_MAX = ID_DST
318};
319
320enum EncBits : unsigned {
321 OFF = 0,
322 SRC0_ENABLE = 1 << ID_SRC0,
323 SRC1_ENABLE = 1 << ID_SRC1,
324 SRC2_ENABLE = 1 << ID_SRC2,
325 DST_ENABLE = 1 << ID_DST,
326 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
327 UNDEF = 0xFFFF
328};
329
330} // namespace VGPRIndexMode
331} // namespace AMDGPU
332
333namespace AMDGPUAsmVariants {
334 enum : unsigned {
335 DEFAULT = 0,
336 VOP3 = 1,
337 SDWA = 2,
338 SDWA9 = 3,
339 DPP = 4,
340 VOP3_DPP = 5
341 };
342} // namespace AMDGPUAsmVariants
343
344namespace AMDGPU {
345namespace EncValues { // Encoding values of enum9/8/7 operands
346
347enum : unsigned {
348 SGPR_MIN = 0,
349 SGPR_MAX_SI = 101,
350 SGPR_MAX_GFX10 = 105,
351 TTMP_VI_MIN = 112,
352 TTMP_VI_MAX = 123,
353 TTMP_GFX9PLUS_MIN = 108,
354 TTMP_GFX9PLUS_MAX = 123,
355 INLINE_INTEGER_C_MIN = 128,
356 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
357 INLINE_INTEGER_C_MAX = 208,
358 INLINE_FLOATING_C_MIN = 240,
359 INLINE_FLOATING_C_MAX = 248,
360 LITERAL_CONST = 255,
361 VGPR_MIN = 256,
362 VGPR_MAX = 511,
363 IS_VGPR = 256, // Indicates VGPR or AGPR
364};
365
366} // namespace EncValues
367
368// Register codes as defined in the TableGen's HWEncoding field.
369namespace HWEncoding {
370enum : unsigned {
371 REG_IDX_MASK = 0xff,
372 IS_VGPR_OR_AGPR = 1 << 8,
373 IS_HI = 1 << 9, // High 16-bit register.
374};
375} // namespace HWEncoding
376
377namespace CPol {
378
379enum CPol {
380 GLC = 1,
381 SLC = 2,
382 DLC = 4,
383 SCC = 16,
384 SC0 = GLC,
385 SC1 = SCC,
386 NT = SLC,
387 ALL_pregfx12 = GLC | SLC | DLC | SCC,
388 SWZ_pregfx12 = 8,
389
390 // Below are GFX12+ cache policy bits
391
392 // Temporal hint
393 TH = 0x7, // All TH bits
394 TH_RT = 0, // regular
395 TH_NT = 1, // non-temporal
396 TH_HT = 2, // high-temporal
397 TH_LU = 3, // last use
398 TH_RT_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
399 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
400 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
401 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
402 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
403 TH_BYPASS = 3, // only to be used with scope = 3
404
405 TH_RESERVED = 7, // unused value for load insts
406
407 // Bits of TH for atomics
408 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
409 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
410 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
411
412 // Scope
413 SCOPE = 0x3 << 3, // All Scope bits
414 SCOPE_CU = 0 << 3,
415 SCOPE_SE = 1 << 3,
416 SCOPE_DEV = 2 << 3,
417 SCOPE_SYS = 3 << 3,
418
419 SWZ = 1 << 6, // Swizzle bit
420
421 ALL = TH | SCOPE,
422
423 // Helper bits
424 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
425 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
426 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
427 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
428
429 // Volatile (used to preserve/signal operation volatility for buffer
430 // operations not a real instruction bit)
431 VOLATILE = 1 << 31,
432};
433
434} // namespace CPol
435
436namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
437
438enum Id { // Message ID, width(4) [3:0].
439 ID_INTERRUPT = 1,
440
441 ID_GS_PreGFX11 = 2, // replaced in GFX11
442 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
443
444 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
445 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
446
447 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
448 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
449 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
450 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
451 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
452 ID_GS_ALLOC_REQ = 9, // added in GFX9
453 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
454 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
455 ID_SYSMSG = 15,
456
457 ID_RTN_GET_DOORBELL = 128,
458 ID_RTN_GET_DDID = 129,
459 ID_RTN_GET_TMA = 130,
460 ID_RTN_GET_REALTIME = 131,
461 ID_RTN_SAVE_WAVE = 132,
462 ID_RTN_GET_TBA = 133,
463 ID_RTN_GET_TBA_TO_PC = 134,
464 ID_RTN_GET_SE_AID_ID = 135,
465
466 ID_MASK_PreGFX11_ = 0xF,
467 ID_MASK_GFX11Plus_ = 0xFF
468};
469
470enum Op { // Both GS and SYS operation IDs.
471 OP_UNKNOWN_ = -1,
472 OP_SHIFT_ = 4,
473 OP_NONE_ = 0,
474 // Bits used for operation encoding
475 OP_WIDTH_ = 3,
476 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
477 // GS operations are encoded in bits 5:4
478 OP_GS_NOP = 0,
479 OP_GS_CUT = 1,
480 OP_GS_EMIT = 2,
481 OP_GS_EMIT_CUT = 3,
482 OP_GS_LAST_,
483 OP_GS_FIRST_ = OP_GS_NOP,
484 // SYS operations are encoded in bits 6:4
485 OP_SYS_ECC_ERR_INTERRUPT = 1,
486 OP_SYS_REG_RD = 2,
487 OP_SYS_HOST_TRAP_ACK = 3,
488 OP_SYS_TTRACE_PC = 4,
489 OP_SYS_LAST_,
490 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
491};
492
493enum StreamId : unsigned { // Stream ID, (2) [9:8].
494 STREAM_ID_NONE_ = 0,
495 STREAM_ID_DEFAULT_ = 0,
496 STREAM_ID_LAST_ = 4,
497 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
498 STREAM_ID_SHIFT_ = 8,
499 STREAM_ID_WIDTH_= 2,
500 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
501};
502
503} // namespace SendMsg
504
505namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
506
507enum Id { // HwRegCode, (6) [5:0]
508 ID_MODE = 1,
509 ID_STATUS = 2,
510 ID_TRAPSTS = 3,
511 ID_HW_ID = 4,
512 ID_GPR_ALLOC = 5,
513 ID_LDS_ALLOC = 6,
514 ID_IB_STS = 7,
515 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,
516 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,
517 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,
518 ID_MEM_BASES = 15,
519 ID_TBA_LO = 16,
520 ID_TBA_HI = 17,
521 ID_TMA_LO = 18,
522 ID_TMA_HI = 19,
523 ID_FLAT_SCR_LO = 20,
524 ID_FLAT_SCR_HI = 21,
525 ID_XNACK_MASK = 22,
526 ID_HW_ID1 = 23,
527 ID_HW_ID2 = 24,
528 ID_POPS_PACKER = 25,
529 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,
530 ID_SHADER_CYCLES = 29,
531 ID_SHADER_CYCLES_HI = 30,
532 ID_DVGPR_ALLOC_LO = 31,
533 ID_DVGPR_ALLOC_HI = 32,
534
535 // Register numbers reused in GFX11
536 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,
537 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,
538
539 // Register numbers reused in GFX12+
540 ID_STATE_PRIV = 4,
541 ID_PERF_SNAPSHOT_DATA1 = 15,
542 ID_PERF_SNAPSHOT_DATA2 = 16,
543 ID_EXCP_FLAG_PRIV = 17,
544 ID_EXCP_FLAG_USER = 18,
545 ID_TRAP_CTRL = 19,
546
547 // GFX940 specific registers
548 ID_XCC_ID = 20,
549 ID_SQ_PERF_SNAPSHOT_DATA = 21,
550 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
551 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
552 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
553};
554
555enum Offset : unsigned { // Offset, (5) [10:6]
556 OFFSET_MEM_VIOL = 8,
557};
558
559enum ModeRegisterMasks : uint32_t {
560 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
561 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
562 DX10_CLAMP_MASK = 1 << 8,
563 IEEE_MODE_MASK = 1 << 9,
564 LOD_CLAMP_MASK = 1 << 10,
565 DEBUG_MASK = 1 << 11,
566
567 // EXCP_EN fields.
568 EXCP_EN_INVALID_MASK = 1 << 12,
569 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,
570 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,
571 EXCP_EN_OVERFLOW_MASK = 1 << 15,
572 EXCP_EN_UNDERFLOW_MASK = 1 << 16,
573 EXCP_EN_INEXACT_MASK = 1 << 17,
574 EXCP_EN_INT_DIV0_MASK = 1 << 18,
575
576 GPR_IDX_EN_MASK = 1 << 27,
577 VSKIP_MASK = 1 << 28,
578 CSP_MASK = 0x7u << 29 // Bits 29..31
579};
580
581} // namespace Hwreg
582
583namespace MTBUFFormat {
584
585enum DataFormat : int64_t {
586 DFMT_INVALID = 0,
587 DFMT_8,
588 DFMT_16,
589 DFMT_8_8,
590 DFMT_32,
591 DFMT_16_16,
592 DFMT_10_11_11,
593 DFMT_11_11_10,
594 DFMT_10_10_10_2,
595 DFMT_2_10_10_10,
596 DFMT_8_8_8_8,
597 DFMT_32_32,
598 DFMT_16_16_16_16,
599 DFMT_32_32_32,
600 DFMT_32_32_32_32,
601 DFMT_RESERVED_15,
602
603 DFMT_MIN = DFMT_INVALID,
604 DFMT_MAX = DFMT_RESERVED_15,
605
606 DFMT_UNDEF = -1,
607 DFMT_DEFAULT = DFMT_8,
608
609 DFMT_SHIFT = 0,
610 DFMT_MASK = 0xF
611};
612
613enum NumFormat : int64_t {
614 NFMT_UNORM = 0,
615 NFMT_SNORM,
616 NFMT_USCALED,
617 NFMT_SSCALED,
618 NFMT_UINT,
619 NFMT_SINT,
620 NFMT_RESERVED_6, // VI and GFX9
621 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
622 NFMT_FLOAT,
623
624 NFMT_MIN = NFMT_UNORM,
625 NFMT_MAX = NFMT_FLOAT,
626
627 NFMT_UNDEF = -1,
628 NFMT_DEFAULT = NFMT_UNORM,
629
630 NFMT_SHIFT = 4,
631 NFMT_MASK = 7
632};
633
634enum MergedFormat : int64_t {
635 DFMT_NFMT_UNDEF = -1,
636 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |
637 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),
638
639
640 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),
641
642 DFMT_NFMT_MAX = DFMT_NFMT_MASK
643};
644
645enum UnifiedFormatCommon : int64_t {
646 UFMT_MAX = 127,
647 UFMT_UNDEF = -1,
648 UFMT_DEFAULT = 1
649};
650
651} // namespace MTBUFFormat
652
653namespace UfmtGFX10 {
654enum UnifiedFormat : int64_t {
655 UFMT_INVALID = 0,
656
657 UFMT_8_UNORM,
658 UFMT_8_SNORM,
659 UFMT_8_USCALED,
660 UFMT_8_SSCALED,
661 UFMT_8_UINT,
662 UFMT_8_SINT,
663
664 UFMT_16_UNORM,
665 UFMT_16_SNORM,
666 UFMT_16_USCALED,
667 UFMT_16_SSCALED,
668 UFMT_16_UINT,
669 UFMT_16_SINT,
670 UFMT_16_FLOAT,
671
672 UFMT_8_8_UNORM,
673 UFMT_8_8_SNORM,
674 UFMT_8_8_USCALED,
675 UFMT_8_8_SSCALED,
676 UFMT_8_8_UINT,
677 UFMT_8_8_SINT,
678
679 UFMT_32_UINT,
680 UFMT_32_SINT,
681 UFMT_32_FLOAT,
682
683 UFMT_16_16_UNORM,
684 UFMT_16_16_SNORM,
685 UFMT_16_16_USCALED,
686 UFMT_16_16_SSCALED,
687 UFMT_16_16_UINT,
688 UFMT_16_16_SINT,
689 UFMT_16_16_FLOAT,
690
691 UFMT_10_11_11_UNORM,
692 UFMT_10_11_11_SNORM,
693 UFMT_10_11_11_USCALED,
694 UFMT_10_11_11_SSCALED,
695 UFMT_10_11_11_UINT,
696 UFMT_10_11_11_SINT,
697 UFMT_10_11_11_FLOAT,
698
699 UFMT_11_11_10_UNORM,
700 UFMT_11_11_10_SNORM,
701 UFMT_11_11_10_USCALED,
702 UFMT_11_11_10_SSCALED,
703 UFMT_11_11_10_UINT,
704 UFMT_11_11_10_SINT,
705 UFMT_11_11_10_FLOAT,
706
707 UFMT_10_10_10_2_UNORM,
708 UFMT_10_10_10_2_SNORM,
709 UFMT_10_10_10_2_USCALED,
710 UFMT_10_10_10_2_SSCALED,
711 UFMT_10_10_10_2_UINT,
712 UFMT_10_10_10_2_SINT,
713
714 UFMT_2_10_10_10_UNORM,
715 UFMT_2_10_10_10_SNORM,
716 UFMT_2_10_10_10_USCALED,
717 UFMT_2_10_10_10_SSCALED,
718 UFMT_2_10_10_10_UINT,
719 UFMT_2_10_10_10_SINT,
720
721 UFMT_8_8_8_8_UNORM,
722 UFMT_8_8_8_8_SNORM,
723 UFMT_8_8_8_8_USCALED,
724 UFMT_8_8_8_8_SSCALED,
725 UFMT_8_8_8_8_UINT,
726 UFMT_8_8_8_8_SINT,
727
728 UFMT_32_32_UINT,
729 UFMT_32_32_SINT,
730 UFMT_32_32_FLOAT,
731
732 UFMT_16_16_16_16_UNORM,
733 UFMT_16_16_16_16_SNORM,
734 UFMT_16_16_16_16_USCALED,
735 UFMT_16_16_16_16_SSCALED,
736 UFMT_16_16_16_16_UINT,
737 UFMT_16_16_16_16_SINT,
738 UFMT_16_16_16_16_FLOAT,
739
740 UFMT_32_32_32_UINT,
741 UFMT_32_32_32_SINT,
742 UFMT_32_32_32_FLOAT,
743 UFMT_32_32_32_32_UINT,
744 UFMT_32_32_32_32_SINT,
745 UFMT_32_32_32_32_FLOAT,
746
747 UFMT_FIRST = UFMT_INVALID,
748 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
749};
750
751} // namespace UfmtGFX10
752
753namespace UfmtGFX11 {
754enum UnifiedFormat : int64_t {
755 UFMT_INVALID = 0,
756
757 UFMT_8_UNORM,
758 UFMT_8_SNORM,
759 UFMT_8_USCALED,
760 UFMT_8_SSCALED,
761 UFMT_8_UINT,
762 UFMT_8_SINT,
763
764 UFMT_16_UNORM,
765 UFMT_16_SNORM,
766 UFMT_16_USCALED,
767 UFMT_16_SSCALED,
768 UFMT_16_UINT,
769 UFMT_16_SINT,
770 UFMT_16_FLOAT,
771
772 UFMT_8_8_UNORM,
773 UFMT_8_8_SNORM,
774 UFMT_8_8_USCALED,
775 UFMT_8_8_SSCALED,
776 UFMT_8_8_UINT,
777 UFMT_8_8_SINT,
778
779 UFMT_32_UINT,
780 UFMT_32_SINT,
781 UFMT_32_FLOAT,
782
783 UFMT_16_16_UNORM,
784 UFMT_16_16_SNORM,
785 UFMT_16_16_USCALED,
786 UFMT_16_16_SSCALED,
787 UFMT_16_16_UINT,
788 UFMT_16_16_SINT,
789 UFMT_16_16_FLOAT,
790
791 UFMT_10_11_11_FLOAT,
792
793 UFMT_11_11_10_FLOAT,
794
795 UFMT_10_10_10_2_UNORM,
796 UFMT_10_10_10_2_SNORM,
797 UFMT_10_10_10_2_UINT,
798 UFMT_10_10_10_2_SINT,
799
800 UFMT_2_10_10_10_UNORM,
801 UFMT_2_10_10_10_SNORM,
802 UFMT_2_10_10_10_USCALED,
803 UFMT_2_10_10_10_SSCALED,
804 UFMT_2_10_10_10_UINT,
805 UFMT_2_10_10_10_SINT,
806
807 UFMT_8_8_8_8_UNORM,
808 UFMT_8_8_8_8_SNORM,
809 UFMT_8_8_8_8_USCALED,
810 UFMT_8_8_8_8_SSCALED,
811 UFMT_8_8_8_8_UINT,
812 UFMT_8_8_8_8_SINT,
813
814 UFMT_32_32_UINT,
815 UFMT_32_32_SINT,
816 UFMT_32_32_FLOAT,
817
818 UFMT_16_16_16_16_UNORM,
819 UFMT_16_16_16_16_SNORM,
820 UFMT_16_16_16_16_USCALED,
821 UFMT_16_16_16_16_SSCALED,
822 UFMT_16_16_16_16_UINT,
823 UFMT_16_16_16_16_SINT,
824 UFMT_16_16_16_16_FLOAT,
825
826 UFMT_32_32_32_UINT,
827 UFMT_32_32_32_SINT,
828 UFMT_32_32_32_FLOAT,
829 UFMT_32_32_32_32_UINT,
830 UFMT_32_32_32_32_SINT,
831 UFMT_32_32_32_32_FLOAT,
832
833 UFMT_FIRST = UFMT_INVALID,
834 UFMT_LAST = UFMT_32_32_32_32_FLOAT,
835};
836
837} // namespace UfmtGFX11
838
839namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
840
841enum Id : unsigned { // id of symbolic names
842 ID_QUAD_PERM = 0,
843 ID_BITMASK_PERM,
844 ID_SWAP,
845 ID_REVERSE,
846 ID_BROADCAST
847};
848
849enum EncBits : unsigned {
850
851 // swizzle mode encodings
852
853 QUAD_PERM_ENC = 0x8000,
854 QUAD_PERM_ENC_MASK = 0xFF00,
855
856 BITMASK_PERM_ENC = 0x0000,
857 BITMASK_PERM_ENC_MASK = 0x8000,
858
859 // QUAD_PERM encodings
860
861 LANE_MASK = 0x3,
862 LANE_MAX = LANE_MASK,
863 LANE_SHIFT = 2,
864 LANE_NUM = 4,
865
866 // BITMASK_PERM encodings
867
868 BITMASK_MASK = 0x1F,
869 BITMASK_MAX = BITMASK_MASK,
870 BITMASK_WIDTH = 5,
871
872 BITMASK_AND_SHIFT = 0,
873 BITMASK_OR_SHIFT = 5,
874 BITMASK_XOR_SHIFT = 10
875};
876
877} // namespace Swizzle
878
879namespace SDWA {
880
881enum SdwaSel : unsigned {
882 BYTE_0 = 0,
883 BYTE_1 = 1,
884 BYTE_2 = 2,
885 BYTE_3 = 3,
886 WORD_0 = 4,
887 WORD_1 = 5,
888 DWORD = 6,
889};
890
891enum DstUnused : unsigned {
892 UNUSED_PAD = 0,
893 UNUSED_SEXT = 1,
894 UNUSED_PRESERVE = 2,
895};
896
897enum SDWA9EncValues : unsigned {
898 SRC_SGPR_MASK = 0x100,
899 SRC_VGPR_MASK = 0xFF,
900 VOPC_DST_VCC_MASK = 0x80,
901 VOPC_DST_SGPR_MASK = 0x7F,
902
903 SRC_VGPR_MIN = 0,
904 SRC_VGPR_MAX = 255,
905 SRC_SGPR_MIN = 256,
906 SRC_SGPR_MAX_SI = 357,
907 SRC_SGPR_MAX_GFX10 = 361,
908 SRC_TTMP_MIN = 364,
909 SRC_TTMP_MAX = 379,
910};
911
912} // namespace SDWA
913
914namespace DPP {
915
916// clang-format off
917enum DppCtrl : unsigned {
918 QUAD_PERM_FIRST = 0,
919 QUAD_PERM_ID = 0xE4, // identity permutation
920 QUAD_PERM_LAST = 0xFF,
921 DPP_UNUSED1 = 0x100,
922 ROW_SHL0 = 0x100,
923 ROW_SHL_FIRST = 0x101,
924 ROW_SHL_LAST = 0x10F,
925 DPP_UNUSED2 = 0x110,
926 ROW_SHR0 = 0x110,
927 ROW_SHR_FIRST = 0x111,
928 ROW_SHR_LAST = 0x11F,
929 DPP_UNUSED3 = 0x120,
930 ROW_ROR0 = 0x120,
931 ROW_ROR_FIRST = 0x121,
932 ROW_ROR_LAST = 0x12F,
933 WAVE_SHL1 = 0x130,
934 DPP_UNUSED4_FIRST = 0x131,
935 DPP_UNUSED4_LAST = 0x133,
936 WAVE_ROL1 = 0x134,
937 DPP_UNUSED5_FIRST = 0x135,
938 DPP_UNUSED5_LAST = 0x137,
939 WAVE_SHR1 = 0x138,
940 DPP_UNUSED6_FIRST = 0x139,
941 DPP_UNUSED6_LAST = 0x13B,
942 WAVE_ROR1 = 0x13C,
943 DPP_UNUSED7_FIRST = 0x13D,
944 DPP_UNUSED7_LAST = 0x13F,
945 ROW_MIRROR = 0x140,
946 ROW_HALF_MIRROR = 0x141,
947 BCAST15 = 0x142,
948 BCAST31 = 0x143,
949 DPP_UNUSED8_FIRST = 0x144,
950 DPP_UNUSED8_LAST = 0x14F,
951 ROW_NEWBCAST_FIRST= 0x150,
952 ROW_NEWBCAST_LAST = 0x15F,
953 ROW_SHARE0 = 0x150,
954 ROW_SHARE_FIRST = 0x150,
955 ROW_SHARE_LAST = 0x15F,
956 ROW_XMASK0 = 0x160,
957 ROW_XMASK_FIRST = 0x160,
958 ROW_XMASK_LAST = 0x16F,
959 DPP_LAST = ROW_XMASK_LAST
960};
961// clang-format on
962
963enum DppFiMode {
964 DPP_FI_0 = 0,
965 DPP_FI_1 = 1,
966 DPP8_FI_0 = 0xE9,
967 DPP8_FI_1 = 0xEA,
968};
969
970} // namespace DPP
971
972namespace Exp {
973
974enum Target : unsigned {
975 ET_MRT0 = 0,
976 ET_MRT7 = 7,
977 ET_MRTZ = 8,
978 ET_NULL = 9, // Pre-GFX11
979 ET_POS0 = 12,
980 ET_POS3 = 15,
981 ET_POS4 = 16, // GFX10+
982 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
983 ET_PRIM = 20, // GFX10+
984 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
985 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
986 ET_PARAM0 = 32, // Pre-GFX11
987 ET_PARAM31 = 63, // Pre-GFX11
988
989 ET_NULL_MAX_IDX = 0,
990 ET_MRTZ_MAX_IDX = 0,
991 ET_PRIM_MAX_IDX = 0,
992 ET_MRT_MAX_IDX = 7,
993 ET_POS_MAX_IDX = 4,
994 ET_DUAL_SRC_BLEND_MAX_IDX = 1,
995 ET_PARAM_MAX_IDX = 31,
996
997 ET_INVALID = 255,
998};
999
1000} // namespace Exp
1001
1002namespace VOP3PEncoding {
1003
1004enum OpSel : uint64_t {
1005 OP_SEL_HI_0 = UINT64_C(1) << 59,
1006 OP_SEL_HI_1 = UINT64_C(1) << 60,
1007 OP_SEL_HI_2 = UINT64_C(1) << 14,
1008};
1009
1010} // namespace VOP3PEncoding
1011
1012namespace ImplicitArg {
1013// Implicit kernel argument offset for code object version 5.
1014enum Offset_COV5 : unsigned {
1015 HOSTCALL_PTR_OFFSET = 80,
1016 MULTIGRID_SYNC_ARG_OFFSET = 88,
1017 HEAP_PTR_OFFSET = 96,
1018
1019 DEFAULT_QUEUE_OFFSET = 104,
1020 COMPLETION_ACTION_OFFSET = 112,
1021
1022 PRIVATE_BASE_OFFSET = 192,
1023 SHARED_BASE_OFFSET = 196,
1024 QUEUE_PTR_OFFSET = 200,
1025};
1026
1027} // namespace ImplicitArg
1028
1029namespace VirtRegFlag {
1030// Virtual register flags used for various target specific handlings during
1031// codegen.
1032enum Register_Flag : uint8_t {
1033 // Register operand in a whole-wave mode operation.
1034 WWM_REG = 1 << 0,
1035};
1036
1037} // namespace VirtRegFlag
1038
1039} // namespace AMDGPU
1040
1041namespace AMDGPU {
1042namespace Barrier {
1043enum Type { TRAP = -2, WORKGROUP = -1 };
1044} // namespace Barrier
1045} // namespace AMDGPU
1046
1047// clang-format off
1048
1049#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1050#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1051#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1052#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1053#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1054#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1055
1056#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1057#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1058#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1059#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1060#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1061#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1062
1063#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1064#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1065#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1066#define C_00B228_WGP_MODE 0xF7FFFFFF
1067#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1068#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1069#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1070
1071#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1072#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1073#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1074#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1075#define C_00B428_WGP_MODE 0xFBFFFFFF
1076#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1077#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1078#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1079
1080#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1081
1082#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1083#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1084#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1085#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1086#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1087#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1088#define C_00B84C_USER_SGPR 0xFFFFFFC1
1089#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1090#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1091#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1092#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1093#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1094#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1095#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1096#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1097#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1098#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1099#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1100#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1101#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1102#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1103#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1104#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1105#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1106#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1107/* CIK */
1108#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1109#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1110#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1111/* */
1112#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1113#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1114#define C_00B84C_LDS_SIZE 0xFF007FFF
1115#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1116#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1117#define C_00B84C_EXCP_EN
1118
1119#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1120#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1121
1122#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1123#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1124#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1125#define C_00B848_VGPRS 0xFFFFFFC0
1126#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1127#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1128#define C_00B848_SGPRS 0xFFFFFC3F
1129#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1130#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1131#define C_00B848_PRIORITY 0xFFFFF3FF
1132#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1133#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1134#define C_00B848_FLOAT_MODE 0xFFF00FFF
1135#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1136#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1137#define C_00B848_PRIV 0xFFEFFFFF
1138#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1139#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1140#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1141#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1142#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1143#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1144#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1145#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1146#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1147#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1148#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1149#define C_00B848_IEEE_MODE 0xFF7FFFFF
1150#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1151#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1152#define C_00B848_WGP_MODE 0xDFFFFFFF
1153#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1154#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1155#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1156#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1157#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1158#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1159
1160// Helpers for setting FLOAT_MODE
1161#define FP_ROUND_ROUND_TO_NEAREST 0
1162#define FP_ROUND_ROUND_TO_INF 1
1163#define FP_ROUND_ROUND_TO_NEGINF 2
1164#define FP_ROUND_ROUND_TO_ZERO 3
1165
1166// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1167// precision.
1168#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1169#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1170
1171#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1172#define FP_DENORM_FLUSH_OUT 1
1173#define FP_DENORM_FLUSH_IN 2
1174#define FP_DENORM_FLUSH_NONE 3
1175
1176
1177// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1178// precision.
1179#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1180#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1181
1182#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1183#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1184#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1185#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1186
1187#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1188#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1189#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1190#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1191
1192#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1193#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1194#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1195#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1196#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1197#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1198#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1199#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1200
1201#define R_SPILLED_SGPRS 0x4
1202#define R_SPILLED_VGPRS 0x8
1203
1204// clang-format on
1205
1206} // End namespace llvm
1207
1208#endif
1209

source code of llvm/lib/Target/AMDGPU/SIDefines.h