| 1 | //===- OptimizeSharedMemory.cpp - MLIR NVGPU pass implementation ----------===// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file implements transforms to enable 1xtf32 and 3xtf32 nvgpu.mma sync |
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| 10 | // operations on f32 input datatype |
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| 11 | // |
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| 12 | //===----------------------------------------------------------------------===// |
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| 13 | |
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| 14 | #include "mlir/Dialect/NVGPU/Transforms/Transforms.h" |
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| 15 | |
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| 16 | #include "mlir/Dialect/MemRef/IR/MemRef.h" |
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| 17 | #include "mlir/Dialect/NVGPU/IR/NVGPUDialect.h" |
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| 18 | #include "mlir/Dialect/Vector/IR/VectorOps.h" |
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| 19 | |
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| 20 | using namespace mlir; |
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| 21 | using namespace mlir::nvgpu; |
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| 22 | |
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| 23 | namespace { |
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| 24 | |
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| 25 | struct MmaSyncF32ToTF32Pattern : public OpRewritePattern<nvgpu::MmaSyncOp> { |
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| 26 | |
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| 27 | using OpRewritePattern<nvgpu::MmaSyncOp>::OpRewritePattern; |
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| 28 | |
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| 29 | MmaSyncF32ToTF32Pattern(MLIRContext *context, |
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| 30 | nvgpu::MmaSyncF32Lowering precision) |
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| 31 | : OpRewritePattern<nvgpu::MmaSyncOp>(context, /*benifit*/ 1), |
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| 32 | precision(precision) {} |
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| 33 | |
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| 34 | LogicalResult matchAndRewrite(nvgpu::MmaSyncOp op, |
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| 35 | PatternRewriter &rewriter) const override { |
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| 36 | Location location = op->getLoc(); |
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| 37 | |
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| 38 | if (op->hasAttr(name: op.getTf32EnabledAttrName()) || |
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| 39 | !cast<VectorType>(Val: op.getMatrixA().getType()).getElementType().isF32()) |
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| 40 | return failure(); |
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| 41 | |
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| 42 | if (precision == MmaSyncF32Lowering::Unkown) |
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| 43 | return emitError(loc: location, message: "MmaSync F32-to-TF32 cannot be lowered with " |
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| 44 | "unknown precision level" ); |
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| 45 | |
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| 46 | if (precision == MmaSyncF32Lowering::TF32x3) |
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| 47 | return emitError(loc: location, message: "TF32x3 is not supported at the moment " |
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| 48 | "for nvgpu.mma.sync on f32 datatype" ); |
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| 49 | |
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| 50 | if (precision == MmaSyncF32Lowering::TF32) { |
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| 51 | rewriter.modifyOpInPlace( |
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| 52 | root: op, callable: [&]() { op.setTf32EnabledAttr(rewriter.getUnitAttr()); }); |
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| 53 | } |
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| 54 | |
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| 55 | return success(); |
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| 56 | } |
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| 57 | |
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| 58 | private: |
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| 59 | /// Precision for F32 Tensor Cores (TF32 or TF32x3) |
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| 60 | nvgpu::MmaSyncF32Lowering precision; |
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| 61 | }; |
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| 62 | |
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| 63 | } // namespace |
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| 64 | |
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| 65 | void mlir::nvgpu::populateMmaSyncF32ToTF32Patterns( |
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| 66 | RewritePatternSet &patterns, nvgpu::MmaSyncF32Lowering precision) { |
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| 67 | |
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| 68 | patterns.add<MmaSyncF32ToTF32Pattern>(arg: patterns.getContext(), args&: precision); |
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| 69 | } |
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| 70 | |
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