| 1 | // Copyright (C) 2020 The Qt Company Ltd. |
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| 2 | // Copyright (C) 2022 Intel Corporation. |
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| 3 | // SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only |
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| 4 | |
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| 5 | #ifndef QSIMD_H |
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| 6 | #define QSIMD_H |
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| 7 | |
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| 8 | #include <QtCore/qglobal.h> |
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| 9 | |
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| 10 | /* |
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| 11 | * qconfig.h defines the QT_COMPILER_SUPPORTS_XXX macros. |
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| 12 | * They mean the compiler supports the necessary flags and the headers |
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| 13 | * for the x86 and ARM intrinsics. |
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| 14 | * |
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| 15 | * Supported instruction set extensions are: |
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| 16 | * Flag | Arch |
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| 17 | * neon | ARM |
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| 18 | * sve | ARM |
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| 19 | * mips_dsp | mips |
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| 20 | * mips_dspr2 | mips |
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| 21 | * sse2 | x86 |
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| 22 | * sse4_1 | x86 |
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| 23 | * sse4_2 | x86 |
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| 24 | * avx | x86 |
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| 25 | * avx2 | x86 |
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| 26 | * lsx | loongarch |
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| 27 | * lasx | loongarch |
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| 28 | * |
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| 29 | * Code can use the following constructs to determine compiler support & status: |
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| 30 | * - #if QT_COMPILER_USES(XXX) (e.g: #if QT_COMPILER_USES(neon) or QT_COMPILER_USES(sse4_1) |
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| 31 | * If this test passes, then the compiler is already generating code using the |
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| 32 | * given instruction set. The intrinsics for those instructions are |
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| 33 | * #included and can be used without restriction or runtime check. |
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| 34 | * |
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| 35 | * Code that requires runtime detection and different code paths at runtime is |
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| 36 | * currently not supported here, have a look at qsimd_p.h for support. |
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| 37 | */ |
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| 38 | |
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| 39 | #define QT_COMPILER_USES(feature) (1/QT_COMPILER_USES_##feature == 1) |
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| 40 | |
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| 41 | #if defined(Q_PROCESSOR_ARM) && defined(__ARM_NEON) || defined(__ARM_NEON__) || defined(_M_ARM64) |
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| 42 | # include <arm_neon.h> |
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| 43 | # define QT_COMPILER_USES_neon 1 |
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| 44 | #else |
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| 45 | # define QT_COMPILER_USES_neon -1 |
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| 46 | #endif |
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| 47 | |
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| 48 | // To avoid to many untestable fringe cases we so far only support 64bit LE in SVE code |
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| 49 | // The test for QT_COMPILER_SUPPORTS_SVE ensures the intrinsics exists |
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| 50 | #if defined(Q_PROCESSOR_ARM_64) && defined(__ARM_FEATURE_SVE) && defined(Q_LITTLE_ENDIAN) && defined(QT_COMPILER_SUPPORTS_SVE) |
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| 51 | # include <arm_sve.h> |
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| 52 | # define QT_COMPILER_USES_sve 1 |
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| 53 | #else |
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| 54 | # define QT_COMPILER_USES_sve -1 |
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| 55 | #endif |
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| 56 | |
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| 57 | #if defined(Q_PROCESSOR_MIPS) && (defined(__MIPS_DSP__) || (defined(__mips_dsp) && defined(Q_PROCESSOR_MIPS_32))) |
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| 58 | # define QT_COMPILER_USES_mips_dsp 1 |
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| 59 | #else |
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| 60 | # define QT_COMPILER_USES_mips_dsp -1 |
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| 61 | #endif |
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| 62 | |
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| 63 | #if defined(Q_PROCESSOR_MIPS) && (defined(__MIPS_DSPR2__) || (defined(__mips_dspr2) && defined(Q_PROCESSOR_MIPS_32))) |
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| 64 | # define QT_COMPILER_USES_mips_dspr2 1 |
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| 65 | #else |
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| 66 | # define QT_COMPILER_USES_mips_dspr2 -1 |
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| 67 | #endif |
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| 68 | |
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| 69 | #if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_sx) |
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| 70 | # include <lsxintrin.h> |
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| 71 | # define QT_COMPILER_USES_lsx 1 |
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| 72 | #else |
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| 73 | # define QT_COMPILER_USES_lsx -1 |
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| 74 | #endif |
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| 75 | |
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| 76 | #if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_asx) |
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| 77 | # include <lasxintrin.h> |
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| 78 | # define QT_COMPILER_USES_lasx 1 |
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| 79 | #else |
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| 80 | # define QT_COMPILER_USES_lasx -1 |
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| 81 | #endif |
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| 82 | |
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| 83 | #if defined(Q_PROCESSOR_X86) && defined(Q_CC_MSVC) |
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| 84 | // MSVC doesn't define __SSE2__, so do it ourselves |
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| 85 | # if (defined(_M_X64) || _M_IX86_FP >= 2) && defined(QT_COMPILER_SUPPORTS_SSE2) |
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| 86 | # define __SSE__ 1 |
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| 87 | # define __SSE2__ 1 |
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| 88 | # endif |
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| 89 | # if (defined(_M_AVX) || defined(__AVX__)) |
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| 90 | // Visual Studio defines __AVX__ when /arch:AVX is passed, but not the earlier macros |
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| 91 | // See: https://msdn.microsoft.com/en-us/library/b0084kay.aspx |
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| 92 | # define __SSE3__ 1 |
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| 93 | # define __SSSE3__ 1 |
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| 94 | # define __SSE4_1__ 1 |
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| 95 | # define __SSE4_2__ 1 |
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| 96 | # define __POPCNT__ 1 |
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| 97 | # ifndef __AVX__ |
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| 98 | # define __AVX__ 1 |
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| 99 | # endif |
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| 100 | # endif |
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| 101 | # ifdef __SSE2__ |
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| 102 | # define QT_VECTORCALL __vectorcall |
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| 103 | # endif |
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| 104 | # ifdef __AVX2__ |
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| 105 | // MSVC defines __AVX2__ with /arch:AVX2 |
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| 106 | # define __F16C__ 1 |
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| 107 | # define __RDRND__ 1 |
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| 108 | # define __FMA__ 1 |
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| 109 | # define __BMI__ 1 |
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| 110 | # define __BMI2__ 1 |
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| 111 | # define __MOVBE__ 1 |
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| 112 | # define __LZCNT__ 1 |
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| 113 | # endif |
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| 114 | // Starting with /arch:AVX512, MSVC defines all the macros |
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| 115 | #endif |
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| 116 | |
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| 117 | #if defined(Q_PROCESSOR_X86) && defined(__SSE2__) |
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| 118 | # include <immintrin.h> |
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| 119 | # define QT_COMPILER_USES_sse2 1 |
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| 120 | #else |
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| 121 | # define QT_COMPILER_USES_sse2 -1 |
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| 122 | #endif |
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| 123 | |
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| 124 | #if defined(Q_PROCESSOR_X86) && defined(__SSE3__) |
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| 125 | # define QT_COMPILER_USES_sse3 1 |
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| 126 | #else |
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| 127 | # define QT_COMPILER_USES_sse3 -1 |
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| 128 | #endif |
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| 129 | |
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| 130 | #if defined(Q_PROCESSOR_X86) && defined(__SSSE3__) |
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| 131 | # define QT_COMPILER_USES_ssse3 1 |
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| 132 | #else |
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| 133 | # define QT_COMPILER_USES_ssse3 -1 |
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| 134 | #endif |
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| 135 | |
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| 136 | #if defined(Q_PROCESSOR_X86) && defined(__SSE4_1__) |
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| 137 | # define QT_COMPILER_USES_sse4_1 1 |
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| 138 | #else |
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| 139 | # define QT_COMPILER_USES_sse4_1 -1 |
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| 140 | #endif |
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| 141 | |
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| 142 | #if defined(Q_PROCESSOR_X86) && defined(__SSE4_2__) |
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| 143 | # define QT_COMPILER_USES_sse4_2 1 |
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| 144 | #else |
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| 145 | # define QT_COMPILER_USES_sse4_2 -1 |
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| 146 | #endif |
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| 147 | |
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| 148 | #if defined(Q_PROCESSOR_X86) && defined(__AVX__) |
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| 149 | # define QT_COMPILER_USES_avx 1 |
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| 150 | #else |
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| 151 | # define QT_COMPILER_USES_avx -1 |
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| 152 | #endif |
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| 153 | |
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| 154 | #if defined(Q_PROCESSOR_X86) && defined(__AVX2__) |
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| 155 | # define QT_COMPILER_USES_avx2 1 |
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| 156 | #else |
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| 157 | # define QT_COMPILER_USES_avx2 -1 |
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| 158 | #endif |
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| 159 | |
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| 160 | #ifndef QT_VECTORCALL |
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| 161 | #define QT_VECTORCALL |
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| 162 | #endif |
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| 163 | |
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| 164 | QT_BEGIN_NAMESPACE |
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| 165 | QT_END_NAMESPACE |
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| 166 | |
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| 167 | #endif // QSIMD_H |
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| 168 | |
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