1/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
2/*
3 * Performance events:
4 *
5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 *
9 * Data type definitions, declarations, prototypes.
10 *
11 * Started by: Thomas Gleixner and Ingo Molnar
12 *
13 * For licencing details see kernel-base/COPYING
14 */
15#ifndef _UAPI_LINUX_PERF_EVENT_H
16#define _UAPI_LINUX_PERF_EVENT_H
17
18#include <linux/types.h>
19#include <linux/ioctl.h>
20#include <asm/byteorder.h>
21
22/*
23 * User-space ABI bits:
24 */
25
26/*
27 * attr.type
28 */
29enum perf_type_id {
30 PERF_TYPE_HARDWARE = 0,
31 PERF_TYPE_SOFTWARE = 1,
32 PERF_TYPE_TRACEPOINT = 2,
33 PERF_TYPE_HW_CACHE = 3,
34 PERF_TYPE_RAW = 4,
35 PERF_TYPE_BREAKPOINT = 5,
36
37 PERF_TYPE_MAX, /* non-ABI */
38};
39
40/*
41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA
43 * AA: hardware event ID
44 * EEEEEEEE: PMU type ID
45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB
46 * BB: hardware cache ID
47 * CC: hardware cache op ID
48 * DD: hardware cache op result ID
49 * EEEEEEEE: PMU type ID
50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied.
51 */
52#define PERF_PMU_TYPE_SHIFT 32
53#define PERF_HW_EVENT_MASK 0xffffffff
54
55/*
56 * Generalized performance event event_id types, used by the
57 * attr.event_id parameter of the sys_perf_event_open()
58 * syscall:
59 */
60enum perf_hw_id {
61 /*
62 * Common hardware events, generalized by the kernel:
63 */
64 PERF_COUNT_HW_CPU_CYCLES = 0,
65 PERF_COUNT_HW_INSTRUCTIONS = 1,
66 PERF_COUNT_HW_CACHE_REFERENCES = 2,
67 PERF_COUNT_HW_CACHE_MISSES = 3,
68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
69 PERF_COUNT_HW_BRANCH_MISSES = 5,
70 PERF_COUNT_HW_BUS_CYCLES = 6,
71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
73 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
74
75 PERF_COUNT_HW_MAX, /* non-ABI */
76};
77
78/*
79 * Generalized hardware cache events:
80 *
81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
82 * { read, write, prefetch } x
83 * { accesses, misses }
84 */
85enum perf_hw_cache_id {
86 PERF_COUNT_HW_CACHE_L1D = 0,
87 PERF_COUNT_HW_CACHE_L1I = 1,
88 PERF_COUNT_HW_CACHE_LL = 2,
89 PERF_COUNT_HW_CACHE_DTLB = 3,
90 PERF_COUNT_HW_CACHE_ITLB = 4,
91 PERF_COUNT_HW_CACHE_BPU = 5,
92 PERF_COUNT_HW_CACHE_NODE = 6,
93
94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
95};
96
97enum perf_hw_cache_op_id {
98 PERF_COUNT_HW_CACHE_OP_READ = 0,
99 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
101
102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
103};
104
105enum perf_hw_cache_op_result_id {
106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
108
109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
110};
111
112/*
113 * Special "software" events provided by the kernel, even if the hardware
114 * does not support performance events. These events measure various
115 * physical and sw events of the kernel (and allow the profiling of them as
116 * well):
117 */
118enum perf_sw_ids {
119 PERF_COUNT_SW_CPU_CLOCK = 0,
120 PERF_COUNT_SW_TASK_CLOCK = 1,
121 PERF_COUNT_SW_PAGE_FAULTS = 2,
122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
123 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
127 PERF_COUNT_SW_EMULATION_FAULTS = 8,
128 PERF_COUNT_SW_DUMMY = 9,
129 PERF_COUNT_SW_BPF_OUTPUT = 10,
130 PERF_COUNT_SW_CGROUP_SWITCHES = 11,
131
132 PERF_COUNT_SW_MAX, /* non-ABI */
133};
134
135/*
136 * Bits that can be set in attr.sample_type to request information
137 * in the overflow packets.
138 */
139enum perf_event_sample_format {
140 PERF_SAMPLE_IP = 1U << 0,
141 PERF_SAMPLE_TID = 1U << 1,
142 PERF_SAMPLE_TIME = 1U << 2,
143 PERF_SAMPLE_ADDR = 1U << 3,
144 PERF_SAMPLE_READ = 1U << 4,
145 PERF_SAMPLE_CALLCHAIN = 1U << 5,
146 PERF_SAMPLE_ID = 1U << 6,
147 PERF_SAMPLE_CPU = 1U << 7,
148 PERF_SAMPLE_PERIOD = 1U << 8,
149 PERF_SAMPLE_STREAM_ID = 1U << 9,
150 PERF_SAMPLE_RAW = 1U << 10,
151 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
152 PERF_SAMPLE_REGS_USER = 1U << 12,
153 PERF_SAMPLE_STACK_USER = 1U << 13,
154 PERF_SAMPLE_WEIGHT = 1U << 14,
155 PERF_SAMPLE_DATA_SRC = 1U << 15,
156 PERF_SAMPLE_IDENTIFIER = 1U << 16,
157 PERF_SAMPLE_TRANSACTION = 1U << 17,
158 PERF_SAMPLE_REGS_INTR = 1U << 18,
159 PERF_SAMPLE_PHYS_ADDR = 1U << 19,
160 PERF_SAMPLE_AUX = 1U << 20,
161 PERF_SAMPLE_CGROUP = 1U << 21,
162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22,
163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23,
164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24,
165
166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */
167
168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */
169};
170
171#define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT)
172/*
173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
174 *
175 * If the user does not pass priv level information via branch_sample_type,
176 * the kernel uses the event's priv level. Branch and event priv levels do
177 * not have to match. Branch priv level is checked for permissions.
178 *
179 * The branch types can be combined, however BRANCH_ANY covers all types
180 * of branches and therefore it supersedes all the other types.
181 */
182enum perf_branch_sample_type_shift {
183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
186
187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
195
196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
199
200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
202
203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */
204
205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */
206
207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
208};
209
210enum perf_branch_sample_type {
211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
214
215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
223
224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
227
228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
230
231 PERF_SAMPLE_BRANCH_TYPE_SAVE =
232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
233
234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT,
235
236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
237};
238
239/*
240 * Common flow change classification
241 */
242enum {
243 PERF_BR_UNKNOWN = 0, /* unknown */
244 PERF_BR_COND = 1, /* conditional */
245 PERF_BR_UNCOND = 2, /* unconditional */
246 PERF_BR_IND = 3, /* indirect */
247 PERF_BR_CALL = 4, /* function call */
248 PERF_BR_IND_CALL = 5, /* indirect function call */
249 PERF_BR_RET = 6, /* function return */
250 PERF_BR_SYSCALL = 7, /* syscall */
251 PERF_BR_SYSRET = 8, /* syscall return */
252 PERF_BR_COND_CALL = 9, /* conditional function call */
253 PERF_BR_COND_RET = 10, /* conditional function return */
254 PERF_BR_ERET = 11, /* exception return */
255 PERF_BR_IRQ = 12, /* irq */
256 PERF_BR_MAX,
257};
258
259#define PERF_SAMPLE_BRANCH_PLM_ALL \
260 (PERF_SAMPLE_BRANCH_USER|\
261 PERF_SAMPLE_BRANCH_KERNEL|\
262 PERF_SAMPLE_BRANCH_HV)
263
264/*
265 * Values to determine ABI of the registers dump.
266 */
267enum perf_sample_regs_abi {
268 PERF_SAMPLE_REGS_ABI_NONE = 0,
269 PERF_SAMPLE_REGS_ABI_32 = 1,
270 PERF_SAMPLE_REGS_ABI_64 = 2,
271};
272
273/*
274 * Values for the memory transaction event qualifier, mostly for
275 * abort events. Multiple bits can be set.
276 */
277enum {
278 PERF_TXN_ELISION = (1 << 0), /* From elision */
279 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
280 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
281 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
282 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
283 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
284 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
285 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
286
287 PERF_TXN_MAX = (1 << 8), /* non-ABI */
288
289 /* bits 32..63 are reserved for the abort code */
290
291 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
292 PERF_TXN_ABORT_SHIFT = 32,
293};
294
295/*
296 * The format of the data returned by read() on a perf event fd,
297 * as specified by attr.read_format:
298 *
299 * struct read_format {
300 * { u64 value;
301 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
302 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
303 * { u64 id; } && PERF_FORMAT_ID
304 * { u64 lost; } && PERF_FORMAT_LOST
305 * } && !PERF_FORMAT_GROUP
306 *
307 * { u64 nr;
308 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
309 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
310 * { u64 value;
311 * { u64 id; } && PERF_FORMAT_ID
312 * { u64 lost; } && PERF_FORMAT_LOST
313 * } cntr[nr];
314 * } && PERF_FORMAT_GROUP
315 * };
316 */
317enum perf_event_read_format {
318 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
319 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
320 PERF_FORMAT_ID = 1U << 2,
321 PERF_FORMAT_GROUP = 1U << 3,
322 PERF_FORMAT_LOST = 1U << 4,
323
324 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */
325};
326
327#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
328#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
329#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
330#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
331 /* add: sample_stack_user */
332#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
333#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
334#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */
335#define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */
336
337/*
338 * Hardware event_id to monitor via a performance monitoring event:
339 *
340 * @sample_max_stack: Max number of frame pointers in a callchain,
341 * should be < /proc/sys/kernel/perf_event_max_stack
342 */
343struct perf_event_attr {
344
345 /*
346 * Major type: hardware/software/tracepoint/etc.
347 */
348 __u32 type;
349
350 /*
351 * Size of the attr structure, for fwd/bwd compat.
352 */
353 __u32 size;
354
355 /*
356 * Type specific configuration information.
357 */
358 __u64 config;
359
360 union {
361 __u64 sample_period;
362 __u64 sample_freq;
363 };
364
365 __u64 sample_type;
366 __u64 read_format;
367
368 __u64 disabled : 1, /* off by default */
369 inherit : 1, /* children inherit it */
370 pinned : 1, /* must always be on PMU */
371 exclusive : 1, /* only group on PMU */
372 exclude_user : 1, /* don't count user */
373 exclude_kernel : 1, /* ditto kernel */
374 exclude_hv : 1, /* ditto hypervisor */
375 exclude_idle : 1, /* don't count when idle */
376 mmap : 1, /* include mmap data */
377 comm : 1, /* include comm data */
378 freq : 1, /* use freq, not period */
379 inherit_stat : 1, /* per task counts */
380 enable_on_exec : 1, /* next exec enables */
381 task : 1, /* trace fork/exit */
382 watermark : 1, /* wakeup_watermark */
383 /*
384 * precise_ip:
385 *
386 * 0 - SAMPLE_IP can have arbitrary skid
387 * 1 - SAMPLE_IP must have constant skid
388 * 2 - SAMPLE_IP requested to have 0 skid
389 * 3 - SAMPLE_IP must have 0 skid
390 *
391 * See also PERF_RECORD_MISC_EXACT_IP
392 */
393 precise_ip : 2, /* skid constraint */
394 mmap_data : 1, /* non-exec mmap data */
395 sample_id_all : 1, /* sample_type all events */
396
397 exclude_host : 1, /* don't count in host */
398 exclude_guest : 1, /* don't count in guest */
399
400 exclude_callchain_kernel : 1, /* exclude kernel callchains */
401 exclude_callchain_user : 1, /* exclude user callchains */
402 mmap2 : 1, /* include mmap with inode data */
403 comm_exec : 1, /* flag comm events that are due to an exec */
404 use_clockid : 1, /* use @clockid for time fields */
405 context_switch : 1, /* context switch data */
406 write_backward : 1, /* Write ring buffer from end to beginning */
407 namespaces : 1, /* include namespaces data */
408 ksymbol : 1, /* include ksymbol events */
409 bpf_event : 1, /* include bpf events */
410 aux_output : 1, /* generate AUX records instead of events */
411 cgroup : 1, /* include cgroup events */
412 text_poke : 1, /* include text poke events */
413 build_id : 1, /* use build id in mmap2 events */
414 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */
415 remove_on_exec : 1, /* event is removed from task on exec */
416 sigtrap : 1, /* send synchronous SIGTRAP on event */
417 __reserved_1 : 26;
418
419 union {
420 __u32 wakeup_events; /* wakeup every n events */
421 __u32 wakeup_watermark; /* bytes before wakeup */
422 };
423
424 __u32 bp_type;
425 union {
426 __u64 bp_addr;
427 __u64 kprobe_func; /* for perf_kprobe */
428 __u64 uprobe_path; /* for perf_uprobe */
429 __u64 config1; /* extension of config */
430 };
431 union {
432 __u64 bp_len;
433 __u64 kprobe_addr; /* when kprobe_func == NULL */
434 __u64 probe_offset; /* for perf_[k,u]probe */
435 __u64 config2; /* extension of config1 */
436 };
437 __u64 branch_sample_type; /* enum perf_branch_sample_type */
438
439 /*
440 * Defines set of user regs to dump on samples.
441 * See asm/perf_regs.h for details.
442 */
443 __u64 sample_regs_user;
444
445 /*
446 * Defines size of the user stack to dump on samples.
447 */
448 __u32 sample_stack_user;
449
450 __s32 clockid;
451 /*
452 * Defines set of regs to dump for each sample
453 * state captured on:
454 * - precise = 0: PMU interrupt
455 * - precise > 0: sampled instruction
456 *
457 * See asm/perf_regs.h for details.
458 */
459 __u64 sample_regs_intr;
460
461 /*
462 * Wakeup watermark for AUX area
463 */
464 __u32 aux_watermark;
465 __u16 sample_max_stack;
466 __u16 __reserved_2;
467 __u32 aux_sample_size;
468 __u32 __reserved_3;
469
470 /*
471 * User provided data if sigtrap=1, passed back to user via
472 * siginfo_t::si_perf_data, e.g. to permit user to identify the event.
473 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be
474 * truncated accordingly on 32 bit architectures.
475 */
476 __u64 sig_data;
477};
478
479/*
480 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command
481 * to query bpf programs attached to the same perf tracepoint
482 * as the given perf event.
483 */
484struct perf_event_query_bpf {
485 /*
486 * The below ids array length
487 */
488 __u32 ids_len;
489 /*
490 * Set by the kernel to indicate the number of
491 * available programs
492 */
493 __u32 prog_cnt;
494 /*
495 * User provided buffer to store program ids
496 */
497 __u32 ids[];
498};
499
500/*
501 * Ioctls that can be done on a perf event fd:
502 */
503#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
504#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
505#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
506#define PERF_EVENT_IOC_RESET _IO ('$', 3)
507#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
508#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
509#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
510#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
511#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
512#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
513#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *)
514#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *)
515
516enum perf_event_ioc_flags {
517 PERF_IOC_FLAG_GROUP = 1U << 0,
518};
519
520/*
521 * Structure of the page that can be mapped via mmap
522 */
523struct perf_event_mmap_page {
524 __u32 version; /* version number of this structure */
525 __u32 compat_version; /* lowest version this is compat with */
526
527 /*
528 * Bits needed to read the hw events in user-space.
529 *
530 * u32 seq, time_mult, time_shift, index, width;
531 * u64 count, enabled, running;
532 * u64 cyc, time_offset;
533 * s64 pmc = 0;
534 *
535 * do {
536 * seq = pc->lock;
537 * barrier()
538 *
539 * enabled = pc->time_enabled;
540 * running = pc->time_running;
541 *
542 * if (pc->cap_usr_time && enabled != running) {
543 * cyc = rdtsc();
544 * time_offset = pc->time_offset;
545 * time_mult = pc->time_mult;
546 * time_shift = pc->time_shift;
547 * }
548 *
549 * index = pc->index;
550 * count = pc->offset;
551 * if (pc->cap_user_rdpmc && index) {
552 * width = pc->pmc_width;
553 * pmc = rdpmc(index - 1);
554 * }
555 *
556 * barrier();
557 * } while (pc->lock != seq);
558 *
559 * NOTE: for obvious reason this only works on self-monitoring
560 * processes.
561 */
562 __u32 lock; /* seqlock for synchronization */
563 __u32 index; /* hardware event identifier */
564 __s64 offset; /* add to hardware event value */
565 __u64 time_enabled; /* time event active */
566 __u64 time_running; /* time event on cpu */
567 union {
568 __u64 capabilities;
569 struct {
570 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
571 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
572
573 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
574 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */
575 cap_user_time_zero : 1, /* The time_zero field is used */
576 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */
577 cap_____res : 58;
578 };
579 };
580
581 /*
582 * If cap_user_rdpmc this field provides the bit-width of the value
583 * read using the rdpmc() or equivalent instruction. This can be used
584 * to sign extend the result like:
585 *
586 * pmc <<= 64 - width;
587 * pmc >>= 64 - width; // signed shift right
588 * count += pmc;
589 */
590 __u16 pmc_width;
591
592 /*
593 * If cap_usr_time the below fields can be used to compute the time
594 * delta since time_enabled (in ns) using rdtsc or similar.
595 *
596 * u64 quot, rem;
597 * u64 delta;
598 *
599 * quot = (cyc >> time_shift);
600 * rem = cyc & (((u64)1 << time_shift) - 1);
601 * delta = time_offset + quot * time_mult +
602 * ((rem * time_mult) >> time_shift);
603 *
604 * Where time_offset,time_mult,time_shift and cyc are read in the
605 * seqcount loop described above. This delta can then be added to
606 * enabled and possible running (if index), improving the scaling:
607 *
608 * enabled += delta;
609 * if (index)
610 * running += delta;
611 *
612 * quot = count / running;
613 * rem = count % running;
614 * count = quot * enabled + (rem * enabled) / running;
615 */
616 __u16 time_shift;
617 __u32 time_mult;
618 __u64 time_offset;
619 /*
620 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
621 * from sample timestamps.
622 *
623 * time = timestamp - time_zero;
624 * quot = time / time_mult;
625 * rem = time % time_mult;
626 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
627 *
628 * And vice versa:
629 *
630 * quot = cyc >> time_shift;
631 * rem = cyc & (((u64)1 << time_shift) - 1);
632 * timestamp = time_zero + quot * time_mult +
633 * ((rem * time_mult) >> time_shift);
634 */
635 __u64 time_zero;
636
637 __u32 size; /* Header size up to __reserved[] fields. */
638 __u32 __reserved_1;
639
640 /*
641 * If cap_usr_time_short, the hardware clock is less than 64bit wide
642 * and we must compute the 'cyc' value, as used by cap_usr_time, as:
643 *
644 * cyc = time_cycles + ((cyc - time_cycles) & time_mask)
645 *
646 * NOTE: this form is explicitly chosen such that cap_usr_time_short
647 * is a correction on top of cap_usr_time, and code that doesn't
648 * know about cap_usr_time_short still works under the assumption
649 * the counter doesn't wrap.
650 */
651 __u64 time_cycles;
652 __u64 time_mask;
653
654 /*
655 * Hole for extension of the self monitor capabilities
656 */
657
658 __u8 __reserved[116*8]; /* align to 1k. */
659
660 /*
661 * Control data for the mmap() data buffer.
662 *
663 * User-space reading the @data_head value should issue an smp_rmb(),
664 * after reading this value.
665 *
666 * When the mapping is PROT_WRITE the @data_tail value should be
667 * written by userspace to reflect the last read data, after issueing
668 * an smp_mb() to separate the data read from the ->data_tail store.
669 * In this case the kernel will not over-write unread data.
670 *
671 * See perf_output_put_handle() for the data ordering.
672 *
673 * data_{offset,size} indicate the location and size of the perf record
674 * buffer within the mmapped area.
675 */
676 __u64 data_head; /* head in the data section */
677 __u64 data_tail; /* user-space written tail */
678 __u64 data_offset; /* where the buffer starts */
679 __u64 data_size; /* data buffer size */
680
681 /*
682 * AUX area is defined by aux_{offset,size} fields that should be set
683 * by the userspace, so that
684 *
685 * aux_offset >= data_offset + data_size
686 *
687 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
688 *
689 * Ring buffer pointers aux_{head,tail} have the same semantics as
690 * data_{head,tail} and same ordering rules apply.
691 */
692 __u64 aux_head;
693 __u64 aux_tail;
694 __u64 aux_offset;
695 __u64 aux_size;
696};
697
698/*
699 * The current state of perf_event_header::misc bits usage:
700 * ('|' used bit, '-' unused bit)
701 *
702 * 012 CDEF
703 * |||---------||||
704 *
705 * Where:
706 * 0-2 CPUMODE_MASK
707 *
708 * C PROC_MAP_PARSE_TIMEOUT
709 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT
710 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT
711 * F (reserved)
712 */
713
714#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
715#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
716#define PERF_RECORD_MISC_KERNEL (1 << 0)
717#define PERF_RECORD_MISC_USER (2 << 0)
718#define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
719#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
720#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
721
722/*
723 * Indicates that /proc/PID/maps parsing are truncated by time out.
724 */
725#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
726/*
727 * Following PERF_RECORD_MISC_* are used on different
728 * events, so can reuse the same bit position:
729 *
730 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events
731 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event
732 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal)
733 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events
734 */
735#define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
736#define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
737#define PERF_RECORD_MISC_FORK_EXEC (1 << 13)
738#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
739/*
740 * These PERF_RECORD_MISC_* flags below are safely reused
741 * for the following events:
742 *
743 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events
744 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events
745 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event
746 *
747 *
748 * PERF_RECORD_MISC_EXACT_IP:
749 * Indicates that the content of PERF_SAMPLE_IP points to
750 * the actual instruction that triggered the event. See also
751 * perf_event_attr::precise_ip.
752 *
753 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT:
754 * Indicates that thread was preempted in TASK_RUNNING state.
755 *
756 * PERF_RECORD_MISC_MMAP_BUILD_ID:
757 * Indicates that mmap2 event carries build id data.
758 */
759#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
760#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14)
761#define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14)
762/*
763 * Reserve the last bit to indicate some extended misc field
764 */
765#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
766
767struct perf_event_header {
768 __u32 type;
769 __u16 misc;
770 __u16 size;
771};
772
773struct perf_ns_link_info {
774 __u64 dev;
775 __u64 ino;
776};
777
778enum {
779 NET_NS_INDEX = 0,
780 UTS_NS_INDEX = 1,
781 IPC_NS_INDEX = 2,
782 PID_NS_INDEX = 3,
783 USER_NS_INDEX = 4,
784 MNT_NS_INDEX = 5,
785 CGROUP_NS_INDEX = 6,
786
787 NR_NAMESPACES, /* number of available namespaces */
788};
789
790enum perf_event_type {
791
792 /*
793 * If perf_event_attr.sample_id_all is set then all event types will
794 * have the sample_type selected fields related to where/when
795 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
796 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
797 * just after the perf_event_header and the fields already present for
798 * the existing fields, i.e. at the end of the payload. That way a newer
799 * perf.data file will be supported by older perf tools, with these new
800 * optional fields being ignored.
801 *
802 * struct sample_id {
803 * { u32 pid, tid; } && PERF_SAMPLE_TID
804 * { u64 time; } && PERF_SAMPLE_TIME
805 * { u64 id; } && PERF_SAMPLE_ID
806 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
807 * { u32 cpu, res; } && PERF_SAMPLE_CPU
808 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
809 * } && perf_event_attr::sample_id_all
810 *
811 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
812 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
813 * relative to header.size.
814 */
815
816 /*
817 * The MMAP events record the PROT_EXEC mappings so that we can
818 * correlate userspace IPs to code. They have the following structure:
819 *
820 * struct {
821 * struct perf_event_header header;
822 *
823 * u32 pid, tid;
824 * u64 addr;
825 * u64 len;
826 * u64 pgoff;
827 * char filename[];
828 * struct sample_id sample_id;
829 * };
830 */
831 PERF_RECORD_MMAP = 1,
832
833 /*
834 * struct {
835 * struct perf_event_header header;
836 * u64 id;
837 * u64 lost;
838 * struct sample_id sample_id;
839 * };
840 */
841 PERF_RECORD_LOST = 2,
842
843 /*
844 * struct {
845 * struct perf_event_header header;
846 *
847 * u32 pid, tid;
848 * char comm[];
849 * struct sample_id sample_id;
850 * };
851 */
852 PERF_RECORD_COMM = 3,
853
854 /*
855 * struct {
856 * struct perf_event_header header;
857 * u32 pid, ppid;
858 * u32 tid, ptid;
859 * u64 time;
860 * struct sample_id sample_id;
861 * };
862 */
863 PERF_RECORD_EXIT = 4,
864
865 /*
866 * struct {
867 * struct perf_event_header header;
868 * u64 time;
869 * u64 id;
870 * u64 stream_id;
871 * struct sample_id sample_id;
872 * };
873 */
874 PERF_RECORD_THROTTLE = 5,
875 PERF_RECORD_UNTHROTTLE = 6,
876
877 /*
878 * struct {
879 * struct perf_event_header header;
880 * u32 pid, ppid;
881 * u32 tid, ptid;
882 * u64 time;
883 * struct sample_id sample_id;
884 * };
885 */
886 PERF_RECORD_FORK = 7,
887
888 /*
889 * struct {
890 * struct perf_event_header header;
891 * u32 pid, tid;
892 *
893 * struct read_format values;
894 * struct sample_id sample_id;
895 * };
896 */
897 PERF_RECORD_READ = 8,
898
899 /*
900 * struct {
901 * struct perf_event_header header;
902 *
903 * #
904 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
905 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
906 * # is fixed relative to header.
907 * #
908 *
909 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
910 * { u64 ip; } && PERF_SAMPLE_IP
911 * { u32 pid, tid; } && PERF_SAMPLE_TID
912 * { u64 time; } && PERF_SAMPLE_TIME
913 * { u64 addr; } && PERF_SAMPLE_ADDR
914 * { u64 id; } && PERF_SAMPLE_ID
915 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
916 * { u32 cpu, res; } && PERF_SAMPLE_CPU
917 * { u64 period; } && PERF_SAMPLE_PERIOD
918 *
919 * { struct read_format values; } && PERF_SAMPLE_READ
920 *
921 * { u64 nr,
922 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
923 *
924 * #
925 * # The RAW record below is opaque data wrt the ABI
926 * #
927 * # That is, the ABI doesn't make any promises wrt to
928 * # the stability of its content, it may vary depending
929 * # on event, hardware, kernel version and phase of
930 * # the moon.
931 * #
932 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
933 * #
934 *
935 * { u32 size;
936 * char data[size];}&& PERF_SAMPLE_RAW
937 *
938 * { u64 nr;
939 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
940 * { u64 from, to, flags } lbr[nr];
941 * } && PERF_SAMPLE_BRANCH_STACK
942 *
943 * { u64 abi; # enum perf_sample_regs_abi
944 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
945 *
946 * { u64 size;
947 * char data[size];
948 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
949 *
950 * { union perf_sample_weight
951 * {
952 * u64 full; && PERF_SAMPLE_WEIGHT
953 * #if defined(__LITTLE_ENDIAN_BITFIELD)
954 * struct {
955 * u32 var1_dw;
956 * u16 var2_w;
957 * u16 var3_w;
958 * } && PERF_SAMPLE_WEIGHT_STRUCT
959 * #elif defined(__BIG_ENDIAN_BITFIELD)
960 * struct {
961 * u16 var3_w;
962 * u16 var2_w;
963 * u32 var1_dw;
964 * } && PERF_SAMPLE_WEIGHT_STRUCT
965 * #endif
966 * }
967 * }
968 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
969 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
970 * { u64 abi; # enum perf_sample_regs_abi
971 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
972 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR
973 * { u64 size;
974 * char data[size]; } && PERF_SAMPLE_AUX
975 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE
976 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE
977 * };
978 */
979 PERF_RECORD_SAMPLE = 9,
980
981 /*
982 * The MMAP2 records are an augmented version of MMAP, they add
983 * maj, min, ino numbers to be used to uniquely identify each mapping
984 *
985 * struct {
986 * struct perf_event_header header;
987 *
988 * u32 pid, tid;
989 * u64 addr;
990 * u64 len;
991 * u64 pgoff;
992 * union {
993 * struct {
994 * u32 maj;
995 * u32 min;
996 * u64 ino;
997 * u64 ino_generation;
998 * };
999 * struct {
1000 * u8 build_id_size;
1001 * u8 __reserved_1;
1002 * u16 __reserved_2;
1003 * u8 build_id[20];
1004 * };
1005 * };
1006 * u32 prot, flags;
1007 * char filename[];
1008 * struct sample_id sample_id;
1009 * };
1010 */
1011 PERF_RECORD_MMAP2 = 10,
1012
1013 /*
1014 * Records that new data landed in the AUX buffer part.
1015 *
1016 * struct {
1017 * struct perf_event_header header;
1018 *
1019 * u64 aux_offset;
1020 * u64 aux_size;
1021 * u64 flags;
1022 * struct sample_id sample_id;
1023 * };
1024 */
1025 PERF_RECORD_AUX = 11,
1026
1027 /*
1028 * Indicates that instruction trace has started
1029 *
1030 * struct {
1031 * struct perf_event_header header;
1032 * u32 pid;
1033 * u32 tid;
1034 * struct sample_id sample_id;
1035 * };
1036 */
1037 PERF_RECORD_ITRACE_START = 12,
1038
1039 /*
1040 * Records the dropped/lost sample number.
1041 *
1042 * struct {
1043 * struct perf_event_header header;
1044 *
1045 * u64 lost;
1046 * struct sample_id sample_id;
1047 * };
1048 */
1049 PERF_RECORD_LOST_SAMPLES = 13,
1050
1051 /*
1052 * Records a context switch in or out (flagged by
1053 * PERF_RECORD_MISC_SWITCH_OUT). See also
1054 * PERF_RECORD_SWITCH_CPU_WIDE.
1055 *
1056 * struct {
1057 * struct perf_event_header header;
1058 * struct sample_id sample_id;
1059 * };
1060 */
1061 PERF_RECORD_SWITCH = 14,
1062
1063 /*
1064 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
1065 * next_prev_tid that are the next (switching out) or previous
1066 * (switching in) pid/tid.
1067 *
1068 * struct {
1069 * struct perf_event_header header;
1070 * u32 next_prev_pid;
1071 * u32 next_prev_tid;
1072 * struct sample_id sample_id;
1073 * };
1074 */
1075 PERF_RECORD_SWITCH_CPU_WIDE = 15,
1076
1077 /*
1078 * struct {
1079 * struct perf_event_header header;
1080 * u32 pid;
1081 * u32 tid;
1082 * u64 nr_namespaces;
1083 * { u64 dev, inode; } [nr_namespaces];
1084 * struct sample_id sample_id;
1085 * };
1086 */
1087 PERF_RECORD_NAMESPACES = 16,
1088
1089 /*
1090 * Record ksymbol register/unregister events:
1091 *
1092 * struct {
1093 * struct perf_event_header header;
1094 * u64 addr;
1095 * u32 len;
1096 * u16 ksym_type;
1097 * u16 flags;
1098 * char name[];
1099 * struct sample_id sample_id;
1100 * };
1101 */
1102 PERF_RECORD_KSYMBOL = 17,
1103
1104 /*
1105 * Record bpf events:
1106 * enum perf_bpf_event_type {
1107 * PERF_BPF_EVENT_UNKNOWN = 0,
1108 * PERF_BPF_EVENT_PROG_LOAD = 1,
1109 * PERF_BPF_EVENT_PROG_UNLOAD = 2,
1110 * };
1111 *
1112 * struct {
1113 * struct perf_event_header header;
1114 * u16 type;
1115 * u16 flags;
1116 * u32 id;
1117 * u8 tag[BPF_TAG_SIZE];
1118 * struct sample_id sample_id;
1119 * };
1120 */
1121 PERF_RECORD_BPF_EVENT = 18,
1122
1123 /*
1124 * struct {
1125 * struct perf_event_header header;
1126 * u64 id;
1127 * char path[];
1128 * struct sample_id sample_id;
1129 * };
1130 */
1131 PERF_RECORD_CGROUP = 19,
1132
1133 /*
1134 * Records changes to kernel text i.e. self-modified code. 'old_len' is
1135 * the number of old bytes, 'new_len' is the number of new bytes. Either
1136 * 'old_len' or 'new_len' may be zero to indicate, for example, the
1137 * addition or removal of a trampoline. 'bytes' contains the old bytes
1138 * followed immediately by the new bytes.
1139 *
1140 * struct {
1141 * struct perf_event_header header;
1142 * u64 addr;
1143 * u16 old_len;
1144 * u16 new_len;
1145 * u8 bytes[];
1146 * struct sample_id sample_id;
1147 * };
1148 */
1149 PERF_RECORD_TEXT_POKE = 20,
1150
1151 /*
1152 * Data written to the AUX area by hardware due to aux_output, may need
1153 * to be matched to the event by an architecture-specific hardware ID.
1154 * This records the hardware ID, but requires sample_id to provide the
1155 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT
1156 * records from multiple events.
1157 *
1158 * struct {
1159 * struct perf_event_header header;
1160 * u64 hw_id;
1161 * struct sample_id sample_id;
1162 * };
1163 */
1164 PERF_RECORD_AUX_OUTPUT_HW_ID = 21,
1165
1166 PERF_RECORD_MAX, /* non-ABI */
1167};
1168
1169enum perf_record_ksymbol_type {
1170 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,
1171 PERF_RECORD_KSYMBOL_TYPE_BPF = 1,
1172 /*
1173 * Out of line code such as kprobe-replaced instructions or optimized
1174 * kprobes or ftrace trampolines.
1175 */
1176 PERF_RECORD_KSYMBOL_TYPE_OOL = 2,
1177 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */
1178};
1179
1180#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0)
1181
1182enum perf_bpf_event_type {
1183 PERF_BPF_EVENT_UNKNOWN = 0,
1184 PERF_BPF_EVENT_PROG_LOAD = 1,
1185 PERF_BPF_EVENT_PROG_UNLOAD = 2,
1186 PERF_BPF_EVENT_MAX, /* non-ABI */
1187};
1188
1189#define PERF_MAX_STACK_DEPTH 127
1190#define PERF_MAX_CONTEXTS_PER_STACK 8
1191
1192enum perf_callchain_context {
1193 PERF_CONTEXT_HV = (__u64)-32,
1194 PERF_CONTEXT_KERNEL = (__u64)-128,
1195 PERF_CONTEXT_USER = (__u64)-512,
1196
1197 PERF_CONTEXT_GUEST = (__u64)-2048,
1198 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
1199 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
1200
1201 PERF_CONTEXT_MAX = (__u64)-4095,
1202};
1203
1204/**
1205 * PERF_RECORD_AUX::flags bits
1206 */
1207#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
1208#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
1209#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
1210#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
1211#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */
1212
1213/* CoreSight PMU AUX buffer formats */
1214#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
1215#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */
1216
1217#define PERF_FLAG_FD_NO_GROUP (1UL << 0)
1218#define PERF_FLAG_FD_OUTPUT (1UL << 1)
1219#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
1220#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
1221
1222#if defined(__LITTLE_ENDIAN_BITFIELD)
1223union perf_mem_data_src {
1224 __u64 val;
1225 struct {
1226 __u64 mem_op:5, /* type of opcode */
1227 mem_lvl:14, /* memory hierarchy level */
1228 mem_snoop:5, /* snoop mode */
1229 mem_lock:2, /* lock instr */
1230 mem_dtlb:7, /* tlb access */
1231 mem_lvl_num:4, /* memory hierarchy level number */
1232 mem_remote:1, /* remote */
1233 mem_snoopx:2, /* snoop mode, ext */
1234 mem_blk:3, /* access blocked */
1235 mem_hops:3, /* hop level */
1236 mem_rsvd:18;
1237 };
1238};
1239#elif defined(__BIG_ENDIAN_BITFIELD)
1240union perf_mem_data_src {
1241 __u64 val;
1242 struct {
1243 __u64 mem_rsvd:18,
1244 mem_hops:3, /* hop level */
1245 mem_blk:3, /* access blocked */
1246 mem_snoopx:2, /* snoop mode, ext */
1247 mem_remote:1, /* remote */
1248 mem_lvl_num:4, /* memory hierarchy level number */
1249 mem_dtlb:7, /* tlb access */
1250 mem_lock:2, /* lock instr */
1251 mem_snoop:5, /* snoop mode */
1252 mem_lvl:14, /* memory hierarchy level */
1253 mem_op:5; /* type of opcode */
1254 };
1255};
1256#else
1257#error "Unknown endianness"
1258#endif
1259
1260/* type of opcode (load/store/prefetch,code) */
1261#define PERF_MEM_OP_NA 0x01 /* not available */
1262#define PERF_MEM_OP_LOAD 0x02 /* load instruction */
1263#define PERF_MEM_OP_STORE 0x04 /* store instruction */
1264#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
1265#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
1266#define PERF_MEM_OP_SHIFT 0
1267
1268/*
1269 * PERF_MEM_LVL_* namespace being depricated to some extent in the
1270 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields.
1271 * Supporting this namespace inorder to not break defined ABIs.
1272 *
1273 * memory hierarchy (memory level, hit or miss)
1274 */
1275#define PERF_MEM_LVL_NA 0x01 /* not available */
1276#define PERF_MEM_LVL_HIT 0x02 /* hit level */
1277#define PERF_MEM_LVL_MISS 0x04 /* miss level */
1278#define PERF_MEM_LVL_L1 0x08 /* L1 */
1279#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
1280#define PERF_MEM_LVL_L2 0x20 /* L2 */
1281#define PERF_MEM_LVL_L3 0x40 /* L3 */
1282#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
1283#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
1284#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
1285#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
1286#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
1287#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1288#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1289#define PERF_MEM_LVL_SHIFT 5
1290
1291#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */
1292#define PERF_MEM_REMOTE_SHIFT 37
1293
1294#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */
1295#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
1296#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1297#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1298/* 5-0xa available */
1299#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1300#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
1301#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
1302#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */
1303#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */
1304
1305#define PERF_MEM_LVLNUM_SHIFT 33
1306
1307/* snoop mode */
1308#define PERF_MEM_SNOOP_NA 0x01 /* not available */
1309#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
1310#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
1311#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
1312#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
1313#define PERF_MEM_SNOOP_SHIFT 19
1314
1315#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */
1316/* 1 free */
1317#define PERF_MEM_SNOOPX_SHIFT 38
1318
1319/* locked instruction */
1320#define PERF_MEM_LOCK_NA 0x01 /* not available */
1321#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
1322#define PERF_MEM_LOCK_SHIFT 24
1323
1324/* TLB access */
1325#define PERF_MEM_TLB_NA 0x01 /* not available */
1326#define PERF_MEM_TLB_HIT 0x02 /* hit level */
1327#define PERF_MEM_TLB_MISS 0x04 /* miss level */
1328#define PERF_MEM_TLB_L1 0x08 /* L1 */
1329#define PERF_MEM_TLB_L2 0x10 /* L2 */
1330#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
1331#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
1332#define PERF_MEM_TLB_SHIFT 26
1333
1334/* Access blocked */
1335#define PERF_MEM_BLK_NA 0x01 /* not available */
1336#define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */
1337#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */
1338#define PERF_MEM_BLK_SHIFT 40
1339
1340/* hop level */
1341#define PERF_MEM_HOPS_0 0x01 /* remote core, same node */
1342#define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */
1343#define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */
1344#define PERF_MEM_HOPS_3 0x04 /* remote board */
1345/* 5-7 available */
1346#define PERF_MEM_HOPS_SHIFT 43
1347
1348#define PERF_MEM_S(a, s) \
1349 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1350
1351/*
1352 * single taken branch record layout:
1353 *
1354 * from: source instruction (may not always be a branch insn)
1355 * to: branch target
1356 * mispred: branch target was mispredicted
1357 * predicted: branch target was predicted
1358 *
1359 * support for mispred, predicted is optional. In case it
1360 * is not supported mispred = predicted = 0.
1361 *
1362 * in_tx: running in a hardware transaction
1363 * abort: aborting a hardware transaction
1364 * cycles: cycles from last branch (or 0 if not supported)
1365 * type: branch type
1366 */
1367struct perf_branch_entry {
1368 __u64 from;
1369 __u64 to;
1370 __u64 mispred:1, /* target mispredicted */
1371 predicted:1,/* target predicted */
1372 in_tx:1, /* in transaction */
1373 abort:1, /* transaction abort */
1374 cycles:16, /* cycle count to last branch */
1375 type:4, /* branch type */
1376 reserved:40;
1377};
1378
1379union perf_sample_weight {
1380 __u64 full;
1381#if defined(__LITTLE_ENDIAN_BITFIELD)
1382 struct {
1383 __u32 var1_dw;
1384 __u16 var2_w;
1385 __u16 var3_w;
1386 };
1387#elif defined(__BIG_ENDIAN_BITFIELD)
1388 struct {
1389 __u16 var3_w;
1390 __u16 var2_w;
1391 __u32 var1_dw;
1392 };
1393#else
1394#error "Unknown endianness"
1395#endif
1396};
1397
1398#endif /* _UAPI_LINUX_PERF_EVENT_H */
1399

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source code of qtbase/src/testlib/3rdparty/linux/perf_event_p.h