1use crate::common::Register;
2
3macro_rules! registers {
4 ($struct_name:ident, { $($name:ident = ($val:expr, $disp:expr)),+ $(,)? }
5 $(, aliases { $($alias_name:ident = ($alias_val:expr, $alias_disp:expr)),+ $(,)? })?) => {
6 #[allow(missing_docs)]
7 impl $struct_name {
8 $(
9 pub const $name: Register = Register($val);
10 )+
11 $(
12 $(pub const $alias_name: Register = Register($alias_val);)+
13 )*
14 }
15
16 impl $struct_name {
17 /// The name of a register, or `None` if the register number is unknown.
18 ///
19 /// Only returns the primary name for registers that alias with others.
20 pub fn register_name(register: Register) -> Option<&'static str> {
21 match register {
22 $(
23 Self::$name => Some($disp),
24 )+
25 _ => return None,
26 }
27 }
28
29 /// Converts a register name into a register number.
30 pub fn name_to_register(value: &str) -> Option<Register> {
31 match value {
32 $(
33 $disp => Some(Self::$name),
34 )+
35 $(
36 $($alias_disp => Some(Self::$alias_name),)+
37 )*
38 _ => return None,
39 }
40 }
41 }
42 };
43}
44
45/// ARM architecture specific definitions.
46///
47/// See [DWARF for the ARM Architecture](
48/// https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst).
49#[derive(Debug, Clone, Copy)]
50pub struct Arm;
51
52registers!(Arm, {
53 R0 = (0, "R0"),
54 R1 = (1, "R1"),
55 R2 = (2, "R2"),
56 R3 = (3, "R3"),
57 R4 = (4, "R4"),
58 R5 = (5, "R5"),
59 R6 = (6, "R6"),
60 R7 = (7, "R7"),
61 R8 = (8, "R8"),
62 R9 = (9, "R9"),
63 R10 = (10, "R10"),
64 R11 = (11, "R11"),
65 R12 = (12, "R12"),
66 R13 = (13, "R13"),
67 R14 = (14, "R14"),
68 R15 = (15, "R15"),
69
70 WCGR0 = (104, "wCGR0"),
71 WCGR1 = (105, "wCGR1"),
72 WCGR2 = (106, "wCGR2"),
73 WCGR3 = (107, "wCGR3"),
74 WCGR4 = (108, "wCGR4"),
75 WCGR5 = (109, "wCGR5"),
76 WCGR6 = (110, "wCGR6"),
77 WCGR7 = (111, "wCGR7"),
78
79 WR0 = (112, "wR0"),
80 WR1 = (113, "wR1"),
81 WR2 = (114, "wR2"),
82 WR3 = (115, "wR3"),
83 WR4 = (116, "wR4"),
84 WR5 = (117, "wR5"),
85 WR6 = (118, "wR6"),
86 WR7 = (119, "wR7"),
87 WR8 = (120, "wR8"),
88 WR9 = (121, "wR9"),
89 WR10 = (122, "wR10"),
90 WR11 = (123, "wR11"),
91 WR12 = (124, "wR12"),
92 WR13 = (125, "wR13"),
93 WR14 = (126, "wR14"),
94 WR15 = (127, "wR15"),
95
96 SPSR = (128, "SPSR"),
97 SPSR_FIQ = (129, "SPSR_FIQ"),
98 SPSR_IRQ = (130, "SPSR_IRQ"),
99 SPSR_ABT = (131, "SPSR_ABT"),
100 SPSR_UND = (132, "SPSR_UND"),
101 SPSR_SVC = (133, "SPSR_SVC"),
102
103 RA_AUTH_CODE = (143, "RA_AUTH_CODE"),
104
105 R8_USR = (144, "R8_USR"),
106 R9_USR = (145, "R9_USR"),
107 R10_USR = (146, "R10_USR"),
108 R11_USR = (147, "R11_USR"),
109 R12_USR = (148, "R12_USR"),
110 R13_USR = (149, "R13_USR"),
111 R14_USR = (150, "R14_USR"),
112
113 R8_FIQ = (151, "R8_FIQ"),
114 R9_FIQ = (152, "R9_FIQ"),
115 R10_FIQ = (153, "R10_FIQ"),
116 R11_FIQ = (154, "R11_FIQ"),
117 R12_FIQ = (155, "R12_FIQ"),
118 R13_FIQ = (156, "R13_FIQ"),
119 R14_FIQ = (157, "R14_FIQ"),
120
121 R13_IRQ = (158, "R13_IRQ"),
122 R14_IRQ = (159, "R14_IRQ"),
123
124 R13_ABT = (160, "R13_ABT"),
125 R14_ABT = (161, "R14_ABT"),
126
127 R13_UND = (162, "R13_UND"),
128 R14_UND = (163, "R14_UND"),
129
130 R13_SVC = (164, "R13_SVC"),
131 R14_SVC = (165, "R14_SVC"),
132
133 WC0 = (192, "wC0"),
134 WC1 = (193, "wC1"),
135 WC2 = (194, "wC2"),
136 WC3 = (195, "wC3"),
137 WC4 = (196, "wC4"),
138 WC5 = (197, "wC5"),
139 WC6 = (198, "wC6"),
140 WC7 = (199, "wC7"),
141
142 D0 = (256, "D0"),
143 D1 = (257, "D1"),
144 D2 = (258, "D2"),
145 D3 = (259, "D3"),
146 D4 = (260, "D4"),
147 D5 = (261, "D5"),
148 D6 = (262, "D6"),
149 D7 = (263, "D7"),
150 D8 = (264, "D8"),
151 D9 = (265, "D9"),
152 D10 = (266, "D10"),
153 D11 = (267, "D11"),
154 D12 = (268, "D12"),
155 D13 = (269, "D13"),
156 D14 = (270, "D14"),
157 D15 = (271, "D15"),
158 D16 = (272, "D16"),
159 D17 = (273, "D17"),
160 D18 = (274, "D18"),
161 D19 = (275, "D19"),
162 D20 = (276, "D20"),
163 D21 = (277, "D21"),
164 D22 = (278, "D22"),
165 D23 = (279, "D23"),
166 D24 = (280, "D24"),
167 D25 = (281, "D25"),
168 D26 = (282, "D26"),
169 D27 = (283, "D27"),
170 D28 = (284, "D28"),
171 D29 = (285, "D29"),
172 D30 = (286, "D30"),
173 D31 = (287, "D31"),
174
175 TPIDRURO = (320, "TPIDRURO"),
176 TPIDRURW = (321, "TPIDRURW"),
177 TPIDPR = (322, "TPIDPR"),
178 HTPIDPR = (323, "HTPIDPR"),
179},
180aliases {
181 SP = (13, "SP"),
182 LR = (14, "LR"),
183 PC = (15, "PC"),
184
185 ACC0 = (104, "ACC0"),
186 ACC1 = (105, "ACC1"),
187 ACC2 = (106, "ACC2"),
188 ACC3 = (107, "ACC3"),
189 ACC4 = (108, "ACC4"),
190 ACC5 = (109, "ACC5"),
191 ACC6 = (110, "ACC6"),
192 ACC7 = (111, "ACC7"),
193
194 S0 = (256, "S0"),
195 S1 = (256, "S1"),
196 S2 = (257, "S2"),
197 S3 = (257, "S3"),
198 S4 = (258, "S4"),
199 S5 = (258, "S5"),
200 S6 = (259, "S6"),
201 S7 = (259, "S7"),
202 S8 = (260, "S8"),
203 S9 = (260, "S9"),
204 S10 = (261, "S10"),
205 S11 = (261, "S11"),
206 S12 = (262, "S12"),
207 S13 = (262, "S13"),
208 S14 = (263, "S14"),
209 S15 = (263, "S15"),
210 S16 = (264, "S16"),
211 S17 = (264, "S17"),
212 S18 = (265, "S18"),
213 S19 = (265, "S19"),
214 S20 = (266, "S20"),
215 S21 = (266, "S21"),
216 S22 = (267, "S22"),
217 S23 = (267, "S23"),
218 S24 = (268, "S24"),
219 S25 = (268, "S25"),
220 S26 = (269, "S26"),
221 S27 = (269, "S27"),
222 S28 = (270, "S28"),
223 S29 = (270, "S29"),
224 S30 = (271, "S30"),
225 S31 = (271, "S31"),
226});
227
228/// ARM 64-bit (AArch64) architecture specific definitions.
229///
230/// See [DWARF for the ARM 64-bit Architecture](
231/// https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst).
232#[derive(Debug, Clone, Copy)]
233pub struct AArch64;
234
235registers!(AArch64, {
236 X0 = (0, "X0"),
237 X1 = (1, "X1"),
238 X2 = (2, "X2"),
239 X3 = (3, "X3"),
240 X4 = (4, "X4"),
241 X5 = (5, "X5"),
242 X6 = (6, "X6"),
243 X7 = (7, "X7"),
244 X8 = (8, "X8"),
245 X9 = (9, "X9"),
246 X10 = (10, "X10"),
247 X11 = (11, "X11"),
248 X12 = (12, "X12"),
249 X13 = (13, "X13"),
250 X14 = (14, "X14"),
251 X15 = (15, "X15"),
252 X16 = (16, "X16"),
253 X17 = (17, "X17"),
254 X18 = (18, "X18"),
255 X19 = (19, "X19"),
256 X20 = (20, "X20"),
257 X21 = (21, "X21"),
258 X22 = (22, "X22"),
259 X23 = (23, "X23"),
260 X24 = (24, "X24"),
261 X25 = (25, "X25"),
262 X26 = (26, "X26"),
263 X27 = (27, "X27"),
264 X28 = (28, "X28"),
265 X29 = (29, "X29"),
266 X30 = (30, "X30"),
267 SP = (31, "SP"),
268 PC = (32, "PC"),
269 ELR_MODE = (33, "ELR_mode"),
270 RA_SIGN_STATE = (34, "RA_SIGN_STATE"),
271 TPIDRRO_EL0 = (35, "TPIDRRO_EL0"),
272 TPIDR_EL0 = (36, "TPIDR_EL0"),
273 TPIDR_EL1 = (37, "TPIDR_EL1"),
274 TPIDR_EL2 = (38, "TPIDR_EL2"),
275 TPIDR_EL3 = (39, "TPIDR_EL3"),
276
277 V0 = (64, "V0"),
278 V1 = (65, "V1"),
279 V2 = (66, "V2"),
280 V3 = (67, "V3"),
281 V4 = (68, "V4"),
282 V5 = (69, "V5"),
283 V6 = (70, "V6"),
284 V7 = (71, "V7"),
285 V8 = (72, "V8"),
286 V9 = (73, "V9"),
287 V10 = (74, "V10"),
288 V11 = (75, "V11"),
289 V12 = (76, "V12"),
290 V13 = (77, "V13"),
291 V14 = (78, "V14"),
292 V15 = (79, "V15"),
293 V16 = (80, "V16"),
294 V17 = (81, "V17"),
295 V18 = (82, "V18"),
296 V19 = (83, "V19"),
297 V20 = (84, "V20"),
298 V21 = (85, "V21"),
299 V22 = (86, "V22"),
300 V23 = (87, "V23"),
301 V24 = (88, "V24"),
302 V25 = (89, "V25"),
303 V26 = (90, "V26"),
304 V27 = (91, "V27"),
305 V28 = (92, "V28"),
306 V29 = (93, "V29"),
307 V30 = (94, "V30"),
308 V31 = (95, "V31"),
309});
310
311/// LoongArch architecture specific definitions.
312///
313/// See [LoongArch ELF psABI specification](https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html).
314#[derive(Debug, Clone, Copy)]
315pub struct LoongArch;
316
317registers!(LoongArch, {
318 R0 = (0, "$r0"),
319 R1 = (1, "$r1"),
320 R2 = (2, "$r2"),
321 R3 = (3, "$r3"),
322 R4 = (4, "$r4"),
323 R5 = (5, "$r5"),
324 R6 = (6, "$r6"),
325 R7 = (7, "$r7"),
326 R8 = (8, "$r8"),
327 R9 = (9, "$r9"),
328 R10 = (10, "$r10"),
329 R11 = (11, "$r11"),
330 R12 = (12, "$r12"),
331 R13 = (13, "$r13"),
332 R14 = (14, "$r14"),
333 R15 = (15, "$r15"),
334 R16 = (16, "$r16"),
335 R17 = (17, "$r17"),
336 R18 = (18, "$r18"),
337 R19 = (19, "$r19"),
338 R20 = (20, "$r20"),
339 R21 = (21, "$r21"),
340 R22 = (22, "$r22"),
341 R23 = (23, "$r23"),
342 R24 = (24, "$r24"),
343 R25 = (25, "$r25"),
344 R26 = (26, "$r26"),
345 R27 = (27, "$r27"),
346 R28 = (28, "$r28"),
347 R29 = (29, "$r29"),
348 R30 = (30, "$r30"),
349 R31 = (31, "$r31"),
350
351 F0 = (32, "$f0"),
352 F1 = (33, "$f1"),
353 F2 = (34, "$f2"),
354 F3 = (35, "$f3"),
355 F4 = (36, "$f4"),
356 F5 = (37, "$f5"),
357 F6 = (38, "$f6"),
358 F7 = (39, "$f7"),
359 F8 = (40, "$f8"),
360 F9 = (41, "$f9"),
361 F10 = (42, "$f10"),
362 F11 = (43, "$f11"),
363 F12 = (44, "$f12"),
364 F13 = (45, "$f13"),
365 F14 = (46, "$f14"),
366 F15 = (47, "$f15"),
367 F16 = (48, "$f16"),
368 F17 = (49, "$f17"),
369 F18 = (50, "$f18"),
370 F19 = (51, "$f19"),
371 F20 = (52, "$f20"),
372 F21 = (53, "$f21"),
373 F22 = (54, "$f22"),
374 F23 = (55, "$f23"),
375 F24 = (56, "$f24"),
376 F25 = (57, "$f25"),
377 F26 = (58, "$f26"),
378 F27 = (59, "$f27"),
379 F28 = (60, "$f28"),
380 F29 = (61, "$f29"),
381 F30 = (62, "$f30"),
382 F31 = (63, "$f31"),
383 FCC0 = (64, "$fcc0"),
384 FCC1 = (65, "$fcc1"),
385 FCC2 = (66, "$fcc2"),
386 FCC3 = (67, "$fcc3"),
387 FCC4 = (68, "$fcc4"),
388 FCC5 = (69, "$fcc5"),
389 FCC6 = (70, "$fcc6"),
390 FCC7 = (71, "$fcc7"),
391},
392aliases {
393 ZERO = (0, "$zero"),
394 RA = (1, "$ra"),
395 TP = (2, "$tp"),
396 SP = (3, "$sp"),
397 A0 = (4, "$a0"),
398 A1 = (5, "$a1"),
399 A2 = (6, "$a2"),
400 A3 = (7, "$a3"),
401 A4 = (8, "$a4"),
402 A5 = (9, "$a5"),
403 A6 = (10, "$a6"),
404 A7 = (11, "$a7"),
405 T0 = (12, "$t0"),
406 T1 = (13, "$t1"),
407 T2 = (14, "$t2"),
408 T3 = (15, "$t3"),
409 T4 = (16, "$t4"),
410 T5 = (17, "$t5"),
411 T6 = (18, "$t6"),
412 T7 = (19, "$t7"),
413 T8 = (20, "$t8"),
414 FP = (22, "$fp"),
415 S0 = (23, "$s0"),
416 S1 = (24, "$s1"),
417 S2 = (25, "$s2"),
418 S3 = (26, "$s3"),
419 S4 = (27, "$s4"),
420 S5 = (28, "$s5"),
421 S6 = (29, "$s6"),
422 S7 = (30, "$s7"),
423 S8 = (31, "$s8"),
424
425 FA0 = (32, "$fa0"),
426 FA1 = (33, "$fa1"),
427 FA2 = (34, "$fa2"),
428 FA3 = (35, "$fa3"),
429 FA4 = (36, "$fa4"),
430 FA5 = (37, "$fa5"),
431 FA6 = (38, "$fa6"),
432 FA7 = (39, "$fa7"),
433 FT0 = (40, "$ft0"),
434 FT1 = (41, "$ft1"),
435 FT2 = (42, "$ft2"),
436 FT3 = (43, "$ft3"),
437 FT4 = (44, "$ft4"),
438 FT5 = (45, "$ft5"),
439 FT6 = (46, "$ft6"),
440 FT7 = (47, "$ft7"),
441 FT8 = (48, "$ft8"),
442 FT9 = (49, "$ft9"),
443 FT10 = (50, "$ft10"),
444 FT11 = (51, "$ft11"),
445 FT12 = (52, "$ft12"),
446 FT13 = (53, "$ft13"),
447 FT14 = (54, "$ft14"),
448 FT15 = (55, "$ft15"),
449 FS0 = (56, "$fs0"),
450 FS1 = (57, "$fs1"),
451 FS2 = (58, "$fs2"),
452 FS3 = (59, "$fs3"),
453 FS4 = (60, "$fs4"),
454 FS5 = (61, "$fs5"),
455 FS6 = (62, "$fs6"),
456 FS7 = (63, "$fs7"),
457});
458
459/// RISC-V architecture specific definitions.
460///
461/// See [RISC-V ELF psABI specification](https://github.com/riscv/riscv-elf-psabi-doc).
462#[derive(Debug, Clone, Copy)]
463pub struct RiscV;
464
465registers!(RiscV, {
466 X0 = (0, "x0"),
467 X1 = (1, "x1"),
468 X2 = (2, "x2"),
469 X3 = (3, "x3"),
470 X4 = (4, "x4"),
471 X5 = (5, "x5"),
472 X6 = (6, "x6"),
473 X7 = (7, "x7"),
474 X8 = (8, "x8"),
475 X9 = (9, "x9"),
476 X10 = (10, "x10"),
477 X11 = (11, "x11"),
478 X12 = (12, "x12"),
479 X13 = (13, "x13"),
480 X14 = (14, "x14"),
481 X15 = (15, "x15"),
482 X16 = (16, "x16"),
483 X17 = (17, "x17"),
484 X18 = (18, "x18"),
485 X19 = (19, "x19"),
486 X20 = (20, "x20"),
487 X21 = (21, "x21"),
488 X22 = (22, "x22"),
489 X23 = (23, "x23"),
490 X24 = (24, "x24"),
491 X25 = (25, "x25"),
492 X26 = (26, "x26"),
493 X27 = (27, "x27"),
494 X28 = (28, "x28"),
495 X29 = (29, "x29"),
496 X30 = (30, "x30"),
497 X31 = (31, "x31"),
498
499 F0 = (32, "f0"),
500 F1 = (33, "f1"),
501 F2 = (34, "f2"),
502 F3 = (35, "f3"),
503 F4 = (36, "f4"),
504 F5 = (37, "f5"),
505 F6 = (38, "f6"),
506 F7 = (39, "f7"),
507 F8 = (40, "f8"),
508 F9 = (41, "f9"),
509 F10 = (42, "f10"),
510 F11 = (43, "f11"),
511 F12 = (44, "f12"),
512 F13 = (45, "f13"),
513 F14 = (46, "f14"),
514 F15 = (47, "f15"),
515 F16 = (48, "f16"),
516 F17 = (49, "f17"),
517 F18 = (50, "f18"),
518 F19 = (51, "f19"),
519 F20 = (52, "f20"),
520 F21 = (53, "f21"),
521 F22 = (54, "f22"),
522 F23 = (55, "f23"),
523 F24 = (56, "f24"),
524 F25 = (57, "f25"),
525 F26 = (58, "f26"),
526 F27 = (59, "f27"),
527 F28 = (60, "f28"),
528 F29 = (61, "f29"),
529 F30 = (62, "f30"),
530 F31 = (63, "f31"),
531},
532aliases {
533 ZERO = (0, "zero"),
534 RA = (1, "ra"),
535 SP = (2, "sp"),
536 GP = (3, "gp"),
537 TP = (4, "tp"),
538 T0 = (5, "t0"),
539 T1 = (6, "t1"),
540 T2 = (7, "t2"),
541 S0 = (8, "s0"),
542 S1 = (9, "s1"),
543 A0 = (10, "a0"),
544 A1 = (11, "a1"),
545 A2 = (12, "a2"),
546 A3 = (13, "a3"),
547 A4 = (14, "a4"),
548 A5 = (15, "a5"),
549 A6 = (16, "a6"),
550 A7 = (17, "a7"),
551 S2 = (18, "s2"),
552 S3 = (19, "s3"),
553 S4 = (20, "s4"),
554 S5 = (21, "s5"),
555 S6 = (22, "s6"),
556 S7 = (23, "s7"),
557 S8 = (24, "s8"),
558 S9 = (25, "s9"),
559 S10 = (26, "s10"),
560 S11 = (27, "s11"),
561 T3 = (28, "t3"),
562 T4 = (29, "t4"),
563 T5 = (30, "t5"),
564 T6 = (31, "t6"),
565
566 FT0 = (32, "ft0"),
567 FT1 = (33, "ft1"),
568 FT2 = (34, "ft2"),
569 FT3 = (35, "ft3"),
570 FT4 = (36, "ft4"),
571 FT5 = (37, "ft5"),
572 FT6 = (38, "ft6"),
573 FT7 = (39, "ft7"),
574 FS0 = (40, "fs0"),
575 FS1 = (41, "fs1"),
576 FA0 = (42, "fa0"),
577 FA1 = (43, "fa1"),
578 FA2 = (44, "fa2"),
579 FA3 = (45, "fa3"),
580 FA4 = (46, "fa4"),
581 FA5 = (47, "fa5"),
582 FA6 = (48, "fa6"),
583 FA7 = (49, "fa7"),
584 FS2 = (50, "fs2"),
585 FS3 = (51, "fs3"),
586 FS4 = (52, "fs4"),
587 FS5 = (53, "fs5"),
588 FS6 = (54, "fs6"),
589 FS7 = (55, "fs7"),
590 FS8 = (56, "fs8"),
591 FS9 = (57, "fs9"),
592 FS10 = (58, "fs10"),
593 FS11 = (59, "fs11"),
594 FT8 = (60, "ft8"),
595 FT9 = (61, "ft9"),
596 FT10 = (62, "ft10"),
597 FT11 = (63, "ft11"),
598});
599
600/// Intel i386 architecture specific definitions.
601///
602/// See Intel386 psABi version 1.1 at the [X86 psABI wiki](https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI).
603#[derive(Debug, Clone, Copy)]
604pub struct X86;
605
606registers!(X86, {
607 EAX = (0, "eax"),
608 ECX = (1, "ecx"),
609 EDX = (2, "edx"),
610 EBX = (3, "ebx"),
611 ESP = (4, "esp"),
612 EBP = (5, "ebp"),
613 ESI = (6, "esi"),
614 EDI = (7, "edi"),
615
616 // Return Address register. This is stored in `0(%esp, "")` and is not a physical register.
617 RA = (8, "RA"),
618
619 ST0 = (11, "st0"),
620 ST1 = (12, "st1"),
621 ST2 = (13, "st2"),
622 ST3 = (14, "st3"),
623 ST4 = (15, "st4"),
624 ST5 = (16, "st5"),
625 ST6 = (17, "st6"),
626 ST7 = (18, "st7"),
627
628 XMM0 = (21, "xmm0"),
629 XMM1 = (22, "xmm1"),
630 XMM2 = (23, "xmm2"),
631 XMM3 = (24, "xmm3"),
632 XMM4 = (25, "xmm4"),
633 XMM5 = (26, "xmm5"),
634 XMM6 = (27, "xmm6"),
635 XMM7 = (28, "xmm7"),
636
637 MM0 = (29, "mm0"),
638 MM1 = (30, "mm1"),
639 MM2 = (31, "mm2"),
640 MM3 = (32, "mm3"),
641 MM4 = (33, "mm4"),
642 MM5 = (34, "mm5"),
643 MM6 = (35, "mm6"),
644 MM7 = (36, "mm7"),
645
646 MXCSR = (39, "mxcsr"),
647
648 ES = (40, "es"),
649 CS = (41, "cs"),
650 SS = (42, "ss"),
651 DS = (43, "ds"),
652 FS = (44, "fs"),
653 GS = (45, "gs"),
654
655 TR = (48, "tr"),
656 LDTR = (49, "ldtr"),
657
658 FS_BASE = (93, "fs.base"),
659 GS_BASE = (94, "gs.base"),
660});
661
662/// AMD64 architecture specific definitions.
663///
664/// See x86-64 psABI version 1.0 at the [X86 psABI wiki](https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI).
665#[derive(Debug, Clone, Copy)]
666pub struct X86_64;
667
668registers!(X86_64, {
669 RAX = (0, "rax"),
670 RDX = (1, "rdx"),
671 RCX = (2, "rcx"),
672 RBX = (3, "rbx"),
673 RSI = (4, "rsi"),
674 RDI = (5, "rdi"),
675 RBP = (6, "rbp"),
676 RSP = (7, "rsp"),
677
678 R8 = (8, "r8"),
679 R9 = (9, "r9"),
680 R10 = (10, "r10"),
681 R11 = (11, "r11"),
682 R12 = (12, "r12"),
683 R13 = (13, "r13"),
684 R14 = (14, "r14"),
685 R15 = (15, "r15"),
686
687 // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
688 RA = (16, "RA"),
689
690 XMM0 = (17, "xmm0"),
691 XMM1 = (18, "xmm1"),
692 XMM2 = (19, "xmm2"),
693 XMM3 = (20, "xmm3"),
694 XMM4 = (21, "xmm4"),
695 XMM5 = (22, "xmm5"),
696 XMM6 = (23, "xmm6"),
697 XMM7 = (24, "xmm7"),
698
699 XMM8 = (25, "xmm8"),
700 XMM9 = (26, "xmm9"),
701 XMM10 = (27, "xmm10"),
702 XMM11 = (28, "xmm11"),
703 XMM12 = (29, "xmm12"),
704 XMM13 = (30, "xmm13"),
705 XMM14 = (31, "xmm14"),
706 XMM15 = (32, "xmm15"),
707
708 ST0 = (33, "st0"),
709 ST1 = (34, "st1"),
710 ST2 = (35, "st2"),
711 ST3 = (36, "st3"),
712 ST4 = (37, "st4"),
713 ST5 = (38, "st5"),
714 ST6 = (39, "st6"),
715 ST7 = (40, "st7"),
716
717 MM0 = (41, "mm0"),
718 MM1 = (42, "mm1"),
719 MM2 = (43, "mm2"),
720 MM3 = (44, "mm3"),
721 MM4 = (45, "mm4"),
722 MM5 = (46, "mm5"),
723 MM6 = (47, "mm6"),
724 MM7 = (48, "mm7"),
725
726 RFLAGS = (49, "rFLAGS"),
727 ES = (50, "es"),
728 CS = (51, "cs"),
729 SS = (52, "ss"),
730 DS = (53, "ds"),
731 FS = (54, "fs"),
732 GS = (55, "gs"),
733
734 FS_BASE = (58, "fs.base"),
735 GS_BASE = (59, "gs.base"),
736
737 TR = (62, "tr"),
738 LDTR = (63, "ldtr"),
739 MXCSR = (64, "mxcsr"),
740 FCW = (65, "fcw"),
741 FSW = (66, "fsw"),
742
743 XMM16 = (67, "xmm16"),
744 XMM17 = (68, "xmm17"),
745 XMM18 = (69, "xmm18"),
746 XMM19 = (70, "xmm19"),
747 XMM20 = (71, "xmm20"),
748 XMM21 = (72, "xmm21"),
749 XMM22 = (73, "xmm22"),
750 XMM23 = (74, "xmm23"),
751 XMM24 = (75, "xmm24"),
752 XMM25 = (76, "xmm25"),
753 XMM26 = (77, "xmm26"),
754 XMM27 = (78, "xmm27"),
755 XMM28 = (79, "xmm28"),
756 XMM29 = (80, "xmm29"),
757 XMM30 = (81, "xmm30"),
758 XMM31 = (82, "xmm31"),
759
760 K0 = (118, "k0"),
761 K1 = (119, "k1"),
762 K2 = (120, "k2"),
763 K3 = (121, "k3"),
764 K4 = (122, "k4"),
765 K5 = (123, "k5"),
766 K6 = (124, "k6"),
767 K7 = (125, "k7"),
768});
769