| 1 | // Targets the Cortex-M4F and Cortex-M7F processors (ARMv7E-M) |
|---|---|
| 2 | // |
| 3 | // This target assumes that the device does have a FPU (Floating Point Unit) and lowers all (single |
| 4 | // precision) floating point operations to hardware instructions. |
| 5 | // |
| 6 | // Additionally, this target uses the "hard" floating convention (ABI) where floating point values |
| 7 | // are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.). |
| 8 | // |
| 9 | // To opt into double precision hardware support, use the `-C target-feature=+fp64` flag. |
| 10 | |
| 11 | use crate::spec::{FloatAbi, Target, TargetMetadata, TargetOptions, base}; |
| 12 | |
| 13 | pub(crate) fn target() -> Target { |
| 14 | Target { |
| 15 | llvm_target: "thumbv7em-none-eabihf".into(), |
| 16 | metadata: TargetMetadata { |
| 17 | description: Some("Bare ARMv7E-M, hardfloat".into()), |
| 18 | tier: Some(2), |
| 19 | host_tools: Some(false), |
| 20 | std: Some(false), |
| 21 | }, |
| 22 | pointer_width: 32, |
| 23 | data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), |
| 24 | arch: "arm".into(), |
| 25 | |
| 26 | options: TargetOptions { |
| 27 | abi: "eabihf".into(), |
| 28 | llvm_floatabi: Some(FloatAbi::Hard), |
| 29 | // vfp4 is the lowest common denominator between the Cortex-M4F (vfp4) and the |
| 30 | // Cortex-M7 (vfp5). |
| 31 | // Both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers |
| 32 | // available, and the Cortex-M4 only supports single-precision floating point operations |
| 33 | // whereas in the Cortex-M7 double-precision is optional. |
| 34 | // |
| 35 | // Reference: |
| 36 | // ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension |
| 37 | features: "+vfp4d16sp".into(), |
| 38 | max_atomic_width: Some(32), |
| 39 | ..base::thumb::opts() |
| 40 | }, |
| 41 | } |
| 42 | } |
| 43 |
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